JP5762893B2 - Key storage circuit, semiconductor integrated circuit, and system - Google Patents

Description

  The present invention relates to a key storage circuit, a semiconductor integrated circuit, and a system, and more particularly, to a key storage circuit, a semiconductor integrated circuit, and a system for storing a key used for encryption and decryption.

  In general, an LSI (semiconductor integrated circuit) in which a key (hereinafter simply referred to as a key) used for encryption and decryption of a data signal is mounted in a nonvolatile memory is known. In order to use a typical EPROM or FLASH memory as a non-volatile memory for key implementation, it is necessary to use a memory-mixed process or to make a multichip module in which a plurality of chips are enclosed in one package. In any case, there are problems in terms of cost, technology, etc., so it is impractical to use the memory only for mounting the key.

  Therefore, a technique is known in which a fuse that can be used in a normal process is used instead of the above-described nonvolatile memory, and a key is mounted on the fuse. For example, Patent Document 1 describes a technique for storing a secure key value in a fuse included in a processing device.

An example in which a key is mounted on a fuse is shown in FIG. An LSI (semiconductor integrated circuit) 100 mounted on a chip (substrate) 112 shown in FIG. 9 includes a key storage block 120 for storing a key. The key storage block 120 has a number of fuse memory cells 130 corresponding to the bit length of the key to be mounted. In the case of the key storage block 120 shown in FIG. 9, n fuse memory cells 130 (130 _{n-1 to} 130 ₀ ) are mounted according to the bit length n of the key. The fuse memory cell 130 includes a fuse 132 connected to the power supply voltage VDD side of the LSI 100 and a fuse 134 connected to the GND (GND of the LSI 100) side. By electrically disconnecting either the fuse 132 or the fuse 134, the output value of the fuse memory cell 130 is determined to be either VDD or GND.

  The key is mounted by cutting one of the fuse 132 and the fuse 134 of each fuse memory cell 130 in a wafer level test process of the LSI 100 or the like. When the fuse 132 connected to the VDD side is cut, the output of the fuse memory cell 130 is fixed to “0”. On the other hand, when the fuse 134 connected to the GND side is cut, the output of the fuse memory cell 130 is fixed to “1”. Therefore, by cutting any fuse (132, 134) of the fuse memory cell 130, the key key [n-1: 0], which is the output value of the key storage block 120, is determined. By changing the combination of cutting the fuses depending on the user who uses the LSI 100 and the application, it is possible to implement a unique key with a unique value.

JP 2009-135905 A

  When a key is mounted on a fuse as described above, since one fuse memory cell 130 corresponds to one bit of the key, the number of fuse memory cells corresponding to the bit length of the key (number equal to the bit length) 130 must be installed.

  Although the method of mounting the key on the fuse has an advantage that it can be realized by an inexpensive normal process as compared with the case of mounting the key on the nonvolatile memory described above, one fuse (fuse 132 or fuse 134) is 10 μm square. Therefore, if the bit length of the key to be mounted is long, the number of fuse memory cells 130 (fuses 132 and 134) to be mounted increases, and as a result, the chip size (area) increases. Cost may be high.

  In addition, as described above, the fuse memory cell 130 and the key value have a one-to-one correspondence, and the trace of the fuse can be easily confirmed visually or with a microscope, so that the key information can be easily guessed. There was a security problem.

  The present invention has been proposed to solve the above-described problem, and provides a key storage circuit, a semiconductor integrated circuit, and a system that can make it difficult to estimate a stored key value. Objective.

To achieve the above object, key storage circuit according to claim 1, Ru is stored first predetermined value at least one of a fuse, and in accordance with the cutting state of the fuse And a storage means having a key mounting fuse for mounting a part of a key for encrypting or decrypting a data signal, a storage means storing a predetermined second value, and the storage means A key obtained by executing a predetermined calculation using the first value stored and the second value stored in the storage means; and mounted on the key mounting fuse. And a key generation circuit for generating a key for encrypting or decrypting the data signal.

The semiconductor integrated circuit according to claim 10 comprises a substrate and, mounted on the substrate, and the key storage circuit according to any one of 請 Motomeko 1 or et請 Motomeko 9, a.

The system of claim 12, based on the stored in the key storage circuit key, a semiconductor according to 請 Motomeko 10 with an encrypted signal generating circuit for generating an encrypted signal by encrypting the data signal an integrated circuit, based on the key stored in the key storage circuit, a semiconductor integrated circuit according to 請 Motomeko 10 for decrypting said encrypted signal with a decoding signal generation circuit for generating the data signal .

  According to the present invention, it is possible to make it difficult to estimate a stored key value.

1 is a schematic configuration diagram showing an example of a schematic configuration of an LSI (semiconductor integrated circuit) according to a first embodiment. It is a circuit diagram which shows an example of schematic structure of the key storage block which concerns on 1st Embodiment. It is a schematic block diagram which shows an example of schematic structure of the key generation circuit which concerns on 1st Embodiment. It is a circuit diagram which shows an example of schematic structure of the key storage block which concerns on 2nd Embodiment. It is a schematic block diagram which shows an example of schematic structure of the key generation circuit which concerns on 2nd Embodiment. It is a circuit diagram which shows an example of schematic structure of the key storage block which concerns on 3rd Embodiment. It is a circuit diagram which shows an example of schematic structure of the key storage block which concerns on 4th Embodiment. It is a schematic block diagram which shows an example of schematic structure of LSI (semiconductor integrated circuit) for encrypting a data signal. It is a circuit diagram which shows an example of schematic structure of the conventional key storage block.

  [First Embodiment]

  Hereinafter, a key storage block (key storage circuit) and an LSI (Large Scale Integration: semiconductor integrated circuit, hereinafter simply referred to as LSI) including the key storage block according to the first embodiment will be described in detail with reference to the drawings. . In the present embodiment, a case will be described in which a data signal (encrypted data signal) previously encrypted with a key is decrypted using the key.

  First, the configuration of the LSI of this embodiment will be described. An example of a schematic configuration of the LSI according to the present embodiment is shown in FIG. The LSI 10 of this embodiment shown in FIG. 1 includes a data signal decryption circuit 14 and a key storage block 20 mounted on a chip (substrate, hereinafter simply referred to as a chip) 12.

  In the LSI 10 of this embodiment, an encrypted data signal obtained by encrypting a data signal with a key is input from the outside. The data signal decryption circuit 14 decrypts the input encrypted data signal using a key stored in the key storage block 20 by a predetermined decryption method (original data signal). It has a function to output. Note that the data signal of the present embodiment is not particularly limited, for example, a video signal or a signal including personal information. In addition, the decoding method performed by the data signal decoding circuit 14 may be a generally used method or the like, and is not particularly limited. A processing circuit that uses the decoded data signal output from the data signal decoding circuit 14 may be mounted in the LSI 10 or may be provided outside the LSI 10 and is particularly limited. It is not a thing.

  The key storage block 20 according to the present embodiment has a function of storing a key used for decryption (encryption) of a data signal, and includes a fuse block 22 and a key generation circuit 24. Yes. FIG. 2 shows a circuit diagram of an example of a schematic configuration of the key storage block 20 of the present embodiment.

The key storage block 20 of the present embodiment includes a fuse block 22 having a plurality (k in this embodiment) of fuse memory cells 30 (30 _k−1 to 30 ₀ ) and a key generation circuit 24. ing. The fuse memory cell 30 includes a fuse 32 connected to the power supply voltage VDD side of the LSI 10 and a fuse 34 connected to the GND (GND of the LSI 10) side. In the present embodiment, as a specific example, the key storage block 20 stores an n-bit key.

  In the present embodiment, by cutting one of the fuse 32 and the fuse 34 included in the fuse memory cell 30 of the fuse block 22 in the wafer level test process of the LSI 10, the output value of the fuse memory cell 30 is It is determined to be either VDD or GND. In the present embodiment, the “cutting” of the fuses (32, 34) may be at least electrically cut, and may not be physically cut.

  In the present embodiment, as a specific example, when the fuse 32 connected to the VDD side is cut, the output of the fuse memory cell 30 is fixed to “0”. On the other hand, when the fuse 34 connected to the GND side is cut, the output of the fuse memory cell 30 is fixed to “1”. By cutting the fuses (32, 34) in this way, the fixed output value fout [k−1: 0] having a bit length k is output from the fuse block 22 to the key generation circuit 24. In the present embodiment, the fixed output value fout [k−1: 0] and the key (key [n−1: 0]) generated by the decryptor 42 have a one-to-one correspondence (details). Later).

  Note that the fuse block 22 according to the present embodiment is mounted with information for decrypting the key, and is not mounted with key information (key value) itself. Therefore, the number of fuse memory cells 30 provided in the fuse block 22 of the present embodiment does not depend on the key bit length n. Therefore, the number of fuse memory cells 30 can be made smaller than the key bit length n. Therefore, in this embodiment, k <n.

In the present embodiment, the number of fuse memory cells 30 to be mounted depends on the number of unique keys that can be stored by the fuse block 22. As a specific example, if you set the number of unique keys 16, since the number of fuse memory cell 30 to be mounted is 16 = 2 ^4, the four. Therefore, in such a case, the number of fuse memory cells 30 mounted in the key storage block 20 is four regardless of whether the bit length n of the key stored in the key storage block 20 is 192 bits or 256 bits. It's okay. Therefore, in the LSI 10 (key storage block 20), only the method of cutting the fuses (32, 34) of the four fuse memory cells 30 is changed, and the 16 unique keys are independent of the bit length n of the key. It can correspond to.

  An example of a schematic configuration of the key generation circuit 24 of the present embodiment is shown in FIG. The key generation circuit 24 according to the present embodiment shown in FIG. 1 includes a register 40 and a decoder 42. The register 40 of this embodiment outputs a fixed value stored in advance. The register 40 only needs to be a logic circuit that can store a fixed value in advance. For example, a register constituted by a circuit element such as a flip-flop can be used, and its type is particularly limited. It is not a thing. A register used in another processor other than the key generation circuit 24 may be used as the register 40. The capacity and the like of the register 40 are not particularly limited, but when configured as a register dedicated to the present embodiment (storage of a fixed value for generating a key), the capacity may be set according to the fixed value. By making the size as small as possible, an increase in chip size and an increase in cost can be suppressed.

  Note that an EPROM, a flash memory, or the like may be used instead of the register 40. However, when the register 40 is used, the degree of freedom of setting in the post-mounting process can be increased and processing can be performed at higher speed. Therefore, it is preferable.

  The decoder 42 of the present embodiment includes an arithmetic processing circuit (this embodiment) that performs predetermined arithmetic processing using the fixed output value fout [k−1: 0] of the fuse block 22 and the output value of the register 40. A logic circuit in the form, and has a function of generating and outputting a key (key [n-1: 0]) having a unique bit length n unique to each LSI 10 by executing the arithmetic processing. ing.

  The arithmetic processing performed by the decoder 42 generates a key (key [n-1: 0]) having a bit length n from the fixed output value fout [k-1: 0] of the fuse block 22 and the output value of the register 40. Any calculation process can be used, and any process that performs a predetermined process such as addition / subtraction / division / division may be performed, and is not particularly limited. In the arithmetic processing of the present embodiment, the bit length n of the key key [n-1: 0] is longer than the bit length k of the fixed output value fout [k-1: 0] input to the decoder 42. Become.

  For example, since the fixed value mounted on the fuse block 22 can be confirmed visually or with a microscope, it may be better if the number is smaller than the key value itself. On the other hand, a larger number of fuse blocks 22 can increase the degree of freedom to set in a post-mounting process such as a wafer level test. Further, if the number of bits of the value stored in the register 40 is increased, the entire circuit of the register 40 becomes larger, which may increase the area of the key storage block 20 (LSI 10) and increase the cost.

  Therefore, the fixed output value fout [k−1: 0] mounted in the fuse block 22, the fixed value stored in the register 40, and the calculation processing method are the fixed output value fout output from the fuse block 22. The bit length k of [k-1: 0], the bit length n of the key key [n-1: 0], the specifications of the LSI 10, the security desired by the user, and the cost may be determined.

  As described above, the key storage block 20 mounted on the LSI 10 of the present embodiment includes the fuse block 22 having k fuse memory cells 30 and the key generation circuit 24. Outputs a fixed output value fout [k-1: 0] having a bit length k that is mounted in advance. The key generation circuit 24 is configured to include a register 40 and a decryptor 42. The decryptor 42 uses a fixed output value fout [k-1: 0] and an output value of the register 40 by arithmetic processing. A key key [n-1: 0] having a bit length n (n> k) is generated and output.

  As described above, in the key storage block 20 of the present embodiment, the key itself is not stored in the fuse block 22, but the LSI 10 (key storage block 20) is based on the fixed output value fout stored in the fuse block 22. Therefore, even when the fuse block 22 is confirmed visually or with a microscope, it is difficult to estimate the key value, and high security can be ensured.

  In the present embodiment, the number of fuse memory cells 30 does not depend on the bit length k of the key and does not correspond one-to-one, so the number is smaller than the bit length k of the key to be stored. Can do. Therefore, even if the bit length k of the key to be mounted increases, the number of fuse memory cells 30 mounted on the key storage block 20 (LSI 10) does not change, and an increase in chip size and cost can be suppressed. In particular, it is preferable to increase the bit length k of the key from the viewpoint of security. However, it is only necessary to change the method of arithmetic processing and the value stored in the register 40, and the number of fuse memory cells 30 can be changed. Since it is not necessary to increase, increase in chip size and cost can be suppressed.

  Also, by changing the combination for cutting the fuses (32, 34) of the fuse memory cell 30, it is possible to mount a key having a unique value depending on the number of the fuse memory cells 30.

  [Second Embodiment]

  Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. In addition, about the structure and operation | movement substantially the same as 1st Embodiment, that is described and detailed description is abbreviate | omitted. In the present embodiment, the register of the key generation circuit stores a plurality of fixed values, and the decoder uses any one of the plurality of fixed values for the arithmetic processing.

An example of a schematic configuration of an LSI (chip) on which the key storage block of this embodiment is mounted is shown in FIG. In the key storage block 53 of this embodiment, the fuse block 22, the register selection block 56, and the key generation circuit 58 are mounted on the chip 12. An example of a schematic configuration of the key generation circuit 58 of the present embodiment is shown in FIG. The key generation circuit 58 of the present embodiment is configured to include a register 41 and a decryptor 43 that include _x memories 45 (45 _{1 to} 45 _x ). In the present embodiment, the memory 45 is referred to as a “memory”, but is a memory (similar to a so-called register) configured by a logic circuit.

The register selection block 56 has a function of outputting a fixed output value (fout [k + 1: k]) that is a selection signal having a bit length 1 for selecting any of the x memories 45 included in the register 41. ing. Therefore, the same number of fuse memory cells 30 (30 _{k + 1} to 30 _k ) as the bit length l of the selection signal are provided, and selection signal information is mounted. The method of mounting the selection signal information of the fuse memory cell 30 is the same as the method of mounting the fixed output value in the fuse block 22, and either the fuse 32 or the fuse 34 of the fuse memory cell 30 is cut. To confirm the output. Further, the mounting timing may be the same as the mounting timing of the fixed output value in the fuse block 22 or may be different.

  The decryptor 43 includes a selection circuit 46 and a key decryption circuit 47. The selection circuit 46 selects one of the output values of the memory 45 of the register 41 based on the selection signal fout [k + 1: k] output from the register selection block 56 and outputs the selected value to the key decryption circuit 47. have.

  The key decryption circuit 47 generates a key key [n-1: 0] having a bit length k by arithmetic processing from the output value output from the selection circuit 46 and the fixed output value fout [k-1: 0]. And output. Note that the calculation process of the key decryption circuit 47 is substantially the same process as the decryption unit 42 of the first embodiment, and therefore detailed description thereof is omitted here.

  As described above, in this embodiment, the key generation circuit 58 includes the x memories 45, and information indicating which memory 45 is selected is stored in the fuse memory cell 30 of the register selection block 56. . Therefore, in addition to the same effects as those of the first embodiment, it is possible to make it difficult to estimate the key value.

  In addition, the number of unique keys corresponding to the number of memories 45 included in the register 41 can be generated. As a result, it is possible to deal with a plurality of users and user specifications only by changing the selection signal information mounted on the register selection block 56, so that the degree of freedom can be further increased.

  In this embodiment, the configuration in which the selection signal information is mounted in the register selection block 56 has been described. However, the present invention is not limited to this, and the selection signal information is stored (mounted) in a storable medium such as another memory without using a fuse. It may be.

  [Third Embodiment]

  Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. In addition, about the structure and operation | movement substantially the same as 1st Embodiment, that is described and detailed description is abbreviate | omitted. In the present embodiment, the key generation circuit generates a part of the key stored in the key storage block.

  An example of a schematic configuration of an LSI on which the key storage block of this embodiment is mounted is shown in FIG. The key storage block 63 of the present embodiment includes a fuse block 64, a key storage sub-block 66, and a key generation circuit 68.

In the fuse block 64 of the present embodiment, information for generating a key having a bit length m out of keys having a bit length k is mounted. Therefore, i fuse memory cells 30 (30 _i−1 to 30 ₀ ) are mounted in the fuse block 64. As in the first embodiment, since the number i of the fuse memory cells 30 to be mounted is smaller than the bit length m of the key generated by the key generation circuit 68, i <m.

  The key generation circuit 68 of the present embodiment has substantially the same configuration and operation as the key generation circuit 24 of the first embodiment, and the fixed output value fout output from the fuse block 64 by arithmetic processing. A key key [m-1: 0] having a bit length m (m> i) is generated from [i-1: 0] and the output value of the register 40 and output.

In the present embodiment, a part of the key (in this embodiment, a key for nm bits) is mounted in the fuse memory cell 30 (30 _n−1 to 30 _m ) of the key storage sub-block 66. Has been. Note that the method of mounting the key of the fuse memory cell 30 in the key storage sub-block 66 is the same as the method of mounting the fixed output value in the fuse block 22, and either the fuse 32 or the fuse 34 of the fuse memory cell 30 is used. The output is determined by disconnecting. Further, the mounting timing may be the same as the mounting timing of the fixed output value in the fuse block 22 or may be different.

  The key storage block 63 combines a bit length n−m key mounted in the fuse memory cell 30 of the key storage sub-block 66 with a bit length m key generated by the key generation circuit 68 to generate a bit length n. Is output to the data signal decryption circuit 14 as a key of. In the key storage block 63 of this embodiment, the bit length m-m key mounted in the key storage sub-block 66 is added to the bit length m key generated by the key generation circuit 68 as it is. Although they are combined, the way of combining is not limited to this. It should be noted that, by using different combinations, the key values to be stored (output) can be made different even in the key storage block 63 in which the same fuse block 64 and key storage sub-block 66 are mounted. Further, a combination circuit for combining the two may be provided in the key storage block 63, and the combination may be performed by the circuit.

  Thus, in this embodiment, a part of the key (bit length nm in this embodiment) is mounted on the fuse memory cell 30 of the key storage sub-block 66, and the rest (bit length m in this embodiment). In the same manner as in the first embodiment, the key generation circuit 68 outputs a fixed output value fout [i−1: 0] having a bit length i output from the fuse block 64 by the arithmetic processing and the output value of the register 40 as in the first embodiment. Generated from and output. The key storage block 63 combines the key output from the key storage sub-block 66 and the key output from the key generation circuit 68 into a final key (key key [k-1: 0] having a bit length k). Is output.

  Therefore, as in the first embodiment, the total number of fuse memory cells 30 mounted in the key storage block 63 can be made equal to or less than the bit length k of the final low key, which increases the chip size. And increase in cost can be suppressed.

  Further, since only a part of the final key is mounted on the fuse memory cell 30, it is difficult to guess the key value as in the first embodiment.

  Furthermore, in this embodiment, since a part of the key is mounted in the fuse memory cell 30 of the key storage sub-block 66, the value of the key (final key) is set after the wafer process according to the user's desire or the like. You can change it or increase the number of keys. Further, since it can be changed after the wafer process rather than being mounted during the wafer process, it becomes easier to set the key value and the degree of freedom is increased.

  [Fourth Embodiment]

  Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. In addition, about the structure and operation | movement substantially the same as 1st Embodiment, that is described and detailed description is abbreviate | omitted. In the present embodiment, the fixed output value fout [i−1: 0] output from the fuse block is switched by the timer.

  An example of a schematic configuration of an LSI on which the key storage block of the present embodiment is mounted is shown in FIG. On the chip 72 of the LSI 70 of the present embodiment, a key storage block 73 and a document size estimation unit 76 are mounted. The key storage block 73 according to the present embodiment includes a fuse block 74 and a key generation circuit 24.

  In the fuse block 22, in addition to the configuration of the fuse block 22 of the first embodiment, a circuit 77 composed of a pair of PMOS transistors and NMOS transistors for switching the connection destination of the fuse memory cell 30, and a similar circuit 78 And an inverting circuit 79. When an “H” level signal is output from the timer 76, the circuit 77 connects the fuse 34 of the fuse memory cell 30 to GND. Meanwhile, the circuit 78 connects the fuse 32 of the fuse memory cell 30 to the power supply voltage VDD. Further, when an “L” level signal is output from the timer 76, the circuit 77 connects the fuse 34 of the fuse memory cell 30 to the power supply voltage VDD. On the other hand, the circuit 32 connects the fuse 32 of the fuse memory cell 30 to GND. Therefore, the output value “1” or “0” of the fuse memory cell 30 is switched according to the level of the signal output from the timer 76.

  As described above, in the present embodiment, the power supply voltage VDD to which the fuse 32 and the fuse 34 of the fuse memory cell 30 of the fuse block 74 are connected is switched according to the level of the signal output from the timer 76. it can. Thereby, the fixed output value fout [i−1: 0] of the fuse block 74 can be switched according to the level of the signal output from the timer 76. Specifically, “1” and “0” of each bit of the fixed output value fout [i−1: 0] can be inverted. Therefore, the key value key [k−1: 0] generated and output by the key generation circuit 24 can be changed according to the level of the signal output from the timer 76.

  Therefore, the same effect as the first embodiment can be obtained, and it becomes difficult to estimate the key value, and higher security can be ensured.

  The operation of the timer 76 (operation for changing the level of the output signal) is not particularly limited. Note that when the LSI 10 on the transmission side of the encrypted data signal and the LSI 10 on the reception side know the timing for changing the key, for example, when the timer 76 operating in the same cycle is mounted, It is preferable to configure the system so that an encrypted data signal encrypted by changing the key at a timing grasped from the LSI 10 on the side is transmitted to the LSI 10 on the reception side. By doing so, higher security can be ensured.

  In each of the above-described embodiments, the fuse memory cell 30 is provided with “1” or “0” by providing the fuse 32 and the fuse 34. However, the present invention is not limited to this. For example, only one fuse is provided. Depending on whether or not the fuse is cut, it may be mounted.

  In each of the embodiments described above, the decrypted data signal (original data signal) obtained by decrypting the encrypted data signal by the data signal decryption circuit 14 based on the key stored in the key storage block 20 is used. Although the configuration for output (see FIG. 1) has been described, the present invention is not limited to this. As shown in FIG. 8, the key storage block 20 and the data signal encryption circuit 16 are mounted on the LSI 11 (chip 13). Thus, the data signal is encrypted by the data signal encryption circuit 16 using the key stored in the key storage block 20, and the encrypted data signal encryption circuit 16 is transmitted (for example, outside the LSI 11). May be. Also in this case, the encryption method using the key by the data signal encryption circuit 16 may be a generally used method or the like, and is not particularly limited. Further, the LSI 10 which encrypts the data signal shown in FIG. 8 with the key stored in the key storage block 20 and transmits the encrypted data signal, and the encrypted data signal shown in FIG. It goes without saying that it is preferable to configure a system that combines the LSI 10 that decrypts with the key.

  The configurations of the LSI, the key storage block, the fuse block, the key generation circuit, etc. described in each of the above-described embodiments are examples, and may be changed according to the situation without departing from the gist of the present invention. Needless to say. Moreover, you may use combining each embodiment mentioned above.

10 LSI (semiconductor integrated circuit)

Claims (12)

It has at least one or more fuses, and implement some of the key for encrypting or decrypting Rutotomoni, the data signal a first value is stored which is determined in advance according to the disconnected state of the fuse Storage means with a key mounting fuse to
Storage means for storing a predetermined second value;
A key obtained by executing a predetermined operation using the first value stored in the storage means and the second value stored in the storage means; and the key-mounted fuse A key generation circuit that generates a key for encrypting or decrypting the data signal by combining the key implemented in
A key storage circuit. The bit length of the first value stored in the storage means, bits obtained by subtracting the bit length of the part of the key that is mounted on the key mount fuse from the bit length of the key generated by the key generating circuit The key storage circuit according to claim 1, wherein the key storage circuit is shorter than the length .   The storage unit includes a plurality of storage units, and the storage unit includes a specifying unit that specifies which of the plurality of storage units is used for the calculation. The key storage circuit described.   The key storage circuit according to claim 3, wherein the specifying unit includes a fuse for mounting information specifying which storage unit is used for the operation. It said storage means has one end connected to the power supply voltage, and the other end connected fuse and one end to the output terminal is connected to the ground voltage, and a pair of fuse fuse the other end of which is connected to the output terminal A fuse cell, wherein the fuse cell has one of the pair of fuses cut,
The key storage circuit according to any one of claims 1 to 4 . Further comprising a first output and for outputting a power supply voltage and the ground voltage are switched complementarily switching means and a second output,
The storage means has one end connected to the first output and the other end connected to the output terminal, one end connected to the second output, and the other end connected to the output terminal. A fuse cell comprising a pair of fuses, wherein the fuse cell has one of the pair of fuses cut;
The key storage circuit according to any one of claims 1 to 4 . The key storage circuit according to claim 6 , wherein the switching unit repeatedly switches the connection destination at a predetermined timing. It said storage means is composed of a logic circuit, a key storage circuit according to any one of claims 1 to 7. The storage means is a register, the key storage circuit as claimed in any one of claims 8. A substrate,
Mounted on the substrate, and the key storage circuit according to any one of 請 Motomeko 1 or et請 Motomeko 9,
A semiconductor integrated circuit. A signal generation circuit that performs at least one of encryption and decryption on a data signal based on a key stored in the key storage circuit;
The semiconductor integrated circuit according to claim 10 . Based on the key stored in the key storage circuit, a semiconductor integrated circuit according to 請 Motomeko 10 with an encrypted signal generating circuit for generating an encrypted signal by encrypting the data signal,
Based on the key stored in the key storage circuit, a semiconductor integrated circuit according to 請 Motomeko 10 having a decoded signal generation circuit for decrypting said encrypted signal to generate the data signal,
With system.

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