JP5789803B2 - Semiconductor memory and system - Google Patents

Description

  The present invention relates to a semiconductor memory and a system in which the semiconductor memory is mounted.

  In order to perform a write operation at high speed and reduce power consumption, a semiconductor memory in which a precharge voltage supplied to a bit line is set lower than a power supply voltage has been proposed (see, for example, Patent Document 1). In order to stably generate the word line voltage when the power supply voltage is low, a semiconductor memory in which a diode-connected pMOS transistor equivalent to the pMOS transistor of the memory cell is arranged between the power supply line and the word driver is proposed. (For example, see Patent Document 2). In order to precharge the data line according to the driving timing of the word line, a semiconductor memory in which a precharge transistor that receives a signal obtained by inverting the output signal of the word decoder at the gate is arranged between the power line and the bit line is proposed. (For example, see Patent Document 3).

JP-A-10-125069 JP 2007-66493 A Japanese Patent Laid-Open No. 11-16356

  For example, when the precharge voltage of the bit line is made lower than the power supply voltage, the voltage of the precharged bit line becomes lower than the high level voltage held in the latch of the memory cell. In this state, when the word line is set to a high level voltage to access the memory cell, and a current flows from the high level node of the memory cell to the bit line via the transfer transistor, one of the data retention characteristics of the memory cell. There is a possibility that the static noise margin is worsened.

  An object of the present invention is to prevent the static noise margin of a memory cell from deteriorating.

  In one embodiment of the present invention, a semiconductor memory is connected to an input / output node through a real memory cell having a latch for storing data, a real transfer transistor connected to the input / output node of the latch, and the real transfer transistor. A bit line, a word line connected to the gate of the real transfer transistor, and a precharge circuit for precharging the bit line, and the precharge circuit is configured to connect the word line at the gate at least when the real memory cell is not accessed. It includes a replica transfer transistor that receives the same first high level voltage as the high level voltage, receives the second high level voltage at the drain, and supplies a precharge voltage generated at the source to the bit line, and has the same structure as the real memory cell. Having a replica memory cell.

  The precharge voltage of the bit line can be set to a value lower than the high level voltage of the word line by the threshold voltage of the transfer transistor, and the static noise margin of the memory cell can be prevented from deteriorating.

1 illustrates an example of a semiconductor memory in one embodiment. The example of the semiconductor memory in another embodiment is shown. The example of the semiconductor memory in another embodiment is shown. The example of the principal part of the semiconductor memory in another embodiment is shown. 5 shows an example of an entire block of the semiconductor memory shown in FIG. 6 shows an example of the word decoder shown in FIG. The example of the principal part of the semiconductor memory in another embodiment is shown. The example of the system by which the semiconductor memory of embodiment mentioned above is mounted is shown.

  Hereinafter, embodiments will be described with reference to the drawings. The same reference numerals as the signal names are used for signal lines through which signals are transmitted. A signal with “X” at the end indicates negative logic. Double square marks indicate external terminals. The external terminal is, for example, a semiconductor macro terminal, a pad on a semiconductor chip, or a lead of a package in which the semiconductor chip is accommodated. For the signal supplied via the external terminal, the same symbol as the terminal name is used.

  FIG. 1 shows an example of a semiconductor memory MEM in one embodiment. For example, the semiconductor memory MEM is an SRAM (Static Random Access Memory). The semiconductor memory MEM may operate in synchronization with the clock signal or may operate asynchronously with the clock signal. The semiconductor memory MEM has a precharge circuit PRE including a memory cell MC, a bit line BIT connected to the memory cell MC, and a replica memory cell RMC connected to the bit line BIT. The memory cell MC is an example of a real memory cell.

  The memory cell MC includes a latch LT that holds data, and a transfer transistor T1 connected to one input / output node ND1 of the latch LT. The transfer transistor T1 is an example of a real transfer transistor. For example, the transfer transistor T1 is an nMOS transistor whose gate is connected to the word line WL. For example, the latch LT has a pair of inverters, and the output of one inverter is connected to the input of the other inverter. For example, the two power terminals of each inverter are connected to the power line VDD and the ground line VSS, respectively. Note that the memory cell MC may include a transfer transistor connected to the other input / output node ND2 of the latch LT. In this case, the memory cell MC is connected to a complementary bit line pair. The power supply voltage VDD supplied to the power supply line VDD may be an external power supply voltage, or may be generated using an external power supply voltage by a voltage generation circuit formed inside the semiconductor memory MEM.

  The replica memory cell RMC has a replica transfer transistor RT1 having a gate connected to the precharge word line PWL and a source connected to the bit line BIT, and a replica latch RLT. The replica memory cell RMC has basically the same structure as the memory cell MC. For example, the element structure of the replica transfer transistor RT1 is the same as the element structure of the transfer transistor T1, and the element structure of the CMOS inverter that forms the replica latch RLT is the same as the element structure of the CMOS inverter that forms the latch LT. The replica transfer transistor RT1 is an nMOS transistor like the transfer transistor T1, and the threshold voltage of the replica transfer transistor RT1 is the same as the threshold voltage of the transfer transistor T1. This is because the replica transfer transistor RT1 in the precharge circuit PRE is formed together with the replica memory cell RMC. That is, the threshold voltage of the real memory cell MC and the replica memory cell RMC can be made the same even if the manufacturing conditions vary.

  For example, in the replica latch RLT, one input / output node RND1 connected to the drain of the replica transfer transistor RT1 is connected to the power supply line VDD, and the other input / output node RND2 is connected to the ground line VSS. The power supply voltage VDD supplied to the input / output node RND1 is an example of a second high level voltage. For example, the two power terminals of each inverter of the replica latch RLT are connected to the power line VDD and the ground line VSS, respectively. Note that the replica latch RLT may fix each input of the inverter pair to a high level or a low level and set each output of the inverter pair to an open state. In this case, the node (that is, the drain) on the replica latch RLT side of the replica transfer transistor RT1 is directly connected to the power supply line VDD. 1 shows an example in which the power supply line VDD and the ground line VSS are connected to the pair of inverters of the replica latch RLT, respectively, these inverters may not be connected to the power supply line VDD or the ground line VSS. . In this case, for example, the drain of the replica transfer transistor RT1 is disconnected from the replica latch RLT and connected only to the power supply line VDD.

  For example, the high level voltage of the word line WL is the power supply voltage VDD. The precharge word line PWL is set to the same power supply voltage VDD as the high level voltage of the word line WL at least when the memory cell MC is not accessed. The power supply voltage VDD supplied to the word line WL and the precharge word line PWL is an example of a first high level voltage.

  When the precharge word line PWL is set to the power supply voltage VDD, the bit line BIT is precharged to a voltage lower than the power supply voltage VDD by the threshold voltage of the replica transfer transistor RT1 via the replica transfer transistor RT1. When the threshold voltage of the transfer transistor T1 and the replica transfer transistor RT1 is Vth, the precharge voltage of the bit line BIT is VDD−Vth.

  When logic 1 is stored in the memory cell MC, the input / output node ND1 is at the high level voltage VDD, and the input / output node ND2 is at the low level VSS. When the word line WL is set to the high level voltage VDD in this storage state, the gate-source voltage of the transfer transistor T1 becomes Vth (= VDD− (VDD−Vth)). Here, the source of the transfer transistor T1 is connected to the bit line BIT. Since the voltage of the bit line BIT is always maintained at VDD-Vth, the gate-source voltage of the transfer transistor T1 does not exceed Vth. For this reason, the transfer transistor T1 maintains an off state, and even if there is a voltage difference between the drain and source, almost no current flows from the input / output node ND1 to the bit line BIT. On the other hand, in order to maintain the input / output node ND1 at the high level, a power supply current is supplied from the latch LT to the input / output node ND1.

  Therefore, even if the word line WL is maintained at the high level voltage VDD, the high level voltage of the input / output node ND1 is not lowered by the leakage current of the transfer transistor T1, and the logic held in the memory cell MC is inverted. Can be prevented. In this embodiment, the difference between the high level voltage of the word line WL and the precharge voltage of the bit line BIT is always the same value as the threshold voltage Vth of the transfer transistor. Therefore, even when the precharge voltage of the bit line BIT is lower than the power supply voltage VDD supplied to the latch LT of the memory cell MC, the transfer transistor T1 can be prevented from being turned on, and the static noise margin of the memory cell MC is reduced. It can be prevented from decreasing. Here, the static noise margin is a data retention margin of the memory cell MC when the word line WL is set to a high level voltage.

  When the manufacturing conditions of the semiconductor memory MEM fluctuate, the threshold voltage Vth of the replica transfer transistor RT1 changes with the threshold voltage Vth of the transfer transistor T1. For this reason, the precharge voltage of the bit line BIT can always be set to a value lower than the high level voltage of the word line WL by the threshold voltage Vth regardless of variations in manufacturing conditions. Even when the power supply voltage VDD fluctuates or the operating temperature fluctuates, the precharge voltage of the bit line BIT is set to a value lower than the high level voltage of the word line WL by the threshold voltage Vth of the transfer transistor T1. Can always be set. Therefore, it is possible to prevent the transfer transistor T1 from being turned on regardless of variations in manufacturing conditions, power supply voltage VDD, and operating temperature, and to prevent a static noise margin of the memory cell MC from being lowered.

  In order to increase the on-resistance of the transfer transistor T1 and improve the static noise margin, the high level voltage of the word line WL may be set to a value lower than the power supply voltage VDD (for example, VDD2). At this time, the precharge word line PWL is set to the same power supply voltage VDD2 as the high level voltage of the word line WL. The precharge voltage of the bit line BIT by the precharge circuit PRE is VDD2-Vth. The power supply voltage VDD2 is another example of the first high level voltage.

  Therefore, when the logic 1 is stored in the memory cell MC and the word line WL is set to a high level voltage, the gate-source voltage of the transfer transistor T1 is Vth (= VDD2- (VDD2-Vth)). become. Therefore, when the word line WL is set to the high level voltage, the transfer transistor T1 can be prevented from being turned on, and the voltage at the input / output node ND1 can be prevented from being lowered due to the leakage current to the bit line BIT.

  As described above, in this embodiment, the precharge circuit PRE is lower than the power supply voltage VDD by the threshold voltage Vth of the transfer transistor T1 using the replica transfer transistor RT1 of the replica memory cell RMC having the same structure as the memory cell MC. Generate a precharge voltage. As a result, when the word line WL is set to a high level voltage, it is possible to prevent the high level voltage of the input / output node ND1 from being lowered by turning on the transfer transistor T1, and the static noise margin of the memory cell MC is deteriorated. Can be prevented.

  It is possible to prevent the static noise margin of the memory cell MC from deteriorating even when the manufacturing conditions of the semiconductor memory MEM, the power supply voltage VDD, and the operating temperature vary.

  FIG. 2 shows an example of a semiconductor memory MEM in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. For example, the semiconductor memory MEM is an SRAM. The semiconductor memory MEM may operate in synchronization with the clock signal or may operate asynchronously with the clock signal.

  The semiconductor memory MEM is different from the precharge circuit PRE shown in FIG. 1 in the precharge circuit PRE. In addition, the semiconductor memory MEM includes a voltage generation circuit VGEN that sets the precharge word line PWL to the same value as the high level voltage of the word line WL. Other configurations of the semiconductor memory MEM are the same as those in FIG.

  The precharge circuit PRE has a precharge switch PSW added to the precharge circuit PRE of FIG. The precharge switch PSW is arranged between the replica transfer transistor RT1 and the bit line BIT. The precharge switch PSW is turned off when a high level control signal COL is received, and is turned on when a low level control signal COL is received. For example, the precharge switch PSW is formed by a pMOS transistor that receives a control signal COL at its gate. The control signal COL is set to a high level when the word line WL is set to a high level, and is set to a low level when the word line WL is set to a low level. That is, the precharge switch PSW is turned on when the memory cell MC is not accessed, and is turned off when the memory cell MC is accessed.

  The voltage generation circuit VGEN always generates a high level voltage supplied to the gate of the replica transfer transistor RT1 regardless of whether the memory cell MC is accessed or not, and supplies it to the precharge word line PWL. The high level voltage generated by the voltage generation circuit VGEN is the same as the high level voltage of the word line WL, and is the same value as the power supply voltage VDD or a value lower than the power supply voltage VDD. For example, the voltage generation circuit VGEN may generate a high level to be supplied to the precharge word line PWL using the same circuit as a word driver that generates a high level voltage of the word line WL. Thereby, the precharge voltage line VPR connected to the source of the replica transfer transistor RT1 is only the threshold voltage Vth of the transfer transistor T1 with respect to the high level voltage of the word line WL regardless of whether the memory cell MC is accessed or not accessed. Always set to a low value. For example, the ability to supply the precharge voltage VPR to the bit line BIT can be stabilized by disposing a capacitor for holding charges between the precharge voltage line VPR and the ground line VSS.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, when the replica transfer transistor RT1 is connected to the bit line BIT via the precharge switch PSW, the precharge voltage VPR can be stably generated by always setting the precharge word line PWL to a high level voltage. That is, it is possible to prevent the voltage of the precharge voltage line VPR connected to the source of the replica transfer transistor RT1 from changing every time the memory cell MC is accessed. The precharge voltage line VPR is always maintained at a high level voltage by the voltage generation circuit VGEN. For this reason, every time the memory cell MC is accessed, the charge of the precharge voltage line VPR can be prevented from being discharged and charged, and fluctuations in the power supply voltage VDD due to power supply noise can be prevented. As a result, it is possible to prevent the static noise margin of the memory cell MC from being lowered.

  FIG. 3 shows an example of a semiconductor memory MEM in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. For example, the semiconductor memory MEM is an SRAM. The semiconductor memory MEM may operate in synchronization with the clock signal or may operate asynchronously with the clock signal.

  The semiconductor memory MEM has a word driver DRV1 for driving the word line WL and a word driver DRV2 for driving the precharge word line PWL in addition to the configuration of FIG. The word drivers DRV1 and DRV2 have the same structure. For this reason, when the manufacturing conditions of the semiconductor memory MEM fluctuate, the electrical characteristics of the word drivers DRV1 and DRV2 change together and are always the same. Therefore, the high level voltages output from the word drivers DRV1 and DRV2 are the same as each other, and are the same value as the power supply voltage VDD or a value lower than the power supply voltage VDD. Even when the power supply voltage VDD varies or the operating temperature varies, the high-level voltages output from the word drivers DRV1 and DRV2 are the same.

  The word driver DRV1 receives the word drive signal WLON set to the high level when accessing the memory cell MC, and sets the word line WL to the high level voltage. The word driver DRV1 receives the word drive signal WLON set to the low level when the memory cell MC is not accessed, and sets the word line WL to the low level.

  The word driver DRV2 operates by receiving a signal obtained by inverting the word drive signal WLON with an inverter. That is, the word driver DRV2 sets the precharge word line PWL to a low level voltage when the word driver DRV1 outputs a high level voltage, and sets the precharge word line PWL to a high level when the word driver DRV1 outputs a low level voltage. Set to voltage.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, by using the word driver DRV2 having the same structure as the word driver DRV1, the high-level voltage of the precharge word line PWL can be set to the word even when the manufacturing conditions, the power supply voltage VDD, or the operating temperature changes. It can be the same as the high level voltage of the line PWL.

  FIG. 4 shows an example of a main part of a semiconductor memory MEM in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. For example, the semiconductor memory MEM is an SRAM. The semiconductor memory MEM may operate in synchronization with the clock signal or may operate asynchronously with the clock signal.

  The semiconductor memory MEM has a plurality of memory cells MC arranged in a matrix and a plurality of precharge circuits PRE each including replica memory cells RMC. The columns of memory cells MC arranged in the horizontal direction in FIG. 3 are connected to a common word line WL (WL1 or WL2), and a memory cell array MCA is formed by the plurality of columns of memory cells MC. Replica memory cell RMC is arranged along the wiring direction of word line WL1 adjacent to the column of the endmost memory cell MC (upper side in FIG. 4).

  A column of replica memory cells RMC is connected to a common precharge word line PWL, and a column of replica memory cells RMC forms a precharge voltage generation unit PVGEN. Similar to the replica memory cell RMC, the precharge circuit PRE is arranged along the wiring direction of the word line WL1.

  The memory cell MC is a general SRAM memory cell, and includes load transistors L1 and L2 (pMOS transistors), drive transistors D1 and D2 (nMOS transistors), and transfer transistors T1 and T2 (nMOS transistors). A latch is formed by an inverter made up of the load transistor L1 and the drive transistor D1 and an inverter made up of the load transistor L2 and the drive transistor D2. A high resistance element may be arranged instead of the load transistors L1 and L2. Two power supply terminals of each inverter of the latch are connected to the power supply line VDD and the ground line VSS, respectively. A pair of input / output nodes of the latch are connected to bit lines BIT (BIT1 or BIT2) and BITX (BIT1X or BIT2X) via transfer transistors T1 and T2, respectively. The gates of the transfer transistors T1 and T2 are connected to the word line WL (WL1 or WL2).

  Replica memory cell RMC has the same element structure as memory cell MC, and includes load transistors L1 and L2, drive transistors D1 and D2, and replica transfer transistors RT1 and RT2. For example, the layout pattern of the replica memory cell RMC is designed to be the same as the layout pattern of the memory cell MC except for the wiring pattern that connects the elements. In other words, the column of memory cells at the end of the memory cell array MCA adjacent to the memory cell MC is used as the replica memory cell RMC.

  For example, the channel direction of the replica transfer transistors RT1 and RT2 of the replica memory cell RMC is the same as the channel direction of the transfer transistors T1 and T2 of the memory cell MC. Here, the same channel direction means that the extending direction of the gate wiring of the transistor is the same. By making the extending direction of the gate wiring the same, the electrical characteristics of the transistors can be made equal. Thereby, the transistor size, threshold voltage, film thickness, material, wiring layer, etc. of the replica memory cell RMC can be made the same as those of the memory cell MC, and the electrical characteristics of the replica memory cell RMC are the memory cell MC. Can be equal to the electrical characteristics of Therefore, when the manufacturing conditions of the semiconductor memory MEM, the power supply voltage VDD, and the operating temperature vary, the electrical characteristics of the replica memory cell RMC and the memory cell MC change by the same value in the same direction. That is, the threshold voltages of the transfer transistors T1, T2 and the replica transfer transistors RT1, RT2 can always be equal to each other.

  Also in the replica memory cell RMC, the two power terminals of each inverter of the latch are connected to the power line VDD and the ground line VSS, respectively. In the replica memory cell RMC, the gates of the load transistor L1 (or L2) and the drive transistor D1 (or D2) that form one of the inverters of the latch are connected to the ground line VSS. As a result, the drains of the replica transfer transistors RT1 and RT2 connected to the input / output nodes of the latch are connected to the power supply line VDD via the load transistors L1 and L2 that are turned on. Note that the drains of the replica transfer transistors RT1 and RT2 may be directly connected to the power supply line VDD without being connected to the latch.

  The sources of the replica transfer transistors RT1 and RT2 are connected to the precharge voltage line VPR. For example, the ability to supply the precharge voltage VPR to the bit lines BIT and BITX can be stabilized by disposing a capacitor for holding charges between the precharge voltage line VPR and the ground line VSS. The precharge word line PWL connected to the gates of the replica transfer transistors RT1 and RT2 is set to the same high level voltage as the high level voltage of the word line WL. For example, the high level voltage of the word line WL and the precharge word line PWL is set lower than the power supply voltage VDD.

  The precharge circuit PRE includes pMOS transistors P1 and P2 that connect the precharge voltage line VPR to the bit lines BIT and BITX, respectively, and a pMOS transistor P3 that connects the bit line pair BIT and BITX to each other. The pMOS transistors P1 and P2 are an example of a precharge switch that is turned on when the memory cell MC is not accessed and turned off when the memory cell MC is accessed. The pMOS transistors P1, P2, and P3 operate by receiving an inverted signal of the column selection signal COLX (COL1X or COL2X) via the inverter IV. The pMOS transistors P1, P2, and P3 are turned on when the column selection signal COLX is at a high level, and supply the precharge voltage VPR to the bit line pair BIT and BITX. The pMOS transistors P1, P2, and P3 are turned off when the column selection signal COLX is at a low level, and the connection between the bit line pair BIT and BITX and the precharge voltage line VPR is released.

  In this embodiment, the address assignments of the column selection signals COL1X and COL2X are different from each other, and the column selection signals COL1X and COL2X do not change to the low level at the same time. In other words, the memory cell MC connected to the bit line pair BIT1 and BIT1X and the memory cell MC connected to the bit line pair BIT2 and BIT2X have different address assignments, and access operation (write operation) simultaneously. , Read operation) is not executed.

  For example, when data is written to the memory cell MC selected by the word line WL1 and the column selection signal COL1X (write operation), the column selection signal COL1X is changed to the low level, and the bit line pair BIT1, BIT1X and the precharge voltage line VPR Is disconnected. Thereby, the bit line pair BIT1, BIT1X is set to a high level floating state. One of the bit lines BIT1 and BIT1X is set to a low level by a write amplifier or the like, and the word line WL1 is set to a high level voltage lower than the power supply voltage VDD. As a result, one of the transfer transistors T1 and T2 is turned on, one charge at the input / output node of the latch of the memory cell MC is extracted to one of the bit lines BIT1 and BIT1X, and data is written into the memory cell MC.

  During the write operation of the memory cell MC selected by the word line WL1 and the column selection signal COL1X, the gates of the transfer transistors T1 and T2 of the memory cell MC corresponding to the word line WL1 and the column selection signal COL2X receive a high level voltage. . For example, in the memory cell MC that is connected to the word line WL1 and in which the write operation is not performed, the input / output node on the transfer transistor T1 side is at a high level voltage and the input / output node on the transfer transistor T2 side is at a low level. Charge is supplied from the bit line BIT2X to the input / output node on the transfer transistor T2 side by the transfer transistor T2 that is turned on. However, since the high level voltage of the word line WL1 is lower than the power supply voltage VDD, the on-resistance of the transfer transistor T2 is high, and the voltage at the input / output node on the transfer transistor T2 side hardly increases.

  Similar to the embodiment described above, the precharge voltage of the bit line BIT2 is set to a value lower than the high level voltage of the word line WL by the threshold voltage Vth of the transfer transistor T1. For this reason, the transfer transistor T1 is not turned on, and no leak current flows from the input / output node on the transfer transistor T1 side set to the high level to the bit line BIT. Therefore, data held in the memory cell MC connected to the high-level voltage word line WL1 and not performing the write operation is not destroyed. That is, it is possible to prevent the static noise margin of the memory cell MC from being lowered.

  On the other hand, when data is read from the memory cell MC selected by the word line WL1 and the column selection signal COL1X (read operation), the column selection signal COL1X is changed to the low level. The word line WL1 is set to a high level voltage in a state where the bit line pair BIT1, BIT1X is set to a high level floating state. For example, in the memory cell MC connected to the word line WL1 and performing a read operation, the input / output node on the transfer transistor T1 side is at a high level voltage, and the input / output node on the transfer transistor T2 side is at a low level. The transfer transistor T2 connected to the low-level input / output node in the latch of the memory cell MC is turned on, and the charge of the bit line BIT1X is extracted through the drive transistor D2. Then, the logic of the data held in the memory cell MC is read according to the voltage difference between the bit line BIT1 that maintains the high level and the bit line BIT1X whose voltage has decreased.

  Similar to the write operation, the precharge voltage of the bit line BIT2 is set to a value lower than the high level voltage of the word line WL1 by the threshold voltage Vth of the transfer transistor T1. For this reason, the transfer transistor T1 is not turned on, and no leak current flows from the input / output node on the transfer transistor T1 side set to the high level to the bit line BIT. Therefore, data held in the memory cell MC connected to the high-level voltage word line WL1 and not performing the read operation is not destroyed. That is, it is possible to prevent the static noise margin of the memory cell MC from being lowered.

  FIG. 5 shows an example of the entire block of the semiconductor memory MEM shown in FIG. The semiconductor memory MEM includes a memory cell array MCA, a precharge voltage generation unit PVGEN, a precharge unit PREU, a word decoder WDEC, a column decoder CDEC, a column switch unit CSWU, a sense amplifier unit SAU, and control circuits CNT1 and CNT2. The shaded area indicates a dummy area DMY.

  The dummy regions DMY are formed, for example, around the memory cell array MCA, on the left and right sides of the precharge unit PREU, on the left and right sides of the column switch unit CSWU, and on the left and right sides of the sense amplifier unit SAU. The dummy area DMY has the same circuit configuration as each circuit block used for the access operation of the semiconductor memory MEM. For example, the dummy area DMY around the memory cell array MCA has columns of memory cells (same structure as the memory cells MC in FIG. 4) arranged on each side of the circumference.

  The dummy area DMY of the precharge unit PREU has the same circuit as the precharge circuit PRE shown in FIG. The dummy area DMY is formed in order to uniformly manufacture the pattern shape of the circuit block used for the access operation (write operation, read operation) regardless of the position. Here, the pattern shape includes the shape of the gate wiring, the diffusion layer, the contact, and the like, and the positional relationship between the patterns.

  The precharge unit PREU includes the pMOS transistors P1, P2, and P3 shown in FIG. Each of the precharge circuit PRE shown in FIG. 4 is formed by the precharge unit PREU and the precharge voltage generation unit PVGEN. The precharge voltage generator PVGEN (replica memory cell RMC) is formed by using a memory cell column at the end (upper side in FIG. 4) of the memory cell array MCA. If the replica memory cell RMC does not have sufficient ability to supply the precharge voltage to the bit lines BIT and BITX, the replica memory cell RMC may be formed in a plurality of columns in the precharge voltage generator PVGEN.

  By disposing the precharge voltage generator PVGEN inside the dummy area DMY of the memory cell array MCA, it is possible to prevent the pattern shape of the replica memory cell RMC from being destroyed. As a result, the electrical characteristics of the replica memory cell RMC can be matched with the electrical characteristics of the memory cell MC. Here, the electrical characteristics include a threshold voltage of the transistor, a current characteristic with respect to the gate voltage of the transistor, and the like.

  The column switch unit CSWU includes a column switch connected to each bit line pair BIT and BITX shown in FIG. The sense amplifier unit SAU includes a sense amplifier SA connected to at least one of the bit line pair BIT and BITX via a column switch.

  The word decoder WDEC includes a decoding unit that selects one of the word lines WL shown in FIG. 4 according to an address signal received at an address terminal in an access operation, and a driver unit that sets the selected word line WL to a high level voltage. And have. The word decoder WDEC has a circuit for setting the precharge word line PWL shown in FIG. 4 to a high level voltage. An example of the word decoder WDEC is shown in FIG. In the access operation, the column decoder CDEC activates one of the column selection signals COLX shown in FIG. 4 according to the address signal received at the address terminal in order to select the memory cell MC to be accessed.

  The control circuit CNT1 has, for example, a buffer that transmits a column selection signal COLX. For example, the control circuit CNT2 includes a command decoder that decodes a command signal CMD received at a command terminal, and generates a timing signal for executing a read operation or a write operation. The control circuit CNT2 has a data input / output circuit that outputs or inputs a data signal to the data terminal I / O. The data terminals may be formed separately for output and input.

  FIG. 6 shows an example of the word decoder WDEC shown in FIG. Here, for simplicity of explanation, it is assumed that the word decoder WDEC receives a 3-bit address signal RA (RA0, RA1, RA2). The word decoder WDEC includes a decoding unit DEC and a driver unit DRV that drives the word line WL according to an output signal from the decoding unit DEC.

  The decode unit DEC has eight 4-input AND circuits AND1 functioning as a decode circuit, and a 4-input AND circuit AND2 for setting the precharge word line PWL to a high level voltage. The decode unit DEC operates by receiving the power supply voltage VDD and the ground voltage VSS.

  The AND circuit AND1 receives three bits of the address signal RA (RA0, RA1, RA2) and a signal obtained by inverting the address signal RA, and when all the bits are at a high level, the AND circuit AND1 is high during the high level period of the word drive signal WLON. Output level. Address signal RA is a row address used for selecting word line WL among the address signals received at address terminal AD shown in FIG.

  In the access operation, of the eight AND circuits AND1, one AND circuit AND1 that receives a high level at all inputs outputs a high level, and the other AND circuit AND1 outputs a low level. The AND circuit AND2 receives a high level (VDD) at all inputs and always outputs a high level.

  The driver unit DRV includes a word driver DRV1 connected to the output of the AND circuit AND1, and a word driver DRV2 connected to the output of the AND circuit AND2. Driver unit DRV operates by receiving power supply voltage WVDD and ground voltage VSS. The word drivers DRV1 and DRV2 are the same circuit and have the same electrical characteristics. The power supply voltage WVDD is an example of a first high-level voltage and has a value lower than the power supply voltage VDD. For example, the power supply voltage WVDD is generated by an internal voltage generation circuit formed inside the semiconductor memory MEM.

  When receiving a high level from the AND circuit AND1, the word driver DRV1 sets the corresponding word line WL (any one of WL1-WL8) to the high level voltage WVDD. The word driver DRV2 receives the high level from the AND circuit AND2, and always sets the precharge word line PWL to the high level voltage WVDD. The word driver DRV2 is an example of a voltage generation circuit that generates a high level voltage WVDD supplied to the gates of the replica transfer transistors RT1 and RT2. Each of the word drivers DRV1 and DRV2 has a function of a level shifter that converts the high level input voltage VDD into the high level output voltage WVDD. Note that the input of the word driver DRV2 of the driver unit DRV may be directly connected to the power supply line VDD without forming the AND circuit AND2 in the decoding unit DEC.

  The high level voltage of the precharge word line PWL is generated using the word driver DRV2 having the same circuit configuration as the word driver DRV1 that drives the word line WL. Further, the word drivers DRV1 and DRV2 are formed adjacent to each other in the driver unit DRV which is one route block, and operate by receiving a common power supply voltage WVDD. Thereby, the high level voltage of the precharge word line PWL can be set to the same value as the high level voltage of the word line WL. For example, when the manufacturing conditions of the semiconductor memory MEM vary, the electrical characteristics of the word drivers DRV1, DRV2 change together and are always the same. Accordingly, the high level voltages output from the word drivers DRV1 and DRV2 are the same. The high level voltages output from the word drivers DRV1 and DRV2 are the same even when the power supply voltages VDD and WVDD vary or the operating temperature varies.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, replica memory cell RMC has the same element structure as memory cell MC, and is arranged adjacent to memory cell MC between memory cell array MCA in which memory cell MC is formed and dummy area DMY. . Thereby, the electrical characteristics of the replica memory cell RMC can be made equal to the electrical characteristics of the memory cell MC, and the threshold voltages of the replica transfer transistors RT1 and RT2 can be made equal to the threshold voltages of the transfer transistors T1 and T2. For example, even when the manufacturing conditions of the semiconductor memory MEM, the power supply voltage VDD, and the operating temperature vary, the amount of variation in the electrical characteristics of the replica memory cell RMC and the memory cell MC can be made the same. Furthermore, by using the word drivers DRV1 and DRV2 that are formed adjacent to each other and have the same circuit configuration, the high level voltage WVDD of the word ship WL and the precharge word line PWL can be set to the same value. As a result, even when the word line WL is maintained at a high level voltage, it is possible to prevent the high level voltage at the input / output node of the memory cell MC from being lowered by the turn-on of the transfer transistor T1, and the static noise margin of the memory cell MC Can be prevented from deteriorating.

  FIG. 7 shows an example of a main part of a semiconductor memory MEM in another embodiment. Detailed description of the same elements as those in FIG. 4 is omitted. In this embodiment, the precharge circuit PRE is formed by deleting the pMOS transistors P1, P2, and P3 from the precharge circuit PRE shown in FIG. For this reason, the sources of the transfer transistors RT1 and RT2 of the replica memory cell RMC are directly connected to the bit lines BIT and BITX.

  For example, the precharge word line PWL is set to a level opposite to that of the word line WL, as in FIG. However, in this embodiment, a plurality of word lines WL (WL1, WL2) are formed. Therefore, the precharge word line PWL is set to the low level when one of the word lines WL is set to the high level, and is set to the high level when all the word lines WL are set to the low level. The

  In this embodiment, one of the memory cells MC connected to the bit line pair BIT1, BIT1X and one of the memory cells MC connected to the bit line pair BIT2, BIT2X are simultaneously subjected to a write operation or a read operation. . The precharge circuit PRE operates in the same manner as the precharge circuit PRE shown in FIG. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 8 shows an example of a system SYS on which the semiconductor memory MEM of the above-described embodiment is mounted. The system SYS (user system) forms at least a part of a microcomputer system such as a portable device, for example. The system SYS has a system-on-chip SoC in which a plurality of macros are integrated on a silicon substrate. Alternatively, the system SYS has a multi-chip package MCP in which a plurality of chips are stacked on a package substrate. Alternatively, the system SYS has a system-in-package SiP in which a plurality of chips are mounted on a package substrate such as a lead frame. Furthermore, the system SYS may be formed in the form of chip-on-chip CoC or package-on-package PoP.

  For example, the system SYS includes a CPU (Central Processing Unit), a ROM (Read Only Memory), a peripheral circuit I / O, and a semiconductor memory MEM. The CPU, ROM, peripheral circuit I / O, and semiconductor memory MEM are connected to each other by a system bus SBUS. The CPU accesses the ROM, the peripheral circuit I / O, and the semiconductor memory MEM and controls the operation of the entire system. The CPU outputs a command signal CMD, an address signal AD, and a write data signal I / O to the semiconductor memory MEM in order to execute a write operation. The CPU outputs a command signal CMD and an address signal AD to the semiconductor memory MEM to execute a read operation, and receives a read data signal I / O from the semiconductor memory MEM. The minimum configuration of the system SYS is a CPU and a semiconductor memory MEM.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
A real memory cell having a latch for storing data and a real transfer transistor connected to an input / output node of the latch;
A bit line connected to the input / output node via the real transfer transistor;
A word line connected to the gate of the real transfer transistor;
A precharge circuit for precharging the bit line,
The precharge circuit receives a first high level voltage having the same value as the high level voltage of the word line at the gate, and receives a second high level voltage at the drain, at least when the real memory cell is not accessed, and is generated at the source A semiconductor memory comprising: a replica transfer transistor that supplies a precharge voltage to the bit line, and having a replica memory cell having the same structure as the real memory cell.
(Appendix 2)
A memory cell array including the real memory cells arranged in a matrix;
A column of dummy memory cells arranged around the memory cell array, and
The replica memory cell is adjacent to each of the real memory cells arranged between the memory cell array and the column of the dummy memory cells, arranged in the wiring direction of the word line, and arranged outside the memory cell array. The semiconductor memory according to appendix 1, wherein the semiconductor memory is arranged as follows.
(Appendix 3)
A first word driver which operates in response to the first high level voltage and sets the word line to the first high level voltage;
A second word driver having the same structure as that of the first word driver, operating upon receiving the first high level voltage, and setting a signal line connected to the gate of the replica transfer transistor to the first high level voltage The semiconductor memory according to appendix 1 or appendix 2, characterized by comprising:
(Appendix 4)
A voltage generation circuit that generates the first high-level voltage supplied to the gate of the replica transfer transistor regardless of whether the real memory cell is accessed or not;
The precharge circuit includes a precharge switch that is disposed between the replica memory cell and the bit line and is turned on when the real memory cell is not accessed and turned off when the real memory cell is accessed. The semiconductor memory according to appendix 1 or appendix 2.
(Appendix 5)
A first word driver that sets the word line to the first high level voltage when the real memory cell is accessed and sets the word line to a low level voltage when the real memory cell is not accessed;
The gate of the replica transfer transistor is set to a low level voltage when the first word driver outputs the first high level voltage, and the gate of the replica transfer transistor is set to a low level voltage when the first word driver outputs a low level voltage. The semiconductor memory according to appendix 1 or appendix 2, further comprising: a second word driver that sets the first high-level voltage.
(Appendix 6)
The semiconductor memory according to any one of appendix 1 to appendix 5,
And a controller for accessing the semiconductor memory.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  BIT, BITX bit line; CDEC column decoder; COL control signal; CNT1, CNT2 control circuit; CSWU column switch part; DEC decode part; DMY ... dummy area; DRV driver part; DRV1, DRV2 word Driver; I / O Peripheral circuit; LT Latch; MC Memory cell; MCA Memory cell array; MEM Semiconductor memory; ND1, ND2 Input / output node; PRE Precharge circuit; PREU Precharge unit; Precharge switch; PVGEN, precharge voltage generation unit; PWL, precharge word line; RLT, replica latch; RMC, replica memory cell; RND1, RND2, input / output node; RT1, replica transfer transistor; SAU, sense amplifier unit; SYS ... System; T , T2 ‥ transfer transistor; VGEN ‥ voltage generating circuit; VPR ‥ precharge voltage line; WDEC ‥ word decoder; WL ‥ word line; WVDD ‥ supply voltage

Claims (5)

A real memory cell having a latch for storing data and a real transfer transistor connected to an input / output node of the latch;
A bit line connected to the input / output node via the real transfer transistor;
A word line connected to the gate of the real transfer transistor;
A precharge circuit for precharging the bit line,
The precharge circuit receives a first high level voltage having the same value as the high level voltage of the word line at the gate, and receives a second high level voltage at the drain, at least when the real memory cell is not accessed, and is generated at the source A semiconductor memory comprising: a replica transfer transistor that supplies a precharge voltage to the bit line, and having a replica memory cell having the same structure as the real memory cell. A memory cell array including the real memory cells arranged in a matrix;
A column of dummy memory cells arranged around the memory cell array, and
The replica memory cell is adjacent to each of the real memory cells arranged between the memory cell array and the column of the dummy memory cells, arranged in the wiring direction of the word line, and arranged outside the memory cell array. The semiconductor memory according to claim 1, wherein the semiconductor memory is arranged. A first word driver which operates in response to the first high level voltage and sets the word line to the first high level voltage;
A second word driver having the same structure as that of the first word driver, operating upon receiving the first high level voltage, and setting a signal line connected to the gate of the replica transfer transistor to the first high level voltage The semiconductor memory according to claim 1, further comprising: A voltage generation circuit that generates the first high-level voltage supplied to the gate of the replica transfer transistor regardless of whether the real memory cell is accessed or not;
The precharge circuit includes a precharge switch that is disposed between the replica memory cell and the bit line and is turned on when the real memory cell is not accessed and turned off when the real memory cell is accessed. The semiconductor memory according to claim 1 or 2. A semiconductor memory according to any one of claims 1 to 4, and
And a controller for accessing the semiconductor memory.

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