JP5810041B2 - Variable delay device and variable delay setting method - Google Patents

Description

  The present invention relates to a variable delay device capable of changing a delay time in an electric circuit and a delay time setting method.

  As a variable delay device in a conventional electric circuit, for example, Non-Patent Document 1 includes a cascade connection of a plurality of variable delay modules using semiconductor delay devices. In this device, when the electrical signal input from the input terminal is input to the first stage of the cascaded variable delay module, the delay of each delay device is determined according to the delay time from the input terminal to the output terminal desired by the control device. By setting the time, the delay time from the input terminal to the output terminal can be arbitrarily set.

Micrel programmable delay line http://www.micrel.com/_PDF/HBW/sy89295u.pdf Micrel's multiplexer http://www.micrel.com/_PDF/HBW/sy10-100e164.pdf

However, in the conventional variable delay device, the variable delay modules are cascade-coupled, so that there is a problem that a fixed delay proportional to the variable range of the delay time, that is, the number of variable delay modules to be used is generated and accumulated. .
The present invention has been made to solve the above-described problems, and only a necessary number of variable delay modules can be dynamically connected between input and output terminals according to a delay time desired to be set. An object of the present invention is to provide a variable delay device and a variable delay setting method for realizing a variable delay function with a fixed delay time.

In order to solve the above problems, a variable delay device according to the present invention is configured in the following manner.
(1) A plurality of variable delay modules that are cascade-coupled to each other, the first stage input terminal is connected to the input terminal, each having an arbitrary delay time, and any module output is selected from the outputs of the plurality of variable delay modules. And a control means for controlling output selection of the plurality of variable delay modules and multiplexers, and the control means includes a set delay time and second and subsequent variable delay modules. The means for comparing the magnitude relationship with the total fixed delay time and the number of stages of variable delay modules required when the set delay time is smaller than the total fixed delay time of the variable delay modules after the second stage Then, the calculated module output of the final stage is selected by the multiplexer and delayed to the variable delay module of the first stage. And when the set delay time is larger than the sum of the fixed delay times of the variable delay modules after the second stage, the multiplexer outputs the module outputs of the last stage of all the variable delay modules, And a means for calculating delay setting times for all variable delay modules and setting the delay times.

The variable delay setting method according to the present invention is configured in the following manner.
(2) A plurality of variable delay modules that are cascade-coupled to each other, the first stage input terminal is connected to the input terminal, each having an arbitrary delay time, and an arbitrary module output is selected from the outputs of the plurality of variable delay modules. A variable delay setting method used in a variable delay device having a multiplexer that leads to an output terminal, and compares the magnitude relationship between the set delay time and the total fixed delay time of the variable delay modules in the second and subsequent stages As a result of the comparison, if the set delay time is smaller than the sum of the fixed delay times of the variable delay modules after the second stage, the number of necessary variable delay modules is calculated, and the calculated final stage The multiplexer output is selected by the multiplexer, the delay time is set in the variable delay module in the first stage, and as a result of the comparison, the set delay is set. When the time is larger than the total of the fixed delay times of the variable delay modules after the second stage, the multiplexer outputs the module outputs of the last stage of all the variable delay modules and set the delay setting time for all the variable delay modules. It is set as the aspect which calculates and sets delay time.

  In the present invention, it is possible not only to cascade the variable delay modules but also to set a variable delay with a minimum fixed delay time by arranging a multiplexer for taking out the output of each variable delay module halfway. It is said. Specifically, a delay device that can set the delay time flexibly by selecting only the required number of variable delay modules according to the delay time to be set and dynamically connecting between the input and output terminals. This makes it possible to minimize the fixed delay time from input to output.

  Therefore, according to the present invention, only the required number of variable delay modules can be dynamically connected according to the delay time desired to be set between the input and output terminals, and the variable delay function with the minimum fixed delay time. It is possible to provide a variable delay device and a variable delay setting method for realizing the above.

It is a block diagram which shows the structure of the variable delay apparatus which concerns on embodiment of this invention. 3 is a flowchart showing a flow of control in the control device of the variable delay device shown in FIG. 1.

Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiment described below is an example of the configuration of the present invention, and the present invention is not limited to the following embodiment.
FIG. 1 is a block diagram showing a configuration of a variable delay device according to the present invention. In FIG. 1, an electrical signal input from an input terminal 10 is input to the first stage of n variable delay modules 101 to 10n that are cascade-coupled. The output terminals of the variable delay modules 101 to 10n are connected to the multiplexer 200, respectively.

  The variable delay modules 101 to 10n and the multiplexer 200 are connected to the control device 300 through the control signal line 301. The control device 300 sets the input selection of the multiplexer 200 and the delay time of each delay module 100 according to the desired delay time from the input terminal 10 to the output terminal 20. Further, the control device 300 selects the output of the variable delay modules 101 to 10n to be extracted by selecting an input in the multiplexer 200. As a result, only the electrical signal from the selected variable delay module 10 i is output to the output terminal 20.

  Next, a delay time setting method according to the present invention will be described with reference to FIG. FIG. 2 is a flowchart showing the flow of processing when the control device 300 executes the delay time setting of each of the variable delay modules 101 to 10n and the input selection of the multiplexer 200.

In this embodiment, n variable delay modules 101 to 10n are cascade-coupled, and outputs of the variable delay modules 101 to 10n are connected to the multiplexer 200 as n inputs, respectively. In this configuration, the variable delay time of the i-th variable delay module 10i is T _vi , the fixed delay time is T _fi , and the set delay time is T _-i . The magnitude relationship among all the variable delay times T _vj , fixed delay times T _fj and set delay times T _−j is as follows:
T _vi ≧ T _-i > T _fj (1)
Suppose that However, 1 ≦ i and j ≦ n.

Hereinafter, a delay time setting method according to the value of the delay time T to be set will be described.
First, in means 500 for comparing the magnitude relationship between the delay time to be set and the sum of the fixed delay times of the variable delay modules 102 to 10n in the second and subsequent stages, in step S1, the delay time T and the sum of the second and subsequent stages are compared. Compare (determine) T _f . However,
T _f = Σ ⁱ ₂ T _fk (2)
It is.
(A) When the delay time T is smaller than T _f by the determination S1 in the means 500
When the delay time to be set is smaller than the sum of the fixed delay times of the plurality of variable delay modules in the second and subsequent stages, the means 501 for setting the delay time is executed. The means 501 calculates the required variable delay module number i (step S21), sets the input of the multiplexer 200 to i (step S22), and sets the delay time in the first stage variable delay module (step S23).

Specifically, the variable delay modules 101 to 10i and the multiplexer 200 are controlled as follows.
First, the delay time T is
0 ≤ T <T _f-2 (3)
In this case, the delay time is set only by the first variable delay module 101. Therefore, 1 is selected as the input of the multiplexer 200, and the set delay time T ₋₁ of the first variable delay module 101 is
T _-1 = T (4)
And

On the other hand, the delay time T is
T _f-2 ≦ T <T _f-2 + T _f-3 (5)
In this case, 2 is selected as the input of the multiplexer 200 and the set delay time T ₋₁ of the first variable delay module 101 is
T- ₁ = T _-Tf-2 (6)
And

In general, the delay time T is
Σ ⁱ ₂ T _fk ≦ T <Σ ^{i + 1} ₂ T _fk (7)
In this case, i is selected as the input of the multiplexer 200, and the set delay time T ₋₁ of the first variable delay module 101 is
T ₋₁ = T−Σ ⁱ ₂ T _fk (8)
And However, i is i <n.
(B) When the delay time T is equal to or longer than T _f by the determination S1 in the means 500
When the delay time to be set is equal to or greater than the sum of the fixed delay times of a plurality of variable delay modules in the second and subsequent stages, the means 502 for setting the delay time is executed. In this means 502, the input of the multiplexer 200 is set to n (step S31), the delay setting time for each module is calculated (step S32), and the delay time is set for each module (step S33).

Specifically, the variable delay modules 101 to 10n and the multiplexer 200 are controlled as follows.
First, n is selected as the input of the multiplexer 200. Next, a variable delay module setting time T _v obtained by subtracting the total T _f of fixed delay times from the delay time T is set in the variable delay module. However,
T _v = T−T _f (9)
It is.

Here, the variable delay module setting time T _v is
0 ≦ T _v <T _v−1 (10)
, The set delay time T ₋₁ of the first variable delay module 101 is
T ₋₁ = T _v (11)
And

On the other hand, the variable delay module setting time T _v is
Σ ⁱ ₁ T _vk ≦ T _v <Σ ^{i + 1} ₁ T _vk (12)
In this case, the set delay time T _vi of the 1st to i-th variable delay modules 101 to 10i is equal to the maximum variable delay time of each variable delay module,
T _-i = T _vi (13)
And set. However, i <n.

Then, the set delay time T _{-i + 1} of the (i + 1) th variable delay module 10i + 1 is
_{T -i + 1 = T v -} Σ i 1 T vk ... (14)
And
As described above, the delay time is set by the means 500, the means 501, and the means 502.

Here, the minimum delay time, the maximum delay time, and the variable delay time of the variable delay device in the present embodiment are obtained as follows.
First, the minimum delay time T _min from the input terminal 10 to the output terminal 20 is when the input of the multiplexer 200 is 1 and all the set delay times T _-i are 0.
T _min = T _f-1 + T _m (15)
It becomes. However, T _m is a fixed delay time of the multiplexer 200.

The maximum delay time T _max is when the input of the multiplexer 200 is n and all the set delay times T _-i are T _vi .
T _max = Σ ⁿ ₁ T _fk + Σ ⁿ ₁ T _vk + T _m (16)
It becomes.
The variable delay time T _var for the entire variable delay device is
T _var = T _max -T _min
= Σ ⁿ ₁ T _vk + Σ ⁿ ₂ T _fk (17)
It becomes.

Next, the minimum delay time T _min-c , the maximum delay time T _max-c and the variable delay time T _var-c of the variable delay device according to the conventional method are as follows.
T _min-c = Σ ⁿ ₁ T _f-k (18)
T _max = Σ ⁿ ₁ T _fk + Σ ⁿ ₁ T _vk (19)
T _var-c = T _max -T _min
= Σ ⁿ ₁ T _vk (20)
Here, from Equation (15) and Equation (18),
ΔT _min = T _min-c -T _min
= Σ ⁿ ₂ T _fk −Tm (21)
However, ΔT _min is a difference in fixed delay time.

From the equations (17) and (20),
ΔT _var = T _var -T _var-c
= Σ ⁿ ₂ T _fk (22)
However, ΔT _var is a difference in variable delay time.
From the above, it can be seen that according to the present embodiment, the fixed delay time of Expression (21) can be decreased by ΔT _min and the variable delay time can be expanded by ΔT _var .
Here, as an improvement example of the minimum delay time and the maximum delay time, the delay device shown in Non-Patent Document 1 and the multiplexer shown in Non-Patent Document 2 are used for the variable delay modules 101 to 10n and the multiplexer 200, respectively. An example is shown. This delay device has a variable delay time T _vi of 11.6 ns and a fixed delay time T _fi of 3.2 ns. The delay time T _m of a multiplexer 200 is about 1 ns.

  In the conventional method, the delay time range is 32 ns to 148 ns, so the variable delay time range is 116 ns. On the other hand, in this embodiment, the delay time range is 4.2 ns to 148 ns, and the variable delay time range is 143.8 ns. Therefore, it can be seen from the equations (21) and (22) that the fixed delay time can be shortened by 27.8 ns and the variable delay time range can be expanded by 28.8 ns.

As described above, according to the variable delay device of the present embodiment, it is possible to minimize the fixed delay time and expand the variable delay time range.
In addition, the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some configurations may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different example embodiments may be combined as appropriate.

DESCRIPTION OF SYMBOLS 10 ... Input terminal 101-10n ... Variable delay module 20 ... Output terminal 200 ... Multiplexer 300 ... Control apparatus 301 ... Control signal line

Claims (2)

A plurality of variable delay modules that are cascade-coupled to each other, the first stage input terminal is connected to the input terminal, and each of which has an arbitrary delay time,
A multiplexer that selects an arbitrary module output from outputs of each of the plurality of variable delay modules and derives the output to an output terminal;
And control means for controlling the output selection of the plurality of variable delay module and the multiplexer,
The control means includes
A first means for comparing the magnitude relationship between the set delay time and the total fixed delay time Tf of the variable delay module from the second stage to the last stage ;
If the is the set delay time is determined and the Tf is less than the said first means, the sum of the fixed delay time of the variable delay module to the second and subsequent stages i-th stage does not exceed the target set delay time Calculate the required number of stages i of variable delay modules, let the multiplexer select the i-th module output , set the fixed delay time for each variable delay module from the second stage to the i-th stage, i stages after the first stage Second means for setting the delay time of the first-stage variable delay module so that the sum of the set delay times of the variable delay modules up to the eye is equal to the set delay time;
When the first device under the set delay time by means of the determined the Tf or more, to select the module output of the final stage to the multiplexer, the maximum variable delay time of the variable delay module until after the first stage the i-th stage Calculate the number i of variable delay modules whose sum does not exceed the value obtained by subtracting Tf from the set delay time, set the maximum variable delay time for each variable delay module from the first stage to the i-th stage, And a third means for setting the delay time of the i + 1 stage variable delay module so that the sum of the set delay times of the variable delay modules up to the stage is equal to the set delay time. apparatus. A plurality of variable delay modules that are cascade-coupled with each other, the first stage input terminal is connected to the input terminal, each of which has an arbitrary delay time, and the output of each of the plurality of variable delay modules is selected and output. a multiplexer for deriving a terminal, a plurality of variable delay module and the variable delay setting method variable delay device and a control means to run for controlling the output selection of the multiplexer,
The control means is
A first step of comparing the magnitude relationship between the set delay time and the total fixed delay time Tf of the variable delay module from the second stage to the last stage ;
If the is the set delay time is determined and the Tf is smaller than the first step, the sum of the fixed delay time of the variable delay module to the second and subsequent stages i-th stage does not exceed the target set delay time Calculate the required number of stages i of variable delay modules, let the multiplexer select the i-th module output , set the fixed delay time for each variable delay module from the second stage to the i-th stage, i stages after the first stage a second step of the sum of the set delay time of the variable delay module until the eye is set the delay time of the first stage of the variable delay module to be equal to the target set delay time,
When the first of the target set delay time in step is determined and the Tf or more, to select the module output of the final stage to the multiplexer, the maximum variable delay time of the variable delay module until after the first stage the i-th stage Calculate the number i of variable delay modules whose sum does not exceed the value obtained by subtracting Tf from the set delay time, set the maximum variable delay time for each variable delay module from the first stage to the i-th stage, A third step of setting the delay time of the i + 1 stage variable delay module so that the sum of the set delay times of the variable delay modules up to the stage becomes equal to the set delay time ;
The variable delay setting method characterized by performing .

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