JP5810782B2 - Asynchronous absorption circuit, image processing apparatus, and program - Google Patents

Description

  The present invention relates to an asynchronous absorption circuit, an image processing device, and a program.

  For example, when a first-in first-out (FIFO) memory device is configured on a semiconductor integrated circuit, there is a disadvantage that the dual port memory is larger in size than the single port memory. For this reason, in a semiconductor device in which more circuits are to be integrated, a method of mounting and controlling a single port SRAM or the like that is as small as possible is used (for example, see Patent Document 1).

  A memory control device that performs writing or reading operation using two single-port SRAMs is conventionally known. The conventional memory control device has an address detection means for detecting the completion of writing and reading operations for one frame of image, and a priority setting for setting a priority to one of the writing or reading operations to the address detecting means and the storage means. Means are provided.

  The switching means switches the storage means each time the operation-side address detection means for which priority is set detects completion of writing or reading for one frame. Further, the writing or reading control means on the operation side for which priority is not set performs writing or reading to continuous addresses before and after switching of the storage means (see, for example, Patent Document 2).

  However, in the conventional memory control device, every time the address detecting means detects completion of writing or reading for one frame, the switching means switches between the first and second storage means capable of storing at least one frame of image. Yes. Therefore, the conventional memory control device has a problem that it requires two storage means capable of storing at least one frame of an image.

  The present invention has been made in view of the above points, and provides an asynchronous absorption circuit, an image processing apparatus, and a program capable of performing asynchronous absorption using a plurality of single-port memories having a storage capacity smaller than that of one image line. For the purpose.

To solve the problems described above, asynchronous absorption circuit according to claim 1, a write operation means storage capacity to input data of a write operation to less Ifuku number storage means than the image one line each A read operation means for performing a read operation of output data from the storage means, a switching means for switching the storage means to be written and read by the write operation means, and an input for one image line Based on the timing at which block data divided into a plurality of data is distributed to the storage means, the switching control means for controlling the switching of the storage means by the switching means, and the data read by the read operation means are converted into the input data inhomogeneous for converting the clock signal of the output data from the clock signal And having an absorption unit.

  In addition, what applied the component, expression, or arbitrary combination of the component of this invention to a method, an apparatus, a system, a computer program, a recording medium, a data structure, etc. is also effective as an aspect of this invention.

  According to the present invention, it is possible to provide an asynchronous absorption circuit, an image processing apparatus, and a program capable of performing asynchronous absorption using a plurality of single port memories having a storage capacity smaller than that of one image line.

It is a block diagram of an example including an asynchronous absorption circuit. It is a timing diagram of an example of an asynchronous absorption circuit. It is the expanded timing diagram of an example of an asynchronous absorption circuit. It is an example block diagram including the asynchronous absorption circuit using dual port RAM. It is explanatory drawing of an example showing calculation of the memory capacity and delay time which are required in the asynchronous absorption circuit using dual port RAM. It is a block diagram of one Example including the asynchronous absorption circuit of this Embodiment. It is a timing diagram of an example of the asynchronous absorption circuit of the present embodiment. It is explanatory drawing of an example of the process from the time t6 to the time t7. It is a block diagram of the other Example containing the asynchronous absorption circuit of this Embodiment. It is a timing diagram of the other example of the asynchronous absorption circuit of this Embodiment. It is explanatory drawing which showed an example of the method of selecting the combination of required single port RAM from several single port RAM. It is explanatory drawing of an example of a several different mode. It is a hardware block diagram of an example of PC. It is explanatory drawing showing an example of the bit number and Word number of two single port RAM. It is explanatory drawing of an example of the block data which divided | segmented input data. It is the flowchart of an example which showed the preparation procedure of RAM switching table. It is explanatory drawing which showed an example of the combination of single port RAM of the storage capacity in FAB. It is explanatory drawing of an example showing the delay time of asynchronous absorption. It is a block diagram of an example of the sheet | seat which produces RAM switching table. It is a block diagram of the other example of the sheet | seat which produces a RAM switching table.

  Hereinafter, embodiments of the present invention will be described in detail.

  The asynchronous absorption circuit in the present embodiment converts the speed of high-speed input data to low-speed output data. The asynchronous absorption circuit is sometimes called a speed conversion circuit. Conventionally, asynchronous absorption circuits generally perform asynchronous absorption using a dual port memory.

  However, the dual port memory may not be used by FAB (foundry). In addition, the dual port memory has a chip size with respect to the storage capacity that is about twice or more larger than that of the single port memory, and the scale of control circuits (such as a Gray code counter) other than the memory is large.

  Further, the dual port memory cannot be diverted to other products even if it is a product having a plurality of different modes and a memory such as a RAM is properly used for each mode to reduce the circuit scale or reduce the power consumption.

  Therefore, in the asynchronous absorption circuit according to the present embodiment, the chip size is reduced by using a plurality of single port memories for asynchronous absorption, and the single port memory can be easily diverted (shared) in a plurality of modes. .

  FIG. 1 is a block diagram of an example including an asynchronous absorption circuit. FIG. 1 shows video data of 30 fps (Frame Per Second) of YUV422 of 1280 × 720 (720p) with input data of 80 MHz. 720p is one of video signal formats for digital television broadcasting.

  YUV422 is one of the YUV methods, which is a color expression method. YUV422 expresses color with 16 bits of luminance information 8 bits and color difference information 8 bits per pixel. fps indicates how many images are displayed per second. FIG. 1 shows 30 fps video data of 720P YUV422 with 50 MHz output data.

  The asynchronous absorption circuit 11 shown in FIG. 1 represents an example in which the speed of 80 MHz input data is converted to 50 MHz output data. Input data is input to the asynchronous absorption circuit 11 via the input data I / F 10. The output data is output from the asynchronous absorption circuit 11 via the output data I / F 12. The input data I / F 10 inputs the input data to the asynchronous absorption circuit 11 in synchronization with the 80 MHz clock signal ICLK. The output data I / F 12 outputs the output data from the asynchronous absorption circuit 11 in synchronization with the 50 MHz clock signal OCLK.

  The input data has 16-bit data DATA in which the input-side vertical synchronization signal VSYNC, the input-side horizontal synchronization signal HSYNC, the input-side luminance information 8 bits, and the color difference information 8 bits are collected. The output data includes an output-side vertical synchronization signal OVSYNC, an output-side horizontal synchronization signal OHSYNC, 16-bit data ODATA that combines output-side luminance information 8 bits and color-difference information 8 bits, and an output-side valid signal OVALID.

  FIG. 2 is a timing diagram of an example of the asynchronous absorption circuit. VBLANK in FIG. 2 indicates the interval of the vertical synchronization signal. HBLANK indicates the interval of the horizontal synchronizing signal. FIG. 2A is a timing chart of the input side vertical synchronization signal VSYNC. FIG. 2B is a timing chart of the input side horizontal synchronization signal HSYNC. FIG. 2C is a timing diagram of 16-bit data DATA.

  FIG. 2D is a timing chart of the output side vertical synchronization signal OVSYNC. FIG. 2E is a timing diagram of the output side horizontal synchronization signal OHSYNC. FIG. 2F is a timing chart of 16-bit data ODATA. FIG. 2G is a timing chart of the output side valid signal OVALID.

  As shown in the timing diagram of FIG. 2, the input side horizontal synchronization signal HSYNC for 720 lines is included in the period of one input side vertical synchronization signal VSYNC. Further, the data DATA for 1280 clocks (clock signal ICLK) is included in the period of one input side horizontal synchronization signal HSYNC.

  Further, the output side horizontal synchronization signal OHSYNC for 720 lines is included in the period of one output side vertical synchronization signal OVSYNC. In addition, a period of one output side horizontal synchronization signal OHSYNC includes data ODATA for 1280 clocks (clock signal OCLK) and an output side valid signal OVALID. The output data is delayed with respect to the input data.

  FIG. 3 is an enlarged timing diagram of an example of the asynchronous absorption circuit. In the enlarged timing diagram of FIG. 3, the input-side vertical synchronization signal VSYNC and the output-side vertical synchronization signal OVSYNC are omitted.

  As shown in FIG. 3, asynchronous absorption of video data is usually performed for each line. Since asynchronous absorption is performed for each line, it is not preferable that the input of the next line starts before the output of one line ends. Note that depending on how the asynchronous absorption circuit 11 is made, it is possible to cope with the start of the input of the next line before the output of one line is finished. However, if the average speed is constant, the data stored in the RAM increases for each line. The required RAM storage capacity increases.

  In general, the vertical synchronization signal interval VBLANK is longer than the horizontal synchronization signal interval HBLANK. Therefore, in order to perform asynchronous absorption for each line, the delay time of asynchronous absorption may be equal to or less than the horizontal synchronization signal interval HBLANK. The asynchronous absorption delay time is the time from the end of data DATA to the end of data ODATA in one line. For example, 720p video data at 80 MHz has a horizontal sync signal interval HBLANK of 20 us or more (maximum average of about 30 us) at 30 fps.

  Here, in order to facilitate understanding of the asynchronous absorption circuit in the present embodiment, an asynchronous absorption circuit using a dual port RAM will be described. FIG. 4 is a block diagram of an example including an asynchronous absorption circuit using a dual port RAM. FIG. 4 shows continuous data for 1280 clocks (clock signal ICLK) of 80 MHz. The output data is continuous data for 1280 clocks (clock signal OCLK) of 50 MHz.

  The asynchronous absorption circuit 11 stores the data DATA in the dual port RAM 13 in synchronization with the 80 MHz clock signal ICLK, and takes out the data ODATA from the dual port RAM 13 in synchronization with the 50 MHz clock signal OCLK.

  FIG. 5 is an explanatory diagram showing an example of calculation of storage capacity and delay time required in an asynchronous absorption circuit using a dual port RAM. Asynchronous absorption circuit 11 starts outputting output data almost simultaneously with the start of input of input data. To be exact, since the input data is asynchronously extracted and output, output of the output data starts slightly later than the input data.

  In the example of FIG. 5, the clock signal ICLK of input data is faster than the clock signal OCLK of output data, so that the output side valid signal OVALID becomes active until the output data is completely output. For this reason, the delay time of asynchronous absorption is 9.6 us, which is the difference between the input time 16 us of input data and the output time 25.6 us of output data.

  At the time when the input of the input data is completed, the dual port RAM 13 stores output data for 480 words to be output over a time of 9.6 us. Note that 480 words is 9.6us / 25.6us of 1280 words.

  Therefore, the dual port RAM 13 needs a storage capacity of 16 bits × 480 words = 960 bytes or more. Actually, since there is no odd number of dual-port RAMs 13 (depending on the FAB), a 16-bit × 512-word dual-port RAM 13 is required.

  FIG. 6 is a block diagram of an example including the asynchronous absorption circuit of the present embodiment. As shown in FIG. 6, the asynchronous absorption circuit 20 of the present embodiment uses two single port RAMs 0 and 1. FIG. 6 shows continuous data for 1280 clocks (clock signal ICLK) of 80 MHz. The output data is continuous data for 1280 clocks of 50 MHz (clock signal OCLK). The storage capacity of the two single-port RAMs 0 and 1 is 16 bits × 384 words = 768 bytes.

  The asynchronous absorption circuit 20 includes a synchronous absorption unit 21 and an asynchronous absorption unit 22. The asynchronous absorption unit 22 has a built-in FF (flip-flop) unit 29. The built-in FF unit 29 holds output data for 8 CLK, for example. The built-in FF unit 29 performs asynchronous absorption with a small FF of 16 bytes, for example. Further, the built-in FF unit 29 temporarily stops the output data from the synchronization absorbing unit 21 with a wait signal before the stored output data becomes full (FULL).

  The synchronization absorption unit 21 includes a data number (CLK number) count unit 23, a RAM switching table 24, a switching determination unit 25, a write operation unit 26, a read operation unit 27, and a RAM selector unit 28. The synchronization absorbing unit 21 performs a write operation in order to continue to secure the input data even while the output data to the asynchronous absorbing unit 22 is temporarily stopped by the wait signal.

  The data number counting unit 23 counts the input data of 80 MHz and recognizes what number of clock input data is now. The RAM switching table 24 stores information on which of the two single-port RAMs 0 and 1 is to be written or read from which of the two single-port RAMs 0 and 1 at a predetermined clock.

  For example, the RAM switching table 24 stores the timing for switching between reading and writing of the two single port RAMs 0 and 1. The switching determination unit 25 distributes the input data to the single port RAMs 0 and 1 by switching the RAM selector unit 28 based on the timing stored in the RAM switching table 24.

  The write operation unit 26 writes data DATA to one of the two single port RAMs 0 and 1 based on switching of the RAM selector unit 28. The read operation unit 27 reads data DATA from one of the two single port RAMs 0 and 1 based on the switching of the RAM selector unit 28. The read operation unit 27 transmits the read data DATA to the built-in FF unit 29.

  FIG. 7 is a timing diagram of an example of the asynchronous absorption circuit of this embodiment. For example, in the timing chart of FIG. 7, input data which is continuous data for 1280 clocks is divided into eight block data D1-D8. The block data D1-D8 is not divided equally but is divided according to a certain rule described later. The timing for switching between reading and writing of the two single-port RAMs 0 and 1 stored in the RAM switching table 24 is determined based on a certain rule to be described later, in other words, based on how the block data D1 to D8 are divided. .

  Since the two single port RAMs 0 and 1 are single ports, the write operation and the read operation are not simultaneously performed at any time. In addition, one of the two single port RAMs 0 and 1 is always written with data DATA at the same time as the input data. The output data is read from one of the two single-port RAMs 0 and 1 and then asynchronously absorbed by the asynchronous absorber 22. Therefore, the output data output from the asynchronous absorption unit 22 is slightly delayed from the data DATA output from one of the two single port RAMs 0 and 1.

  When the asynchronous absorption unit 22 is about to become full, the output data from the synchronous absorption unit 21 is temporarily stopped by a wait signal. Therefore, in the timing chart of FIG. 7, the data DATA read from one of the single port RAMs 0 and 1 is set for each block data, but the data DATA is not always read continuously for each block data. Absent.

  Writing the block data D1 to the single port RAM0 starts at time t1 and ends at time t2. The next block data D2 is written to the single port RAM1. Writing the block data D2 to the single port RAM1 starts at time t2 and ends at time t3. The block data D1 is read from the single port RAM0 between time t2 and time t3. The block data D1 read from the single port RAM0 is asynchronously absorbed by the asynchronous absorber 22 and then output as output data.

  Thereafter, the asynchronous absorption circuit 20 repeatedly performs the same processing from the time t1 to the time t3 as shown in the timing chart of FIG. 7, and the writing of the block data D8 to the single port RAM 1 is completed at the time t9.

  FIG. 8 is an explanatory diagram of an example of processing from time t6 to time t7. The single port RAM0 stores a data block D5. Even if the block data D5 read from the single port RAM0 is asynchronously absorbed by the asynchronous absorber 22 and it takes 20 us (or 40 us) to be output as output data, the 80 MHz of the input side of the asynchronous absorber 22 Since the output is faster than 50 MHz on the output side, the output data is always valid until the block data D5 ends.

  In other words, the asynchronous absorber 22 temporarily pauses the read operation with a wait signal so that the output data held by the built-in FF unit 29 does not become full, but the built-in FF unit 29 until the output of the block data D5 ends. The output data held by is never empty.

  Completion of the writing of the block data D6 from the time t6 to the single port RAM1 is 2912.5 ns corresponding to 233 clocks (clock signal ICLK). In addition, the completion of the output of the block data D5 as the output data from time t6 takes 2760 ns of the 138 clocks (clock signal OCLK) plus 20 us until the output data starts to be output from the asynchronous absorber 22. .

  Thus, the write operation of the block data D6 to the single port RAM1 ends at time t7. On the other hand, the operation of reading the block data D5 from the single port RAM0 and outputting it as asynchronously absorbed output data always ends earlier than time t7. In the timing chart of FIG. 7, the RAM switching table 24 is created so that the read operation always ends earlier than the write operation until time t8.

  At time t9, the writing operation of the block data D8 to the single port RAM 1 is completed. On the other hand, the read operation of the block data D7 from the single port RAM0 does not end at time t9. The RAM switching table 24 is created such that the read operation ends later than the write operation at time t9. However, since the block data D1 of the next line is not input unless the interval HBLANK (20 us) of the horizontal synchronization signal has elapsed, there is no problem. The read operation of the block data D7 from the single port RAM0 ends at time t10.

  The read operation of the block data D8 from the single port RAM 1 starts at time t10 and ends at time t11. The output data output after the block data D8 read from the single-port RAM 1 is asynchronously absorbed by the asynchronous absorption unit 22 is slightly delayed from the time t11, but from the first input to the first output in the asynchronous absorption unit 22 Since it is sufficiently smaller than 1 us at about 20 ns or 40 ns, it can be ignored.

  As described above, the delay time of the asynchronous absorption circuit 20 in FIG. 8 is the time t11-t9. Time t11-t9 can be converted to (t11-t8)-(t9-t8). t11-t8 is the time to output the block data D7 and D8 at 50 MHz. Further, t9-t8 is a time for writing the block data D8 to the single port RAM 1 at 80 MHz.

  Therefore, it can be estimated that 20 ns × (384 + 380) −12.5 ns × 380 = 10.53 us. As described above, the asynchronous absorption circuit 20 of FIG. 6 has a delay time of 10.53 us, which is sufficiently smaller than the horizontal sync signal interval HBLANK (20 us), and video data of 80 MHz, 720 p, and 30 fps is video of 50 MHz, 720 p, and 30 fps. Can be converted to data.

  As described above, the asynchronous absorption circuit 20 can realize asynchronous absorption using the 16-bit × 512 word dual-port RAM 13 by using the two single-port RAMs 0, 1 of 16-bit × 384 word. In general, the combination of two single-port RAMs 0 and 1 of 16 bits × 384 words is smaller in circuit scale than the dual-port RAM 13 of 16 bits × 512 words.

  FIG. 9 is a block diagram of another example including the asynchronous absorption circuit of this embodiment. The asynchronous absorption circuit 20A of FIG. 9 is different from the asynchronous absorption circuit 20 of FIG. 6 in the following points. First, the asynchronous absorption circuit 20A has the built-in FF section 29 of FIG. 6 removed. Further, the asynchronous absorption circuit 20A not only switches the read operation and the write operation of the two single port RAMs 0 and 1, but also switches the clock signal for operation.

  A clock signal for operating the two single port RAMs 0 and 1 is supplied to the two single port RAMs 0 and 1 via the CLK generation circuit 30. The CLK generation circuit 30 has a CLK selector unit 31. The CLK selector 31 is supplied with an 80 MHz clock signal and a 50 MHz clock signal.

  The CLK selector 31 supplies an 80 MHz clock signal to the one performing the write operation of the two single port RAMs 0 and 1 and supplies a 50 MHz clock signal to the one performing the read operation. The switching determination unit 25 performs switching of the 80 MHz clock signal and the 50 MHz clock signal supplied from the CLK selector unit 31 to the two single port RAMs 0 and 1 based on the timing stored in the RAM switching table 24.

  As described above, the two single-port RAMs 0 and 1 are supplied with the 80 MHz clock signal when the write operation is performed, and are supplied with the 50 MHz clock signal when the read operation is performed. In the asynchronous absorption circuit 20A, since the output data is output in synchronization with the clock signals of 50 MHz from the two single port RAMs 0, 1, the built-in FF unit 29 in FIG. 6 is not necessary.

  The basic concept and timing diagram of the asynchronous absorption circuit 20A are the same as those of the asynchronous absorption circuit 20 of FIG. The asynchronous absorption circuit 20A prepares the RAM switching table 24 so that the completion of the read operation is completed earlier than the completion of the write operation, including the time required for switching the clock signal by the CLK selector unit 31.

  For example, the asynchronous absorption circuit 20A has a time until switching to (or stopping) the 80 MHz clock signal in preparation for the next write operation after the read operation by the 50 MHz clock signal of the single port RAM0 is completed. It is earlier than the completion of the 80 MHz write operation.

  The asynchronous absorption circuit 20A is smaller in circuit scale than the asynchronous absorption circuit 20 of FIG. 6, but the 80 MHz and 50 MHz clock signals supplied to the two single port RAMs 0 and 1 and the 80 MHz clock signal ICLK and Since synchronization timing adjustment with the 50 MHz clock signal OCLK is necessary, the CLK generation circuit 30 outside the asynchronous absorption circuit 20A requires logic.

  As described above, the asynchronous absorption circuit 20A can realize asynchronous absorption, which has been conventionally performed by using the 16-bit × 512 word dual-port RAM 13, by using the two single-port RAMs 0, 1 of 16-bit × 384 words.

  The asynchronous absorption circuit 20 of the present embodiment does not have a single combination of storage capacities that can be realized even if the total storage capacities of the two single port RAMs 0 and 1 are the same. For example, in the case of a combination of the storage capacities of the single port RAMs 0 and 1 different from the timing chart of FIG. 7, the RAM switching table 24 stores the timing for switching between reading and writing of two single port RAMs 0 and 1 different from FIG. .

  FIG. 10 is a timing chart of another example of the asynchronous absorption circuit of this embodiment. In the following, description of parts similar to those in the timing chart of FIG. 7 is omitted as appropriate. In FIG. 10, the storage capacity of the single port RAM 0 is 16 bits × 512 words (only 449 words are used), and the storage capacity of the single port RAM 1 is 16 bits × 256 words.

  The delay time of the asynchronous absorption circuit 20 in FIG. 10 can be calculated by subtracting the time for writing the block data D8 to the single port RAM 1 at 80 MHz from the time for outputting the block data D7 and D8 at 50 MHz as in FIG.

  Therefore, the delay time can be estimated as 20 ns × (449 + 256) −12.5 ns × 256 = 10.9 us. As described above, the asynchronous absorption circuit 20 shown in the timing diagram of FIG. 10 has a delay time of 10.9 us, which is slightly longer than the asynchronous absorption circuit 20 of FIG. 6, but is sufficiently smaller than the horizontal synchronization signal interval HBLANK (20 us). ,no problem. The RAM switching table 24 referred to here is information that combines information on the storage capacity of the RAM connected as the two single-port RAMs 0 and 1 and information on timing for switching between reading and writing of the two single-port RAMs 0 and 1. .

  In a product having a plurality of different modes, the combination of necessary single port RAMs can be selected and switched from a plurality of single port RAMs by changing the RAM switching table 24.

  FIG. 11 is an explanatory diagram showing an example of a method of selecting a necessary combination of single port RAMs from a plurality of single port RAMs. The asynchronous absorption circuit 20 in FIG. 11A has a rewritable RAM switching table 24A, and rewrites the RAM switching table 24A rewritable by the CPU 40. The RAM selector 41 selects the single port RAMs 0 and 1 from the single port RAM-A to the single port RAM-D according to the rewritable RAM switching table 24A. The asynchronous absorption circuit 20 in FIG. 11A can intentionally increase the delay time by rewriting the timing information for switching the reading and writing of the two single-port RAMs 0 and 1.

  The asynchronous absorption circuit 20 in FIG. 11B has a plurality of fixed RAM switching tables 24B in advance, and the RAM switching table selector unit 42 automatically selects one from the plurality of fixed RAM switching tables 24B based on the mode (mode signal). One fixed RAM switching table 24B is selected. The RAM selector unit 41 selects the single port RAMs 0 and 1 from the single port RAM-A to the single port RAM-D according to the fixed RAM switching table 24B.

  The RAM selector unit 41 may treat a plurality of single port RAMs as one single port RAM. For example, the single port RAM-A and the single port RAM-B may be connected to form a single port RAM0. As described above, in a product having a plurality of different modes, it is very advantageous to be able to perform another asynchronous absorption by switching the single port RAM.

  FIG. 12 is an explanatory diagram of an example of a plurality of different modes. FIG. 12A is an explanatory diagram of an example of a two-stream mode in which normal video data and luminance information are scaled down and two grayscale video data are simultaneously flowed. A scale down with correction performed by the scale conversion circuit 50 with correction requires a RAM having a storage capacity of one line (1280 × 8 bits), so a 16-bit × 640 word single-port RAM-C is used.

  FIG. 12B is an explanatory diagram of an example of a low power consumption mode in which output data is reduced to 40 MHz instead of 50 MHz. When the low power consumption mode shown in FIG. 12B is further provided, the asynchronous absorption circuit 20 selects the single port RAM-C as the single port RAM0 and the single port RAM-A as the single port RAM1. it can.

  In order to realize the low power consumption mode, the conventional asynchronous absorption circuit 11 must have a 16-bit × 640-word dual-port RAM. In addition, the conventional asynchronous absorption circuit 11 must have a single port RAM-C used by the scale conversion circuit with correction 50 in order to realize the two-stream mode.

  Thus, in a product having a plurality of different modes, the conventional asynchronous absorption circuit 11 is disadvantageous in circuit scale as compared with the asynchronous absorption circuit 20 of the present embodiment. In addition, in a product having a plurality of different modes, when there are a plurality of portions that must be asynchronously absorbed, if all the portions are realized by the asynchronous absorption circuit 20 of the present embodiment, a single port RAM is provided for each mode. As a result, there are more choices for different types of circuits, which is more advantageous in terms of circuit scale than the conventional asynchronous absorption circuit 11.

  In the above description, the input data does not have the input side valid signal INVALID. When the input-side valid signal INVALID is included, the input speed of the input data is slow if there is an INVALID period. However, there is no inconvenience in the asynchronous absorption circuit 20 of the present embodiment. The RAM switching table 24 is created assuming that the input data has the maximum speed.

  The creation of the RAM switching table 24 and the selection of the storage capacities of the single port RAMs 0 and 1 can be realized, for example, by executing a program on a PC (personal computer) as shown in FIG. FIG. 13 is a hardware configuration diagram of an example of a PC. The PC includes an input device 61, an output device 62, a recording medium reading device 63, an auxiliary storage device 64, a main storage device 65, an arithmetic processing device 66, and an interface device 67 that are mutually connected by a bus 68.

  The input device 61 is a keyboard or a mouse. The input device 61 is used for inputting various signals. The output device 62 is a display device or the like. The output device 62 is used to display various windows and data. The interface device 67 is a modem, a LAN card, or the like. The interface device 67 is used for connecting to a network such as a LAN or the Internet.

  A program that realizes creation of the RAM switching table 24 and selection of the storage capacity of the single port RAMs 0 and 1 is provided by, for example, distribution of the recording medium 69 or downloading from a network or the like. A program that realizes creation of the RAM switching table 24 and selection of the storage capacities of the single port RAMs 0 and 1 is at least a part of a program executed on the PC.

  The recording medium 69 is a recording medium that records information optically, electrically, or magnetically, such as a CD-ROM, a flexible disk, or a magneto-optical disk, or a semiconductor that electrically records information, such as a ROM or flash memory. Various types of recording media such as a memory can be used.

  When the recording medium 69 on which the program is recorded is set in the recording medium reading device 63, the program is installed from the recording medium 69 to the auxiliary storage device 64 via the recording medium reading device 63. A program downloaded from a network or the like is installed in the auxiliary storage device 64 via the interface device 67.

  The auxiliary storage device 64 stores programs, necessary files, data, and the like. The main storage device 65 reads the program from the auxiliary storage device 64 and stores it when the program is started. The arithmetic processing unit 66 implements various functions in accordance with programs stored in the main storage device 65.

  First, a method for creating the RAM switching table 24 and a method for selecting the storage capacity of the single port RAMs 0 and 1 will be described.

  FIG. 14 is an explanatory diagram showing an example of the number of bits and the number of words of two single-port RAMs. The two single port RAMs 0 and 1 have the same number of bits (bit width). The number of words in the single port RAM0 is w0. The number of words in the single port RAM 1 is w1. The number of bits of input data and output data is the same as that of the single port RAMs 0 and 1. The word number w0 of the single port RAM0 and the word number w1 of the single port RAM1 are defined as in the following equations (1) and (2).

w0 ≧ w1 (1)
w0 and w1 are natural numbers (2)
Equation (1) indicates that the number of words w0 of the single port RAM0 is greater than or equal to the number of words w1 of the single port RAM1. If FAB (foundry) is determined, conditions such as multiples of 64, multiples of 128, etc. are added to equation (2).

  When the frequency of the clock signal ICLK is variable, there is no problem even with a slow frequency, so the estimation is performed with the maximum frequency. When the frequency of the clock signal OCLK is variable, there is no problem even at an early frequency, so the estimation is performed at the lowest frequency.

  The maximum frequency of the clock signal ICLK is assumed to be fin. The minimum frequency of the clock signal OCLK is fout. The frequency ratio k between the maximum frequency of the clock signal ICLK and the minimum frequency of the clock signal OCLK is defined as in the following equations (3) and (4).

k = fin / fout (3)
k> 1 (fin> 0 and fout> 0 and fin> fout) (4)
When k ≦ 1, the input data clock signal ICLK is slower than the output data clock signal OCLK. Therefore, when k ≦ 1, it is not necessary to use a memory having a large storage capacity for asynchronous absorption, and thus the description thereof is omitted.

  FIG. 15 is an explanatory diagram of an example of block data obtained by dividing input data. The maximum number of clocks in which input data continues is I. Assume that the number of input clocks of a data block formed by dividing the maximum clock number I by n is xn. The subscript n of the input clock number xn gives a large number to the data block that comes first. The relationship between the maximum clock number I and the input clock number xn is defined as in the following equations (5) and (6).

I = Σ (m = 1 to n) × m (5)
I, n and xn are natural numbers (6)
In the case of the asynchronous absorption circuit 20, the delay time of the asynchronous absorption unit 22 is t. In the case of the asynchronous absorption circuit 20A, t is a delay time required for switching clock signals for operating the two single port RAMs 0 and 1. The delay time t is rounded up based on the input clock number xn, and the time is defined by the input clock number xn. Note that the delay time t slightly varies depending on the mounting method of the asynchronous absorption circuit 20. In this embodiment, the maximum integer not exceeding the real number X is represented by [X]. The number of input clocks xn is defined as in the following equations (7) and (8).

When n ≧ 3, xn = [(x _n−1 −t) / k] (where xn does not exceed the word length of the memory) (7)
n is a natural number and is made as large as possible. xn must be a natural number. When n is equal to or greater than a certain number, xn is 0 or a negative number according to the equation (7), but all are 0. ... (8)
Further, in the following description, Expression (9) and Expression (10) are used.

Function f (x) = [(x−t) / k] (9)
Of the real numbers a and b, the smaller one is described as Min (a, b). (10)
In the following, the maximum number of input data clocks L that can be accepted with the determined storage capacity of the memory will be considered. The storage capacities of the two single port RAMs 0 and 1 may be such that the maximum input data clock number L is larger than the maximum clock number I.

  First, consider whether the data block of the last input clock number x1 divided by n should be stored in the single port RAM0 or the single port RAM1.

L = Σ (m = 4 to n) xm + x3 + x2 + x1 (11)
Regardless of whether the data block of the last input clock number x1 divided by n is stored in either the single port RAM0 or the single port RAM1, the following equation (12) is established.

x2 + x1 = w1 + w0 = w0 + w1 (12)
The maximum number of input data clocks L becomes larger when x3 is larger than Expression (7). Whether the data block of the last input clock number x1 should be stored in the single-port RAM0 or the single-port RAM1 should be stored in the single-port RAM1 lastly from the relationship of the following equation (13). I understand.

Min (wo, f (w1)) ≦ Min (w1, f (w0)) (13)
Proof: Proposition Min (wo, f (w1)) ≦ Min (w1, f (w0))
From equation (1), equation (4) and equation (9), w0 ≧ w1 ≧ f (w1)
Min (wo, f (w1)) = f (w1)
Since w1 ≧ f (w1) and f (w0) ≧ f (w1)
Min (w1, f (w0)) ≧ f (w1)
Therefore, Min (wo, f (w1)) ≦ Min (w1, f (w0))
From the above, the maximum input data clock number L is expressed by the following equation (14).

L = Σ (m = 4 to n) × m + Min (w1, f (w0)) + wo + w1 (14)
Further, the RAM switching table 24 is created, for example, according to the flowchart shown in FIG. FIG. 16 is a flowchart illustrating an example of a procedure for creating the RAM switching table. The flowchart of FIG. 16 shows a procedure including an asynchronous absorption circuit specification determination stage S1, an FAB selection stage S2, a combination of RAMs, and a RAM switching table creation stage S3.

  The asynchronous absorption circuit specification determination stage S1 is a procedure for determining data information to be asynchronously absorbed. The FAB selection stage S2 is a procedure for selecting all the single-port RAMs having the number of Words in the FAB in the single-port RAM having the bit width of the data. The RAM combination and the RAM switching table creation stage S3 are procedures for outputting a usable single port RAM combination capable of asynchronous absorption within a predetermined delay time and the RAM switching table 24.

L = Σ (m = 1 to n) × m
= Σ (m = 1 to ∞) xm
= Σ (m = 4 to ∞) xm + Min (w1, f (w0)) + wo + w1 (15)
N is the one before xm becomes 0 only after increasing the value of m in equation (15). L can be obtained using spreadsheet software or the like. In order to reduce the delay time of asynchronous absorption, the input clock number x2 may be reduced so that the maximum input data clock number L is equal to the maximum clock number I of continuous input data. Let x2 = w0− (LI). The asynchronous absorption delay time at that time is expressed by the following equation (16).

(Delay time) = w1 / fin− (w0− (LI)) / fout (16)
In Expression (15), the division number n is made as large as possible so that L becomes large (so that L ≧ I can be satisfied with w0 and w1 as small as possible). In the hardware design, when it is desired to be within a certain number of switching times, the maximum value of n is limited and obtained. Further, in the above, it has been proved that the number of input data clocks L is larger when stored last in the single-port RAM 1, but if L ≧ I, it may be stored last in the single-port RAM 0. .

  Hereinafter, the asynchronous absorption circuit specification determination stage S1, the FAB selection stage S2, the combination of RAM, and the RAM switching table creation stage S3 will be described in detail. Data is assumed to be 1 byte / clock for easy understanding.

  In the case of 1 byte / clock, the storage capacity of the single-port RAM 0 matches the number of clocks, so that it is easy to understand. Similarly, the number of words and the storage capacity of the single port RAMs 0 and 1 are the same. For ease of explanation, the following description will be made using an Excel (registered trademark) function as an example of spreadsheet software.

  In the asynchronous absorption circuit specification determination stage S1, first, as the data information to be asynchronously absorbed, the maximum frequency fin of the clock signal ICLK, the minimum frequency fout of the clock signal OCLK, the maximum number of clocks I in which input data continues, The delay time t required for switching the clock signal as an example of the delay time 22 is determined as follows.

fin = 80MHz
fout = 50MHz
I = 1280
t = 11 clk (fin)
As described above, the delay time t of the asynchronous absorption unit 22 differs depending on whether the asynchronous absorption circuit 20 in FIG. 6 or the asynchronous absorption circuit 20A in FIG. The delay time t of the asynchronous absorption unit 22 is a time required for asynchronous absorption of data, but the maximum frequency fin of the clock signal ICLK, the minimum frequency fout of the clock signal OCLK, and the method of asynchronous absorption (FF two-stage reception, FF three-stage reception, etc.) And the size of the process (65 nano, 90 nano, etc.). The delay time t of the asynchronous absorption unit 22 may be increased based on the ASIC rule or the like. The delay time t of the asynchronous absorber 22 is determined by the designer according to use, for example.

  Next, in the FAB selection stage S2, all the single-port RAMs having the storage capacity in the FAB with the single-port RAM having the data bit width are selected as follows. In an FAB having a single-port RAM in increments of 128B (bytes), for example, a combination that satisfies L ≧ I is searched for in a combination of 128B, 256B, 384B, and 512B.

  For example, the delay time slightly increases (effective output speed is slow) as compared with the asynchronous absorption circuit 11 using the dual port RAM 13, so that the maximum frequency fin of the input data clock signal ICLK does not change. The total storage capacity of the single-port RAMs 0 and 1 of the asynchronous absorption circuits 20 and 20A must be theoretically larger than the storage capacity of the dual-port RAM 13.

  When the asynchronous absorption circuit 11 using the dual port RAM 13 requires 480B, the total storage capacity of the single port RAMs 0 and 1 of the asynchronous absorption circuit 20 and 20A of the present embodiment is more than 480B. It becomes a standard for searching for the storage capacity of the single port RAMs 0 and 1 used in the absorption circuits 20 and 20A.

  Conversely, the sum of the storage capacities of the single-port RAMs 0 and 1 of the asynchronous absorption circuits 20 and 20A of the present embodiment is a specification that the maximum number of clocks I in which input data continues is 1280 and can be output while being input. , 1280B or more is not required.

  FIG. 17 is an explanatory diagram showing an example of a combination of storage capacity single port RAMs in the FAB. In FIG. 17, the area of w0 <w1 is filled with black based on the above equation (1). In the FAB selection stage, a combination of single port RAMs in which L ≧ I and w0 + w1 is minimized is searched for.

  In FIG. 17, “◯” is attached to the combination cell of the single port RAM satisfying L ≧ I, and “×” is attached to the combination cell of the single port RAM satisfying L <I. As shown in FIG. 17, the lower right region when viewed from the “×” cell is “×”. The upper left area when viewed from the “◯” cell is “◯”.

  Eventually, in FIG. 17, it can be seen that the combination of the storage capacities of the single-port RAMs that minimizes the combination of 384B + 384B or 512B + 256B. For reference, FIG. 17 also appears that the combination of 640B + 128B may be “◯”. However, since the total storage capacity of w0 and w1 is not reduced, there is no need to consider unless there is a special circumstance (for example, the 640B single-port RAM is also used for other purposes). The asynchronous absorption delay time is expressed by the following equation (17).

t / fin + (x1 + x2) / fout−x1 / fin (17)
Referring to equation (17), it can be seen that if x1 + x2 is constant, the greater the x1, the shorter the asynchronous absorption delay time. If the increment of the storage capacity of the existing single-port RAM is sufficiently large, x1≈w1, x2≈w0 and w0 ≧ w1, so | w0−w1 | is large under the minimum w0 and w1. As a result, the delay time of asynchronous absorption is expected to increase. If you want to increase the delay time (decrease the effective output speed), it is worth considering. When actually calculated, the combination of 640B + 128B is “×” because L <I.

  W0 + w1 is the minimum based on Rule 1 that the lower right area is “X” when viewed from the “×” cell and Rule 2 that the upper left area is “O” when viewed from the “O” cell. It is possible to create software that outputs a combination of The software is convenient for searching for a large number of combinations of single port RAMs when the storage capacity of the single port RAMs is fine.

  Next, in the RAM combination and RAM switching table creation stage S3, a combination of usable single port RAMs capable of asynchronous absorption within a predetermined delay time and the RAM switching table 24 are output. Hereinafter, the creation of the RAM switching table 24 in the timing chart shown in FIGS. 7 and 10 will be described.

  In the case of the timing diagram of FIG. 7, x1 to xn are expressed as follows.

x1 = 384
x2 = 384
x3 = Max (Min (x1, ROUNDDOWN ((x2-t) / k, 0)), 0)
xn = Max (ROUNDDOWN ((x _n-1 -t) / k, 0), 0)
Note that ROUNDDOWN (numerical value, number of digits) is a function that returns a numerical value rounded down to the specified number of digits. The number of digits 0 indicates that the value is rounded down to the first decimal place. Also, ROUNDUP (numerical value, number of digits), which will be described later, is a function that rounds up a numerical value to a specified number of digits and returns it.

  First, when the maximum number of input data clocks L that can be accepted by a combination of 384B + 384B single-port RAMs is obtained, L = Σxn = 1284. Since the maximum number of clocks I = 1280 in which input data continues, 4 bytes (clocks) out of the maximum number of input data clocks L = 1284 are unnecessary.

  Therefore, unnecessary 4 bytes can be subtracted from x1 or x2. Referring to the equation (17), if x1 + x2 is constant, it is better to subtract from x2, but since x3 = 233, x2 needs to satisfy ROUNDUP (x3 × k + t, 0) ≧ 384 . For this reason, unnecessary 4 bytes are subtracted from x1. As a result, a RAM switching table 24 as shown in Table 1 is created. In order to minimize the delay time of asynchronous absorption, it is left up to the designer to solve the simultaneous inequality and obtain the answer.

図１０のタイミング図の場合は、ｘ１からｘｎは以下のように表される。

In the case of the timing diagram of FIG. 10, x1 to xn are expressed as follows.

x1 = 256
x2 = 512
x3 = Max (Min (x1, ROUNDDOWN ((x2-t) / k, 0)), 0)
xn = Max (ROUNDDOWN ((x _n-1 -t) / k, 0), 0)
First, when the maximum number of input data clocks L that can be accepted by a combination of 512B + 256B single port RAM is obtained, L = Σxn = 1343. Since the maximum clock number I = 1280 for which input data continues, 63 bytes (clocks) of the maximum input data clock number L = 1343 are not required. Therefore, unnecessary 63 bytes can be subtracted from x1 or x2.

  Referring to the above equation (17), if x1 + x2 is constant, it is better to subtract from x2. Therefore, x2 = 512-63 = 449. Since x3 = 256, x2 can satisfy the condition of ROUNDUP (x3 × k + t, 0) ≧ 421. Therefore, the RAM switching table 24 is as shown in Table 2.

なお、上記は機械的な回答例であって、回路が動作するＲＡＭ切り替えテーブル２４は１つではない。例えば切り替え回数を少なくしたいならば、ＲＡＭ切り替えテーブル２４はｘ７及びｘ８を０にすることも可能である。

The above is a mechanical answer example, and there is not one RAM switching table 24 on which the circuit operates. For example, if it is desired to reduce the number of switching times, the RAM switching table 24 can set x7 and x8 to zero.

  For example, if it is desired to create a switching table for an IC that has all tables as registers and can only store values up to x6, it is necessary to set x7 and x8 to zero. In the case where the table is generated in the IC, infinite switching is allowed, so there is no need for such a table. Fine adjustment is left to the designer depending on the application.

  FIG. 18 is an explanatory diagram of an example showing the delay time of asynchronous absorption. The above equation (17) is generated from the relationship shown in FIG. Note that t / fin in equation (17) is a very small value and may be ignored.

  FIG. 19 is a configuration diagram of an example of a sheet for creating a RAM switching table. FIG. 20 is a configuration diagram of another example of a sheet for creating a RAM switching table. The sheet of FIG. 19 shows an example of creating the RAM switching table 24 shown in the timing chart of FIG. The sheet of FIG. 20 shows an example of creating the RAM switching table 24 shown in the timing chart of FIG.

  19 and 20 show the maximum frequency fin of the clock signal ICLK, the minimum frequency fout of the clock signal OCLK, the maximum number of clocks I in which the input data continues, the Word number w0 of the single port RAM0, and the single port RAM1. It represents that the RAM switching table 24 is created by inputting numerical values to the word number w1 and a and b of the function t = ak + b for calculating t from k.

  According to the present embodiment, asynchronous absorption (speed conversion) can be performed using a single port RAM without using a dual port RAM, and the chip size can be greatly reduced as compared with the dual port RAM. In addition, by using two single-port RAMs and a RAM switching table 24, this embodiment uses a memory such as a RAM for each mode in a product having a plurality of different modes, thereby reducing the circuit scale and further reducing power consumption. Can also be lowered.

  The present invention is not limited to the specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims. The write operation means described in the claims corresponds to the write operation unit 26. The read operation means corresponds to the read operation unit 27. The switching means corresponds to the RAM selector unit 28.

  The switching control unit corresponds to the switching determination unit 25. The asynchronous absorption means corresponds to the built-in FF unit 29 or the CLK generation circuit 30. The switching timing recording means corresponds to the RAM switching table 24.

0, 1 single port RAM
10 Input data I / F
11 Asynchronous absorption circuit 12 Output data I / F
13 Dual port RAM
20, 20A Asynchronous absorption circuit 21 Synchronous absorption unit 22 Asynchronous absorption unit 23 Data number (CLK number) count unit 24, 24A, 24B RAM switching table 25 Switching determination unit 26 Write operation unit 27 Read operation unit 28 RAM selector unit 29 Built-in FF (Flip-flop) section 30 CLK generation circuit 31 CLK selector section 40 CPU
41 RAM selector section 42 RAM switching table selector section 50 Scale conversion circuit with correction 61 Input device 62 Output device 63 Recording medium reader 64 Auxiliary storage device 65 Main storage device 66 Arithmetic processing device 67 Interface device 68 Bus

JP 2010-134646 A JP 2007-249010 A

Claims (7)

And write operations means the storage capacity performs the write operation of the input data into small Ifuku number storage means than the image one line, respectively,
A read operation means for performing a read operation of output data from the storage means;
Switching means for switching the storage means to be written by the write operation means and read by the read operation means;
Switching control means for controlling switching of the storage means by the switching means based on the timing at which the block data obtained by dividing the input data for one line of the image into the storage means is distributed;
An asynchronous absorption circuit comprising: asynchronous absorption means for converting the data read by the read operation means from a clock signal of input data to a clock signal of output data and outputting the same . 2. The asynchronous absorption circuit according to claim 1, further comprising switching timing recording means for recording a timing at which block data obtained by dividing input data for one line of image into a plurality of storage means is recorded. In the case where the plurality of storage means are two storage means, the switching timing recording means, when the number of block data is n, until the reading operation of the n-2th block data from the storage means, n -1 -th to end earlier than the writing operation to the memory means of the block data, asynchronous absorption according to claim 2, wherein the block data is recording timing to be distributed to said storage means circuit. 4. The asynchronous absorption means converts the data read by the read operation means from a clock signal of input data into a clock signal of output data by using a flip-flop means and outputs the data. The asynchronous absorption circuit according to any one of claims. The asynchronous absorption means uses a clock signal for operating the storage means as a clock signal of the input data when performing an operation of writing input data to the storage means, and reads out output data from the storage means 4. The data read by the read operation means as a clock signal of the output data at the time of performing the conversion is converted from a clock signal of the input data to a clock signal of the output data and output. An asynchronous absorption circuit according to claim 1.   An image processing apparatus comprising the asynchronous absorption circuit according to claim 1. And write operations means the storage capacity performs the write operation of the input data into small Ifuku number storage means than the image one line, respectively,
A read operation means for performing a read operation of output data from the storage means;
Switching means for switching the storage means to be written by the write operation means and read by the read operation means;
Switching control means for controlling switching of the storage means by the switching means based on the timing at which the block data obtained by dividing the input data for one line of the image into the storage means is distributed;
A computer for generating a switching timing recording means of an asynchronous absorption circuit having an asynchronous absorption means for converting the data read by the read operation means from a clock signal of input data to a clock signal of output data and outputting the clock signal;
A specification determining step for receiving information on data to be converted from a clock signal of input data to a clock signal of output data and outputting ;
A selection step of selecting a storage means having the same storage capacity as the bit width of the data and available;
The combination of the selected storage means capable of converting the input data clock signal into the output data clock signal within the determined delay time and outputting the data, and block data obtained by dividing the input data for one line of the image into a plurality of data. A program for executing a creation step for creating a switching timing recording means for recording a timing assigned to the storage means.

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