JP5814554B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device including a step of forming a multilayer wiring structure on a bonded wafer manufactured by bonding a silicon layer to an insulating substrate.

  2. Description of the Related Art In recent years, SOQ (Silicon-On-Quartz) wafers manufactured by bonding a silicon (Si) layer to a quartz plate as an insulating substrate have been used for manufacturing semiconductor devices. Since the Si layer of the SOQ wafer has few defects and high quality, a high-performance and highly reliable semiconductor device can be manufactured by using the SOQ wafer.

  However, generally, the thermal expansion coefficient of quartz is lower than the thermal expansion coefficient of Si, so cracks are likely to occur in an SOQ wafer manufactured by bonding a Si layer to a quartz plate (see, for example, Patent Document 1). ). As shown in the cross-sectional view of FIG. 1 and the enlarged photograph of FIG. 2, normally, compressive stress C1 is generated in the quartz plate 101 of the SOQ wafer 103, and the outside of the Si layer 102 is exposed as the temperature rises. Since a direction stress T1 is generated, a crack 105 is likely to occur in the quartz plate 101 and the Si layer 102 starting from the vicinity of the bonding surface 104 between the quartz plate 101 and the Si layer 102. As shown in the plan view of FIG. 3 and the enlarged photograph of FIG. 4, the crack 105 is particularly likely to occur in the peripheral vicinity region 106 of the bonding surface 104 of the SOQ wafer 103, and the crack 105 reaches the chip formation region 107. Sometimes. The reason for this is that in the vicinity of the outer periphery 106 of the SOQ wafer 103, there are a jagged shape that can be the starting point of the crack 105 and the floating of the Si layer 102 (reference numeral 102a in the enlarged photograph in FIG. 5). This is because there are many defects (reference numeral 102b in the enlarged photograph in FIG. 6).

  As a countermeasure against this, as shown in the plan view of FIG. 7, the semiconductor chip portion disposed on the outer peripheral side of the chip formation region 125 of the SOQ wafer 123 manufactured by bonding the Si layer 122 to the quartz plate 121, There is a method in which a dummy chip portion 126 (shaded area) that is not used as a product (separated semiconductor chip) is used, and a semiconductor chip portion other than the dummy chip section 126 is used as a product chip portion 127 (area that is not shaded). is there.

JP 2009-188008 A

  However, if the insulating film and metal layer formation process is repeated to form a multilayer wiring structure on the bonded wafer, the micro cracks gradually become larger and may extend into the product chip portion. There has been a problem in that the quality of a semiconductor device manufactured using the chip portion is reduced and the manufacturing yield is reduced.

  Accordingly, the present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide a semiconductor device manufacturing method capable of improving the quality and manufacturing yield of the semiconductor device. .

A method of manufacturing a semiconductor device according to one embodiment of the present invention includes a step of forming a plurality of semiconductor chip portions on a bonded wafer manufactured by bonding a silicon layer to an insulating substrate, a lower layer including an insulating film, A multilayer wiring structure in which a plurality of wiring layers are stacked on the plurality of semiconductor chip portions by performing a process of forming a wiring layer having an upper layer including a metal wiring provided on the lower layer a plurality of times. The plurality of semiconductor chip portions include a product chip portion that is used as a semiconductor chip after singulation and a dummy chip portion that is not used, and a plurality of the semiconductor chip portions are stacked on the dummy chip portion. The wiring layer includes a first wiring layer having the same shape as the wiring layer on the product chip portion, and a second wiring layer having a shape different from the first wiring layer, and the dummy layer The lower layer in any of a plurality superposed said wiring layer onto-up unit, Ri insulating film der that no through metal wiring, the insulating substrate is composed mainly of either quartz or quartz substrate It is characterized by including .

  If the method for manufacturing a semiconductor device according to the present invention is used, there is an effect that the quality and the manufacturing yield of the semiconductor device can be improved.

It is sectional drawing which shows the compressive stress in the quartz board in the conventional SOQ wafer, the thermal stress in a wiring layer, and a crack. It is an enlarged photograph which shows the crack which generate | occur | produces in the conventional SOQ wafer. It is a top view which shows roughly an example of the crack generation position in the outer periphery vicinity area | region of the conventional SOQ wafer. It is an enlarged photograph which shows the crack which generate | occur | produces in the peripheral vicinity area | region of the conventional SOQ wafer. It is an enlarged photograph which shows the jagged shape of the Si layer (within the broken line circle on the left side) and the floating of the Si layer (the tip of the right jagged shape) in the peripheral vicinity region of the conventional SOQ wafer. It is an enlarged photograph which shows the void of the Si layer in the outer periphery vicinity area | region of the conventional SOQ wafer. It is a top view which shows roughly an example of arrangement | positioning of the product chip part and dummy chip part which are the semiconductor chips formed on the SOQ wafer in the prior art and the 1st and 2nd embodiment. It is a figure which shows the cross-section of the dummy chip part manufactured by the manufacturing method of the semiconductor device of the 1st comparative example, the compressive stress in a quartz board, and the thermal stress in a wiring layer. It is a figure which shows the cross-section of the dummy chip part manufactured by the manufacturing method of the semiconductor device of the 2nd comparative example, the compressive stress in a quartz board, and the thermal stress in a wiring layer. It is a figure which shows roughly the structure of one dummy chip part among the several semiconductor chip parts manufactured by the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a longitudinal cross-sectional view which shows roughly the dummy chip part among the semiconductor chip parts manufactured by the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the compressive stress in the quartz board in the dummy chip part among the semiconductor chip parts shown by FIG. 11, and the thermal stress in a wiring layer. It is a longitudinal cross-sectional view which shows schematically the dummy chip part among the semiconductor chip parts manufactured by the modification of the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a longitudinal cross-sectional view which shows schematically the dummy chip part among the semiconductor chip parts manufactured by the other modification of the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a longitudinal cross-sectional view which shows roughly the dummy chip part among the semiconductor chip parts manufactured by the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a figure which shows the compressive stress in the quartz board in the dummy chip part of the semiconductor chip parts shown by FIG. 15, and the thermal stress in a wiring layer. It is a longitudinal cross-sectional view which shows schematically the dummy chip part among the semiconductor chip parts manufactured by the modification of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a longitudinal cross-sectional view which shows schematically the dummy chip part among the semiconductor chip parts manufactured by the other modification of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a top view which shows roughly the other example of arrangement | positioning of the product chip part and dummy chip part which are the semiconductor chips formed on the SOQ wafer in 1st and 2nd embodiment. It is a top view which shows roughly still another example of arrangement | positioning of the product chip part which is a semiconductor chip formed on the SOQ wafer in 1st and 2nd embodiment, and a dummy chip part.

<< 1 >> Outline of Embodiment << 1-1 >> First Comparative Example First, a method of manufacturing a semiconductor device of a first comparative example used for explaining the effects of the method of manufacturing a semiconductor device according to the embodiment of the present invention. Will be explained. FIG. 8 is a diagram showing the cross-sectional structure of the dummy chip portion manufactured by the method for manufacturing the semiconductor device of the first comparative example, the compressive stress in the quartz plate 1, and the thermal stress in the wiring layers 41, 42, and 43. . In the semiconductor device manufacturing method of the first comparative example, the essential function of the semiconductor chip is assigned to the SOQ wafer 3 which is a bonded wafer manufactured by bonding the Si layer 2 to the quartz plate 1 as an insulating substrate. By forming a circuit element (or integrated circuit) or the like, a plurality of semiconductor chip portions (rectangular regions 126 and 127 in FIG. 7) are formed in a chip formation region (region 125 in FIG. 7), and multilayer wiring is formed thereon. Structure 4 is formed.

  In forming the multilayer wiring structure 4, first, a dummy chip is formed on the Si layer 2 of the SOQ wafer 3 by the same formation process as the wiring layer forming process (using photolithography technology, CVD method, etc.) on the product chip portion. A wiring layer 41 on the part is formed. In the example of FIG. 8, the wiring layer 41 on the dummy chip portion has a lower layer 411 and an upper layer 412. The lower layer 411 has an insulating film 411b and a through metal wiring (metal plug) 411a, and the upper layer 412 has an insulating film 412b and a metal wiring (patterned metal layer) 412a.

  Next, the wiring layer 42 on the dummy chip portion is formed on the wiring layer 41 on the dummy chip portion by the same formation process as the wiring layer forming process (using photolithography technology, CVD method, etc.) on the product chip portion. Form. In the example of FIG. 8, the wiring layer 42 has a lower layer 421 and an upper layer 422. The lower layer 421 has an insulating film 421b and a through metal wiring (metal plug) 421a, and the upper layer 422 has an insulating film 422b and a metal wiring (patterned metal layer) 422a.

  Next, the wiring layer 43 on the dummy chip portion is formed on the wiring layer 42 on the dummy chip portion by the same formation process as the wiring layer forming process (using photolithography technology, CVD method, etc.) on the product chip portion. Form. In the example of FIG. 8, the wiring layer 43 includes a lower layer 431, and the lower layer 431 includes an insulating film 431b and a through metal wiring 431a.

  When the multilayer wiring structure 4 of the first comparative example shown in FIG. 8 is formed on the SOQ wafer 3, in addition to the influence of thermal stress generated in the metal wirings 412a and 422a, the through metal wirings 411a, 421a, The influence of the thermal stress generated in 431a is given to the SOQ wafer 3. In other words, the thermal expansion coefficient of the constituent material of the metal wiring is larger than both of the thermal expansion coefficient of the quartz plate 1 constituting the SOQ wafer 3 and the thermal expansion coefficient of the Si layer 2. Receives a pulling force F <b> 1 outward in the horizontal direction from the multilayer wiring structure 4. Furthermore, in the configuration of FIG. 8, the through metal wirings 411 a, 421 a, and 431 a overlap directly above the SOQ wafer 3, and the through metal wirings 411 a, 421 a, and 431 a exist at positions close to the SOQ wafer 3. The horizontal outward pulling force F1 that the SOQ wafer 3 receives from the multilayer wiring structure 4 is likely to be concentrated directly below the through metal wiring 411a. For this reason, for example, a horizontal tensile force corresponding to the thermal stress generated in the through metal wirings 411a, 421a, 431a (indicated by an outward arrow in FIG. 8) is formed in the portion directly below the through metal wiring 411a of the SOQ wafer 3. Force) is applied locally, and the crack 105 is likely to occur in the SOQ wafer 3.

<< 1-2 >> Second Comparative Example A semiconductor device manufacturing method of a second comparative example used for explaining the effects of the method of manufacturing a semiconductor device according to the embodiment of the present invention will be described. FIG. 9 is a diagram showing a cross-sectional structure of the dummy chip portion manufactured by the semiconductor device manufacturing method of the second comparative example, a compressive stress in the quartz plate 1, and a thermal stress in the wiring layers 51, 52 and 53. . In the semiconductor device manufacturing method of the second comparative example, first, an essential function of the semiconductor chip is applied to the SOQ wafer 3 which is a bonded wafer manufactured by bonding the Si layer 2 to the quartz plate 1 as an insulating substrate. A plurality of semiconductor chip portions (rectangular regions 126 and 127 in FIG. 7) are formed in a chip formation region (region 125 in FIG. 7) by forming a circuit element (or integrated circuit) that bears A multilayer wiring structure 5 is formed.

  In forming the multilayer wiring structure 5, first, the wiring layer 51 on the dummy chip portion is formed on the Si layer 2 of the SOQ wafer 3 by using a photolithography technique and a CVD method. In the example of FIG. 9, the wiring layer 51 has a lower layer 511 and an upper layer 512, and the entire area (entire surface) of the lower layer 511 is an insulating film such as a silicon oxide film. The entire region (entire surface) is a metal layer.

  Next, the wiring layer 52 on the dummy chip part is formed on the wiring layer 51 in the same manner as the formation process of the wiring layer 51. In the example of FIG. 9, the wiring layer 52 includes a lower layer 521 and an upper layer 522, and the entire area (entire surface) of the lower layer 521 is an insulating film such as a silicon oxide film. The entire region (entire surface) is a metal layer.

  Next, the wiring layer 53 on the dummy chip portion is formed on the wiring layer 52 in the same manner as the formation process of the wiring layer 52. In the example of FIG. 9, the wiring layer 53 has a lower layer 531, and the entire area (entire surface) of the lower layer 531 is an insulating film such as a silicon oxide film.

  When the multilayer wiring structure 5 of the second comparative example shown in FIG. 9 is formed on the SOQ wafer 3, there is an influence of thermal stress generated in the upper layers (metal layers) 512 and 522 of the wiring layers 51 and 52. , Given to the SOQ wafer 3. In other words, the thermal expansion coefficient of the constituent material of the metal layer is larger than both the thermal expansion coefficient of the quartz plate 1 constituting the SOQ wafer 3 and the thermal expansion coefficient of the Si layer 2, so that the SOQ wafer 3 is increased as the temperature rises. Receives a horizontal outward pulling force F <b> 2 from the multilayer wiring structure 5. In addition, since the upper layers (metal layers) 512 and 522 of the wiring layers 51 and 52 are formed over the entire area (entire surface) of the dummy chip portion, the thermal stress generated in the upper layers (metal layers) 512 and 522 is In addition, since a plurality of upper layers (metal layers) 512 and 522 are overlapped and arranged at a position close to the SOQ wafer 3 (a wiring layer 51 closest to the SOQ wafer and a wiring layer 52 closest to the second), A horizontal outward pulling force (force indicated by an outward arrow in FIG. 9) F2 applied to the SOQ wafer 3 corresponding to the thermal stress generated in these becomes a large force, and a crack 105 is formed in the SOQ wafer 3. Is likely to occur.

<< 1-3 >> Principle of the Embodiment FIG. 10 is a diagram schematically showing the structure of the dummy chip portion of the semiconductor chip portion manufactured by the method of manufacturing a semiconductor device according to the embodiment of the present invention. . As shown in FIG. 10, in the method of manufacturing a semiconductor device according to the embodiment of the present invention, an SOQ wafer that is a bonded wafer manufactured by bonding a Si layer 2 to a quartz plate 1 as an insulating substrate. 3 is formed with a plurality of semiconductor chip portions (rectangular regions 126 in FIG. 7) in a chip formation region (region 125 in FIG. 7) by forming circuit elements (or integrated circuits) or the like that bear the essential functions of the semiconductor chip. And 127), and the multilayer wiring structure 6 is formed thereon. The plurality of semiconductor chip portions include a product chip portion (rectangular region 127 in FIG. 7) that is used as a semiconductor chip after singulation, and a dummy chip portion (126 in FIG. 7) that is not used.

  In forming the multilayer wiring structure 6, first, a wiring layer 61 having a lower layer 611 including an insulating film and an upper layer 612 including metal wiring provided thereon is formed on the Si layer 2 of the SOQ wafer 3. To do. The wiring layer 61 is the wiring layer closest to the SOQ wafer 3.

  Next, a wiring layer 62 having a lower layer 621 including an insulating film and an upper layer 622 including a metal wiring provided thereon is formed on the wiring layer 61. The wiring layer 62 is the wiring layer closest to the SOQ wafer 3.

  If necessary, a wiring layer 63 having a lower layer 631 including an insulating film and an upper layer 632 including a metal wiring provided thereon is formed on the wiring layer 62. The wiring layer 63 is the third closest wiring layer to the SOQ wafer 3. Furthermore, one or more wiring layers are formed on the wiring layer 63 as necessary. Note that the wiring layers after the wiring layer 63 are not essential components.

  A plurality of wiring layers 61, 62,... Stacked on the dummy chip portion include a first wiring layer (61 or 62,...) Having the same shape as the wiring layer on the product chip portion, and a first wiring layer. And a second wiring layer (62 or 61,...) Having a different shape. The upper layer in the second wiring layer is, for example, a layer in which the entire area (entire surface) of the dummy chip portion is a metal layer.

  The first wiring layer (61 or 62,...) On the dummy chip portion having the same shape as the wiring layer on the product chip portion is formed by a process for forming the wiring layer on the product chip portion (photolithography technology, CVD method, etc.). A wiring layer (61 or 62,...) Formed on the dummy chip portion by the same forming process as that used.

  In the multilayer wiring structure 6 of FIG. 10, the lower layer (611, 621,...) In any of the wiring layers stacked on the dummy chip portion is an insulating film having no through metal wiring (metal plug). is there. A specific example of the structure of the wiring layers 61, 62,... Will be described in the first and second embodiments.

  In the multilayer wiring structure 6 shown in FIG. 10, a plurality of wiring layers 61, 62,... Overlaid on the dummy chip portion are first wiring layers having the same shape as the wiring layer on the product chip portion (for example, Wiring layer 61 or 62) and a second wiring layer (for example, wiring layer 62 or 61) having a shape different from that of the first wiring layer. As described above, when a plurality of wiring layers (for example, the wiring layers 61 and 62) stacked on the dummy chip portion have different shapes (wiring patterns), the wiring layers (for example, the wiring layers) 61 and 62) alleviating the influence of the tensile force applied to the SOQ wafer 3 corresponding to the thermal stress generated in the same position of the SOQ wafer 3 as the forces F1 and F2 in FIGS. it can.

  For example, in the case of the first comparative example of FIG. 8, a portion directly below the through metal wiring 411a of the SOQ wafer 3 due to the influence of thermal stress generated in the through metal wirings 411a, 421a and 431a formed with the same wiring pattern. In addition, a large horizontal pulling force (force indicated by an outward arrow F1 in FIG. 8) is applied locally, and cracks 105 are likely to occur in the SOQ wafer 3. However, in the method of manufacturing the semiconductor device according to the embodiment shown in FIG. 10, the wiring layers 61, 62,... Stacked on the dummy chip portion have different shapes (wiring patterns). The lower layer (611, 621,...) In any of the wiring layers that are included and overlapped on the dummy chip portion is an insulating film that does not have a through metal wiring, and therefore the SOQ wafer 3 is specified. It is possible to prevent an undesirable situation in which a large horizontal force is locally applied to a location (for example, directly below the through metal wiring).

  Similarly, for example, in the case of the second comparative example shown in FIG. 9, it is locally applied to a specific portion of the SOQ wafer 3 due to the influence of thermal stress generated in the large-area upper layers (metal layers) 512 and 522 having the same shape. A large horizontal pulling force (the force indicated by the outward arrow F2 in FIG. 9) is applied to the SOQ wafer 3, and cracks are likely to occur in the SOQ wafer 3. However, in the method of manufacturing the semiconductor device according to the embodiment shown in FIG. 10, the wiring layers 61, 62,... Stacked on the dummy chip portion have different shapes (wiring patterns). It is possible to prevent an undesirable situation in which a large horizontal force is locally applied to a specific portion of the wafer 3.

<< 2 >> First Embodiment FIG. 11 is a longitudinal sectional view schematically showing a dummy chip portion of a semiconductor chip portion manufactured by a method for manufacturing a semiconductor device according to a first embodiment of the present invention. . As shown in FIG. 11, in the method of manufacturing a semiconductor device according to the first embodiment, a semiconductor chip is attached to a SOQ wafer 3 that is a bonded wafer manufactured by bonding a Si layer 2 to a quartz plate 1. A plurality of semiconductor chip portions (rectangular regions 126 and 127 in FIG. 7) are formed in a chip formation region (region 125 in FIG. 7) by forming a circuit element (or an integrated circuit) or the like responsible for the essential functions of Then, a multilayer wiring structure 7 is formed thereon. The plurality of semiconductor chip portions include a product chip portion (rectangular region 127 in FIG. 7) used as a semiconductor chip after separation, and a dummy chip portion (rectangular cross-hatching region 126 in FIG. 7) that is not used. including.

  In forming the multilayer wiring structure 7, first, a wiring having a lower layer 711 including an insulating film and an upper layer 712 including a metal layer as a metal wiring provided thereon on the Si layer 2 of the SOQ wafer 3. Layer 71 is formed. The lower layer 711 is, for example, a silicon oxide film or a silicon nitride film, and is formed by a CVD method or the like. The upper layer 712 is a metal layer formed on the entire surface of the dummy chip portion, for example, and is formed by a CVD method or the like. As the metal layer, metal wiring, and through metal wiring, for example, conductive metals and alloys including tungsten, copper, aluminum, and the like can be used.

  Next, a wiring layer 72 having a lower layer 721 including an insulating film and an upper layer 722 including a metal wiring provided thereon is formed on the wiring layer 71. The lower layer 721 is, for example, a silicon oxide film or a silicon nitride film, and is formed by a CVD method or the like. The upper layer 722 is formed by the same formation process as the formation process of the wiring layer on the product chip portion by using a photolithography technique and a CVD method. The upper layer 722 includes an insulating film 722b and a metal wiring 722a. The shape of the metal wiring 722a is not limited to the illustrated example, and may be another shape having the same shape as the wiring pattern of the product chip portion.

  Next, the wiring layer 73 on the dummy chip portion is formed on the wiring layer 72 by the same formation process as that for forming the wiring layer on the product chip portion (using a photolithographic technique and a CVD method). The wiring layer 73 has a lower layer 731, and the lower layer 731 has an insulating film 731 b and a through metal wiring 731 a. Further, the position, shape, and number of the through metal wiring 731a are not limited to the illustrated example, and various positions, various shapes, and various numbers can be adopted according to the wiring pattern of the product chip portion. .

  FIG. 12 is a diagram showing the compressive stress in the quartz plate 1 and the thermal stress in the wiring layers 71, 72, 73 in the dummy chip portion of the semiconductor chip portion shown in FIG. As shown in FIG. 11 and FIG. 12, when the multilayer wiring structure 7 is formed on the SOQ wafer 3 by using the method for manufacturing the semiconductor device according to the first embodiment, the SOQ wafer is increased as the temperature rises. 3 receives a horizontal outward pulling force F3 from the multilayer wiring structure 7. However, in the multilayer wiring structure 7, the upper layer 712 of the wiring layer 71 is entirely composed of a metal layer, but the upper layer 722 of the wiring layer 73 thereon is a process for forming a wiring layer on the product chip portion. It has a metal wiring 722a formed on the dummy chip portion by the same formation process as that (using photolithography technology and CVD method). As described above, in the multilayer wiring structure 7 of the first embodiment, the metal layer extending over the entire area of the dummy chip portion as shown in FIG. 9 (second comparative example) is a layer near the SOQ wafer 3 (for example, In the closest layer and the second closest layer, a plurality of layers are not overlapped. With such a configuration, the horizontal outward pulling force F3 that is likely to be applied to the SOQ wafer 3 when a plurality of metal layers having a large area are arranged in an overlapping manner is prevented.

  Further, in the multilayer wiring structure 7 of the first embodiment, the through metal wiring (metal) is connected to the insulating film 711 of the wiring layer 71 closest to the SOQ wafer 3 and the insulating film 721 of the wiring layer 72 closest to the SOQ wafer 3. Does not have a plug). For this reason, in the multilayer wiring structure 7 of the first embodiment, the SOQ wafer 3 receives from the multilayer wiring structure 4 outside the horizontal direction due to the overlap of the through metal wiring as shown in FIG. 8 (first comparative example). The pulling force F3 in the direction can be prevented from concentrating directly below the through metal wiring 411a. In FIG. 11, both the insulating film 711 of the wiring layer 71 closest to the SOQ wafer 3 and the insulating film 721 of the wiring layer 72 closest to the SOQ wafer 3 do not have through metal wiring (metal plug). Although the case is exemplified, the insulating film 711 does not include the through metal wiring and the insulating film 721 includes the through metal wiring. Alternatively, the insulating film 711 includes the through metal wiring. Even in the case where the 721 includes a through metal wiring, the SOQ wafer 3 may prevent the horizontal outward pulling force F3 received from the multilayer wiring structure 4 from being concentrated to a certain extent directly below the through metal wiring 411a. it can.

  For the above reasons, if the semiconductor device manufacturing method according to the first embodiment is used, cracks are unlikely to occur in the SOQ wafer 3, and the quality and manufacturing yield of the semiconductor device using the separated semiconductor chips can be reduced. Can be improved.

  FIG. 13 is a longitudinal sectional view schematically showing a dummy chip portion of the semiconductor chip portions manufactured by the modification of the method for manufacturing the semiconductor device according to the first embodiment. In FIG. 13, the same or corresponding elements as those shown in FIG. In the method of manufacturing the semiconductor device shown in FIG. 13, the multilayer wiring structure 7a forms the third wiring layer 73a from the SOQ wafer 3 in the same order as the wiring layers (from the SOQ wafer 3 on the product chip portion). The wiring layer 74 is formed on the wiring layer 73a by the same formation process as that of the process of forming the wiring pattern) (using a photolithography technique and a CVD method). In the example of FIG. 13, the wiring layer 73 a has a lower layer 731 and an upper layer 732. The lower layer 731 has an insulating film and a through metal wiring, and the upper layer 732 has an insulating film and a metal wiring. The wiring layer 74 has a lower layer 741. The lower layer 741 has an insulating film and a through metal wiring.

  In the example of FIG. 13, the third and subsequent wiring layers from the SOQ wafer 3 are provided with through metal wiring (metal plugs). However, since the through metal wiring is separated from the SOQ wafer 3, the through metal wiring is overlapped. Due to the thermal stress of the configuration described above, the horizontal outward pulling force that the SOQ wafer 3 receives from the multilayer wiring structure 4 is small. Therefore, in the case of FIG. 13, as in the case of FIG. 11, cracks are hardly generated in the SOQ wafer 3.

  FIG. 14 is a longitudinal sectional view schematically showing a dummy chip portion of the semiconductor chip portions manufactured by another modification of the method for manufacturing the semiconductor device according to the first embodiment. In FIG. 14, the same reference numerals are given to the same or corresponding components as those shown in FIG. In the method for manufacturing the semiconductor device shown in FIG. 14, the multilayer wiring structure 7b forms a fourth wiring layer 74a from the SOQ wafer 3 on the wiring layer on the product chip part (in the product chip part and the dummy chip part, the wiring The same formation process is used as in the formation process (using photolithography technology and CVD method), and the wiring layer 75 is formed on the wiring layer 74a. In the example of FIG. 14, the wiring layer 74 a has a lower layer 741 and an upper layer 742. The lower layer 741 has an insulating film and a through metal wiring, and the upper layer 742 has an insulating film and a metal wiring. The wiring layer 75 has a lower layer 751. The lower layer 751 has an insulating film and a through metal wiring.

  In the example of FIG. 14, the third and subsequent wiring layers from the SOQ wafer 3 are provided with through metal wiring (metal plugs). However, since the through metal wiring is separated from the SOQ wafer 3, the through metal wiring overlaps. Due to the thermal stress of the configuration described above, the horizontal outward pulling force that the SOQ wafer 3 receives from the multilayer wiring structure 4 is small. Therefore, in the case of FIG. 14 as well, cracks are unlikely to occur in the SOQ wafer 3 as in the case of FIGS.

<< 3 >> Second Embodiment FIG. 15 is a longitudinal sectional view schematically showing a dummy chip portion of semiconductor chip portions manufactured by a method for manufacturing a semiconductor device according to a second embodiment. As shown in FIG. 15, in the method for manufacturing a semiconductor device according to the second embodiment, a semiconductor chip is attached to a SOQ wafer 3 which is a bonded wafer manufactured by bonding a Si layer 2 to a quartz plate 1. A plurality of semiconductor chip portions (rectangular regions 126 and 127 in FIG. 7) are formed in a chip formation region (region 125 in FIG. 7) by forming a circuit element (or an integrated circuit) or the like responsible for the essential functions of Then, a multilayer wiring structure 8 is formed thereon. The plurality of semiconductor chip portions include a product chip portion (rectangular region 127 in FIG. 7) used as a semiconductor chip after separation, and a dummy chip portion (rectangular cross-hatching region 126 in FIG. 7) that is not used. including.

  In forming the multilayer wiring structure 8, first, a dummy chip is formed on the Si layer 2 of the SOQ wafer 3 by the same formation process as the wiring layer forming process (using photolithography technology, CVD method, etc.) on the product chip portion. A wiring layer 81 on the part is formed. The wiring layer 81 includes a lower layer 811. The lower layer 811 includes an insulating film 811b and a through metal wiring 811a. Further, the position, shape, and number of the through metal wiring 811a are not limited to the illustrated example, and various positions, various shapes, and various numbers can be adopted according to the wiring pattern of the product chip portion. . The upper layer 812 has an insulating film 812b and a metal wiring 812a. The shape of the metal wiring 812a is not limited to the illustrated example, and has the same shape as the wiring pattern of the product chip portion.

  Next, the wiring layer 82 on the dummy chip part is formed on the wiring layer 81 on the dummy chip part. The wiring layer 82 has a lower layer 821 and an upper layer 822. The lower layer 821 has an insulating film 821b and a through metal wiring 821a. Further, the position, shape, and number of the through metal wiring 821a are not limited to the illustrated example, and various positions, various shapes, and various numbers can be adopted according to the wiring pattern of the product chip portion. . The upper layer 822 on the dummy chip portion is a metal layer whose entire region (entire surface) is formed of a metal material.

  Next, the wiring layer 83 on the dummy chip part is formed on the wiring layer 82 on the dummy chip part. The wiring layer 83 has a lower layer 831. The lower layer 831 is made of an insulating film and does not include a through metal wiring.

  FIG. 16 is a diagram showing compressive stress in the quartz plate 1 and thermal stress in the wiring layers 81, 82, 83 in the dummy chip portion of the semiconductor chip portion shown in FIG. 15. As shown in FIGS. 15 and 16, when the multilayer wiring structure 8 is formed on the SOQ wafer 3 using the manufacturing method according to the second embodiment, as the temperature rises, the SOQ wafer 3 A horizontal outward pulling force F4 is received from the multilayer wiring structure 8. However, in the multilayer wiring structure 8, the upper layer 812 of the wiring layer 81 is not the entire metal layer, but by the same formation process as the wiring layer forming process (using photolithography technology, CVD method, etc.) on the product chip portion, Metal wiring 812a having a pattern formed on the dummy chip portion is provided. Thus, in the multilayer wiring structure 7 of the second embodiment, a large-area metal layer extending over the entire area (entire surface) of the dummy chip portion as shown in FIG. 9 (second comparative example) is formed on the SOQ wafer 3. In the adjacent layer, a plurality of layers are not overlapped. For this reason, a large horizontal outward pulling force applied to the SOQ wafer 3 when a plurality of metal layers having a large area are arranged in an overlapping manner can be suppressed.

  Further, in the multilayer wiring structure 8 of the second embodiment, the insulating film 831 of the wiring layer 83 third closest to the SOQ wafer 3 is not provided with a through metal wiring (metal plug). Therefore, in the multilayer wiring structure 8 of the second embodiment, the SOQ wafer 3 receives from the multilayer wiring structure 8 outside the horizontal direction due to the overlap of the through metal wirings as shown in FIG. 8 (first comparative example). The pulling force in the direction can be prevented from being concentrated directly below the through metal wiring 811a. In FIG. 15, both of the insulating film 811 of the wiring layer 81 closest to the SOQ wafer 3 and the insulating film 821 of the wiring layer 82 closest to the SOQ wafer 3 are provided with through metal wiring (metal plug). Although the case is illustrated, the insulating film 811 does not include the through metal wiring and the insulating film 821 includes the through metal wiring. Alternatively, the insulating film 811 includes the through metal wiring. Even when the 821 includes the through metal wiring, the horizontal outward pulling force that the SOQ wafer 3 receives from the multilayer wiring structure 4 can be prevented from being concentrated directly below the through metal wiring 411a.

  Further, in the multilayer wiring structure 8 shown in FIG. 15, a plurality of wiring layers 81, 82, 83 stacked on the dummy chip portion are connected to the wiring layer 81 having the same shape as the wiring layer on the product chip portion. And a wiring layer 82 having a shape different from that of the layer 81 (the entire surface is a metal layer). As described above, when the wiring layer 81 and the wiring layer 82 stacked on the dummy chip portion have different shapes (wiring patterns), the thermal stresses of the wiring layer 81 and the wiring layer 82 are obtained. Are difficult to concentrate on the same position of the SOQ wafer 3.

  For the above reasons, if the method for manufacturing a semiconductor device according to the second embodiment is used, cracks are unlikely to occur in the SOQ wafer 3, and the quality and manufacturing yield of the semiconductor device using the separated semiconductor chips can be reduced. Can be improved.

  FIG. 17 is a longitudinal sectional view schematically showing a dummy chip portion of the semiconductor chip portions manufactured by the modification of the method for manufacturing the semiconductor device according to the second embodiment. In FIG. 17, the same or corresponding elements as those shown in FIG. In the method for manufacturing the semiconductor device shown in FIG. 17, the multilayer wiring structure 8a includes a third wiring layer 83a from the SOQ wafer 3 which is composed of an insulating film 831 having no through metal wiring and an entire surface metal layer 832. On the layer 83a, a wiring layer 84 made of an insulating film 841 and having no through metal wiring is formed.

  In the example of FIG. 17, the third and subsequent wiring layers from the SOQ wafer 3 include the entire surface metal layer 832 as an upper layer, but are separated from the SOQ wafer 3, so that the entire surface metal layer overlaps with the upper layer 822. 832), the horizontal outward pulling force that the SOQ wafer 3 receives from the multilayer wiring structure 4 is small. Accordingly, in the case of FIG. 17 as well, cracks are unlikely to occur in the SOQ wafer 3 as in the case of FIG.

  FIG. 18 is a vertical cross-sectional view schematically showing a dummy chip portion of semiconductor chip portions manufactured by another modification of the method for manufacturing a semiconductor device according to the second embodiment. In FIG. 18, the same or corresponding elements as those shown in FIG. The semiconductor device manufacturing method shown in FIG. 18 differs from the example of FIG. 15 in that the lower layer 821a of the second wiring layer 82a from the SOQ wafer 3 in the multilayer wiring structure 8b has no through metal wiring. .

  In the example of FIG. 18, since the through metal wiring (metal plug) is not provided in the second and subsequent wiring layers from the SOQ wafer 3, the SOQ wafer 3 receives from the multilayer wiring structure 4 directly below the through metal wiring 811a. The outward pulling force is small. Therefore, in the case of FIG. 18 as well, as in the case of FIG. 15, cracks are unlikely to occur in the SOQ wafer 3.

<< 4 >> Modified Example FIG. 19 is a plan view schematically showing another example of the arrangement of product chip parts and dummy chip parts which are semiconductor chips formed on the SOQ wafer in the first and second embodiments. is there. In FIG. 19, the same reference numerals are given to the same or corresponding components as those in FIG. In FIG. 7, a semiconductor chip portion having a portion in contact with the outer periphery of a chip formation region 125 including a plurality of semiconductor chip portions (one side, two sides, or a corner portion of the semiconductor chip portion is in contact with the chip formation region 125. Is a dummy chip portion (cross-hatched portion). However, as shown in FIG. 19, this is a semiconductor chip portion (one or two sides of the semiconductor chip portion are in contact with the chip formation region 125) having sides that coincide with the outer periphery of the chip formation region 125. In this way, the defective product generation rate due to the influence of cracks may increase, but the product yield can be improved.

  FIG. 20 is a plan view schematically showing still another example of the arrangement of the product chip portion and the dummy chip portion of the SOQ wafer in the first and second embodiments. 20, the same reference numerals are given to the same or corresponding components as those in FIG. In FIG. 7, a semiconductor chip portion (a portion where two sides of the semiconductor chip portion are in contact with the chip formation region 125) having a portion in contact with the outer periphery of the chip formation region 125 including a plurality of semiconductor chip portions is replaced with a dummy chip portion (cross (Hatched part). As shown in FIG. 20, the semiconductor chip portion has two sides that coincide with the outer periphery of the chip formation region 125 (one or two sides of the semiconductor chip portion are in contact with the chip formation region 125). In this way, the defective product generation rate due to the influence of cracks may increase, but the product yield can be improved.

  In the above description, the case where a quartz plate is used as the insulating substrate 1 has been described. However, the insulating substrate 1 may be a substrate made of another material such as a quartz plate.

  Further, the arrangement of the semiconductor chip part and the arrangement of the dummy chip part may have other configurations. The semiconductor chip part that overlaps at least part of the distance from the outer periphery of the wafer within a predetermined value, or the semiconductor chip including the entire area The part may be a dummy chip part.

1,121 quartz plate (insulating substrate), 2,122 silicon layer,
3 SOQ wafer (semiconductor wafer),
6, 7, 7a, 7b, 8, 8a, 8b multilayer wiring structure,
61, 62, 63, 71, 72, 73, 73a, 74, 74a, 75 wiring layers,
125 chip formation region, 126 product chip part, 127 dummy chip part,
711, 721, 731, 741, 751 lower layer,
712, 722, 732, 742, 752 upper layer,
731a, 812a, 821a Through metal wiring (metal plug),
722a, 812a metal wiring (manufactured by the same process as the product chip part),
712, 822, 832 Metal layer (formed on the entire surface of the dummy chip portion).

Claims (17)

Forming a plurality of semiconductor chip portions on a bonded wafer manufactured by bonding a silicon layer to an insulating substrate;
The wiring layer is formed on the plurality of semiconductor chip portions by performing a process of forming a wiring layer having a lower layer including an insulating film and an upper layer including a metal wiring provided on the lower layer a plurality of times. Forming a multi-layered multilayer wiring structure,
The plurality of semiconductor chip parts include a product chip part used as a semiconductor chip after singulation, and a dummy chip part not used,
A plurality of the wiring layers stacked on the dummy chip portion include a first wiring layer having the same shape as the wiring layer on the product chip portion, and a second wiring having a shape different from that of the first wiring layer. Including layers,
Wherein the lower layer in any of a plurality superposed said wiring layer dummy chip part on the Ri insulating film der that no through metal wiring,
The method for manufacturing a semiconductor device, wherein the insulating substrate includes a substrate mainly composed of either quartz or quartz . A step of forming a plurality of semiconductor chip portions on a bonded wafer produced by bonding a silicon layer to an insulating substrate and generating compressive stress in the insulating substrate;
The wiring layer is formed on the plurality of semiconductor chip portions by performing a process of forming a wiring layer having a lower layer including an insulating film and an upper layer including a metal wiring provided on the lower layer a plurality of times. Forming a multi-layered multilayer wiring structure; and
Have
The plurality of semiconductor chip parts include a product chip part used as a semiconductor chip after singulation, and a dummy chip part not used,
A plurality of the wiring layers stacked on the dummy chip portion include a first wiring layer having the same shape as the wiring layer on the product chip portion, and a second wiring having a shape different from that of the first wiring layer. Including layers,
The lower layer in any one of the wiring layers stacked on the dummy chip portion is an insulating film having no through metal wiring.
A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 2, wherein a thermal expansion coefficient of the insulating substrate is different from a thermal expansion coefficient of the silicon layer. The first wiring layer on the dummy chip portion is a wiring layer that is second closest to the bonded wafer;
The method for manufacturing a semiconductor device according to any one of claims 1 to 3 , wherein the second wiring layer on the dummy chip portion is a wiring layer closest to the bonded wafer. The upper layer of the second wiring layer in the dummy chip unit on the any one of claims 1 to 4, characterized in that said a metal layer formed to cover the entire surface of the dummy chip unit The manufacturing method of the semiconductor device as described in 2. The first wiring layer in the dummy chip part on the claims 1-5, characterized in that it is formed by the same forming Puroseru the first wiring layer forming process in the product chip part on the use of photolithography The method for manufacturing a semiconductor device according to any one of the above. Said through lower layer is the insulating film that does not have a metal wiring, a semiconductor according to any one of claims 1 to 6, characterized in that it comprises a bottom layer of the wiring layer closest to the bonded wafer Device manufacturing method. It said through lower layer is the insulating film that does not have a metal wire, according to any one of claims 1 to 7, characterized in that it comprises a lower layer of the wiring layer second closest to the bonded wafer Semiconductor device manufacturing method. The first wiring layer on the dummy chip portion is a wiring layer closest to the bonded wafer,
The second wiring layer in the dummy chip part on the method of manufacturing a semiconductor device according to any one of claims 1 to 3, characterized in that the wiring layer second closest to the bonded wafer . 10. The upper layer of the second wiring layer on the dummy chip portion is a metal layer formed so as to cover the entire surface of the dummy chip portion . A manufacturing method of a semiconductor device given in any 1 paragraph . The first wiring layer in the dummy chip part on the claim 1, 2, characterized in that it is formed by the same forming Puroseru the first forming process of the wiring layer in the product chip part on the use of photolithography 11. A method for manufacturing a semiconductor device according to any one of 3, 9, and 10 . Said through lower layer is the insulating film that does not have a metal wire, according to claim 1, characterized in that it comprises a lower layer of the wiring layer closer to the third position from the bonded wafer, 2,3,9,10 and, 11. A method for manufacturing a semiconductor device according to any one of 11 above. Said through lower layer is the insulating film that does not have a metal wire, according to claim 1, characterized in that it comprises a lower layer of the wiring layer closer to the second from the bonded wafer, 2,3,9,10,11 And a manufacturing method of the semiconductor device according to any one of 12 and 12 . The plurality of wiring layers stacked are three or more wiring layers,
The upper layer of the third and subsequent wiring layers from the bonded wafer side is a metal layer formed so as to cover the entire surface of the dummy chip portion . 14. The method for manufacturing a semiconductor device according to any one of 10, 11, 12, and 13 . The dummy chip portion semiconductor device according to any one of claims 1, characterized in that the semiconductor chip section having a portion in contact with the outer periphery of the chip forming region to 14 including a plurality of semiconductor chips portion Manufacturing method. The dummy chip portion semiconductor of any one of claims 1 to 14, characterized in that the semiconductor chip section having sides matching the outer periphery of the chip formation region including a plurality of semiconductor chips portion Device manufacturing method. The dummy chip portion according to any one of claims 1 to 14, characterized in that the edges to match the periphery of a chip forming area including a plurality of semiconductor chips portion is a semiconductor chip section having two Semiconductor device manufacturing method.

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