JP5835155B2 - Power supply circuit and drive circuit - Google Patents

Description

  The present invention relates to a power supply circuit that generates power by being supplied with an external power supply, and a drive circuit that drives a drive target by being supplied with power from the power supply circuit.

  When this type of power supply circuit is supplied with external power, it is easy to output an inrush current at the power-on timing when the fluctuation of the external power supply voltage is large. For example, a power supply target circuit that operates by receiving power supplied from this type of power supply circuit may be sensitive to the inrush current.

  Consider a case where the power supply target circuit is, for example, a drive circuit that drives a control terminal of a transistor. The drive circuit may have a large parasitic capacitance between the power supply terminal and the output terminal. If the start-up of the power supply for supplying power to the drive circuit is fast, for example, the output of the drive circuit may fluctuate through the parasitic capacitance described above. For example, if the control terminal of the switching transistor is connected to the output terminal of the drive circuit as a drive target, a coupling action due to parasitic capacitance occurs at the time of power activation, and the control terminal voltage of the switching transistor fluctuates and malfunctions. .

  In order to solve this problem, it is conceivable to insert an RC filter or the like at the output terminal of the power supply reference voltage. A configuration in which a capacitive element is provided between the common gate and the output drive circuit is described in Patent Document 1 and the like. However, for example, if the rising slew rate of the power supply reference voltage is increased, the followability to fluctuations in the power supply reference voltage is deteriorated.

JP-A-60-14115

Therefore, it is necessary to prevent malfunction of the power supply target circuit even if the power supply target circuit is sensitive to the inrush current when the power is turned on.
An object of the present invention is to provide a power supply circuit capable of preventing malfunction of a power supply target circuit even when the power supply target circuit is sensitive to an inrush current at power-on at the time of power activation, and the power supply circuit It is an object of the present invention to provide a drive circuit that can output a drive signal to an object to be driven.

  According to the first aspect of the present invention, the following transient phenomenon occurs when the power is turned on. When the power is turned on, the first energization circuit (7) energizes the control terminal of the first transistor (Tr1 or Tr1a). When the power supply reference voltage (V7) of the first energization circuit (7) changes near a predetermined voltage, the capacitor circuit (C2) connected to the control terminal of the first transistor (Tr1 or Tr1a) It is considered that the capacitance formed by adding the capacitance to the parasitic capacitance further increases as the mirror capacitance. At this time, when a current is passed through the capacitor circuit (C2) having an increased apparent capacitance value due to the Miller effect, the potential of the control terminal of the first transistor is stabilized near a predetermined potential.

  During this time, the fluctuation of the power supply reference voltage applied to the control terminal of the first transistor (Tr1 or Tr1a) is suppressed, and accordingly, the fluctuation of the output to the power supply target circuit by the first transistor can be suppressed. As a result, even when the power supply target circuit is sensitive to the inrush current when the power is turned on, the output fluctuation of the first transistor to the power supply target circuit is suppressed. Malfunctions can be prevented.

  According to the third aspect of the present invention, the high impedance circuit cuts off the current energization path other than energizing the capacitor circuit when the power is turned on from the output energization path of the first energization circuit in the steady state. In operation, a steady DC current path is not generated. For this reason, in a steady state, the power supply reference voltage of the first energization circuit is stably output directly to the control terminal of the first transistor. As a result, the power supply reference voltage value can be easily designed, and the degree of design freedom can be improved.

According to the fifth aspect of the present invention, the control terminal of the second transistor can be protected using the Zener diode.
According to the sixth aspect of the present invention, since the power supply reference voltage side of the first energization circuit is not energized to the gate protection circuit and the potential regulating circuit side, the value of the power supply reference voltage of the first energization circuit can be designed independently. The degree of freedom in design can be improved.

According to the seventh aspect of the present invention, since at least a part of the high impedance circuit is configured in front of the control terminal of the second transistor, the energization path for energizing the control terminal of the second transistor can be cut off. The control terminal of the transistor can be protected.

According to the eighth aspect of the present invention, since the on-threshold reference potential by the potential defining circuit is level-shifted according to the power supply reference voltage and the protection voltage, even if the first energization circuit energizes the power supply reference voltage, the transient operation The energization path flowing into the gate protection circuit side in the subsequent normal operation can be cut off. As a result, the value of the power supply reference voltage can be designed independently, and the degree of design freedom can be improved.

In particular, when power is supplied to a drive circuit unit having a parasitic capacitance between the power supply terminal and the output terminal, current is supplied to the control terminal of the switching transistor to be driven through the conventional parasitic capacitance. According to the invention of claim 9, thereby preventing malfunction of the switching transistor by applying any one of the claims 1-8 above.

1 is an electrical configuration diagram schematically showing a power supply circuit and a drive circuit according to a first embodiment of the present invention. Detailed circuit configuration example of output stage of drive circuit Configuration example of constant voltage generation circuit Configuration example of power supply reference voltage generation circuit Timing chart schematically showing signal changes in each part when power is turned on FIG. 5 equivalent diagram showing a comparative example FIG. 1 equivalent view showing a second embodiment of the present invention Figure equivalent to FIG. FIG. 1 equivalent view showing the third embodiment of the present invention (No. 1) FIG. 1 equivalent view showing the third embodiment of the present invention (No. 2) FIG. 1 equivalent view showing a fourth embodiment of the present invention FIG. 1 equivalent view showing a fifth embodiment of the present invention

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a configuration example of a power supply circuit and a drive circuit in the semiconductor integrated circuit device 1. A DC power supply voltage (battery power supply voltage) V1 is supplied to the DC power supply input terminal T1. The ground terminal T4 is fixed to the ground potential GND.

  A power supply circuit (starting circuit) 2 is configured in the semiconductor integrated circuit device 1. The power supply circuit 2 is configured by connecting an N-channel MOS transistor (hereinafter referred to as a transistor) Tr1 to the output in the form of a source follower. The transistor Tr1 has a drain supplied with a positive DC power supply voltage V1, and a source connected to the DC power supply output terminal T2. The transistor Tr1 outputs a DC power supply voltage Vout to the outside through a DC power supply output terminal T2. A capacitor C1 is connected to the DC power output terminal T2 outside the semiconductor integrated circuit device 1.

  A drive circuit unit 3 is configured in the semiconductor integrated circuit device 1. The positive power supply terminal of the drive circuit unit 3 is connected to the DC power supply output terminal T2, and the negative power supply terminal is supplied with the ground potential GND. Therefore, the drive circuit unit 3 is supplied with the DC power supply voltage Vout through the DC power supply output terminal T2.

  The drive circuit unit 3 outputs a drive control signal (for example, PWM drive voltage) to the gate (control terminal) of the external transistor Tr3 through the drive output terminal T3 using the supplied DC power supply voltage Vout. Here, the transistor Tr3 is a voltage-driven transistor such as an N-channel MOS transistor or an IGBT.

  The drive circuit unit 3 includes, for example, a pre-driver circuit and an output stage circuit. FIG. 2 shows a detailed example of the output stage circuit of the drive circuit unit 3. As shown in FIG. 2, the drive circuit unit 3 includes an on / off output circuit 4 having an inverter configuration at an output stage. This on / off output circuit 4 is configured by connecting a P-channel type MOS transistor Tr5 on the upper side and an N-channel type MOS transistor Tr6 on the lower side, and operates by inputting the DC power supply voltage Vout of the DC power supply output terminal T2. Parasitic capacitances Ca1 to Ca3 are formed in the transistors Tr5 and Tr6 of the on / off output circuit 4. That is, when these parasitic capacitances Ca1 to Ca3 are parasitic, a total parasitic capacitance Ca is generated between the power input terminal and the output terminal as shown in FIG.

  Although not shown in FIG. 1, the drive circuit unit 3 includes various circuits before the on / off output circuit 4. The drive circuit unit 3 outputs an on / off drive signal corresponding to the output of the on / off output circuit 4 to the gate of the transistor Tr3 through the drive output terminal T3. A resistor R1 is connected between the gate and source of the transistor Tr3.

  The transistor Tr3 is configured by using, for example, an N-channel MOS transistor, and is configured by connecting a circuit (for example, inductive load: not shown) for supplying current on and off to the high side. When an ON drive signal is given to the transistor Tr3, the high side connection circuit is energized.

  Returning to FIG. 1, the power supply circuit 2 is configured by connecting a gate voltage adjusting circuit 5 to a control terminal (gate) of the transistor Tr1. The gate voltage adjusting circuit 5 includes a DC current source (corresponding to a transient potential starting circuit) I1, an N-channel MOS transistor (hereinafter referred to as transistor) Tr4, and a constant voltage generator between a supply terminal of the power supply voltage V1 and the ground GND. The circuit 6 is connected in series. As the transistor Tr4, for example, a replica transistor having the same shape and different size as the transistor Tr1 is used. The threshold voltage Vt1 of the transistor Tr1 and the threshold voltage Vt4 of the transistor Tr4 are set to substantially the same voltage, which makes it easy to design a circuit using the transistors Tr1 and Tr4.

  A capacitor circuit C2 is formed between the drain and gate of the transistor Tr4. This capacity circuit C2 is a capacity that looks like a mirror capacity when the power supply is turned on, especially when a transient change occurs in each node. For example, the capacitor circuit C2 is configured by intentionally connecting a capacitor in parallel in the semiconductor integrated circuit device 1 in addition to the parasitic capacitance parasitic on the normal transistor Tr4, thereby increasing the capacitance. Constructed (for example, several tens to several hundreds pF). In addition, the DC power supply reference voltage V7 is applied to the gate of the transistor Tr4 through the resistor R2 from the power supply reference voltage generation circuit 7 in a steady state.

  FIG. 3 shows a configuration example of the constant voltage generation circuit 6. The constant voltage generation circuit 6 as a potential regulating circuit is configured by combining, for example, a diode D3, a forward connection Zener diode D4, a reverse connection Zener diode D5, and the like, and generates a positive constant voltage when the power is turned on to generate a transistor Tr4. Apply to the source. The constant voltage generation circuit 6 raises the source potential of the transistor Tr4 in comparison with the source potential of the transistor Tr1 particularly when the power is turned on. The constant voltage generation circuit 6 may use a diode-connected MOS transistor instead of these configurations, and is configured by combining this diode-connected MOS transistor with one or more of the above-described diodes D3, D4, and D5. May be.

  FIG. 4 shows a configuration example of the power supply reference voltage generation circuit 7. The power supply reference voltage generation circuit 7 includes all or part of the current source I2, the resistor R3, the diode-connected transistor Tr7, the diode D6, the reverse connection Zener diode D7, and the like between the supply terminal of the power supply voltage V1 and the ground GND. This is a circuit that generates a power supply reference voltage V7 as a DC voltage. The power supply reference voltage generation circuit 7 may have the same configuration as the constant voltage generation circuit 6 described above. However, the power supply reference voltage V7 generated by the power supply reference voltage generation circuit 7 is set larger than the generated DC voltage V6 of the constant voltage generation circuit 6.

  The operation of the above configuration will be described with reference to FIG. The threshold voltages of the transistors Tr1 and Tr4 are Vt1 and Vt4, respectively. The common connection gate of the transistors Tr1 and Tr4 is a node N1, the drain of the transistor Tr4 is a node N2, the source of the transistor Tr1 is a node N3, and the gate of the transistor Tr3 is a node N4.

  As shown in FIG. 5, when the power is turned on, the power supply voltage V1 rises instantaneously and the power supply reference voltage generation circuit 7 outputs the power supply reference voltage V7, so that the gate potentials (nodes) of the transistors Tr1 and Tr4 N1 potential) is increased instantaneously. When the potential of the node N1 becomes equal to or higher than the threshold voltage Vt1 of the transistor Tr1, the transistor Tr1 starts to be turned on. This is because the source of the transistor Tr1 is connected to the capacitor C1, the parasitic capacitance Ca of the on / off output circuit 4 of the drive circuit unit 3, and the resistor R1, and almost when a voltage is applied to the gate of the transistor Tr1. The output voltage Vout is increased so that the gain becomes 1.

  Even if the transistor Tr1 is energized, the transistor Tr4 remains off. The transistor Tr4 is kept off because the constant voltage generation circuit 6 raises the source potential of the transistor Tr4 compared to the source potential of the transistor Tr1.

  Further, at the time of power-on, the capacitor circuit C2 is not charged immediately before the power supply voltage V1 changes transiently. For this reason, the capacitor circuit C2 starts to be charged immediately after the power is turned on. At this time, since the power supply voltage V1 is set higher than the power supply reference voltage V7, an inrush current is passed between the drain and gate of the transistor Tr4 according to the action of the current source I1, and the drain potential of the transistor Tr4 is To rise.

  However, after that, the gate potentials of the transistors Tr1 and Tr4 further increase, and when the potential of the node N1 reaches the threshold voltage Vt4 + DC voltage V6 at the timing (A) in FIG. 5, the increase in the gate potential is suppressed. This is because a mirror effect is caused in the transistor Tr4. When the gate potential of the transistor Tr4 exceeds the threshold voltage Vt4 + the generation voltage V6 of the constant voltage generation circuit 6, the transistor Tr4 is turned on and the drain current of the transistor Tr4 increases.

  Assuming that the gain of the transistor Tr4 is −Av, the capacitance circuit C2 between the drain and gate is multiplied by (1 + Av) according to the Miller effect. Therefore, the capacitance value of the capacitance circuit C2 between the drain and gate of the transistor Tr4 appears larger than the actual capacitance actually formed between the drain and gate. When the gate potential of the transistor Tr4 rises to the threshold voltage Vt4 + DC voltage V6 with respect to the ground potential GND and enters the gate voltage rise suppression period (referred to as the mirror period Y1) by the action of the capacity circuit C2, the capacity circuit C2 is on the node N1 side. To the node N2 side.

  Then, since the gate potentials of the transistors Tr1 and Tr4 gradually increase, the on-resistance of the transistor Tr4 gradually decreases, and the drain current of the transistor Tr4 increases. Thereby, in the mirror section Y1, as the gate potential of the transistor Tr4 (potential of the node N1) increases, the drain potential of the transistor Tr4 (potential of the node N2) decreases.

  Further, during this mirror section Y1, the energized current is discharged to the resistor R1, and therefore the potential at the terminal T3 (the potential at the node N4) gradually decreases. As a result, an increase in the gate potential Vg of the transistor Tr3 can be suppressed in the mirror section Y1.

  When the transistor Tr4 is in an on-saturated state, the drain potential of the transistor Tr4 is prevented from decreasing (see timing (B) in FIG. 5). When the drain current of the transistor Tr4 is almost saturated, the drain voltage of the transistor Tr4 is stabilized, the influence of the mirror effect is reduced, and the mirror section Y1 is almost ended. Thereafter, since the power supply reference voltage generation circuit 7 charges the capacitor circuit C2 from the gate side to the drain side of the transistor Tr4, the gate potential of the transistor Tr4 is changed from the threshold voltage Vt4 + voltage V6 to the power supply reference voltage of the power supply reference voltage generation circuit 7. It starts to rise towards V7. Since this upward gradient is not affected by the mirror effect of the capacitive circuit C2, the upward gradient is larger than that in the mirror section Y1.

  When the gate potential of the transistor Tr4 rises, the source potential of the transistor Tr1 (potential of the node N3) also rises. Thus, in response to the power supply reference voltage V7 being applied to the gate of the transistor Tr1, the transistor Tr1 outputs a source follower, and a normal power supply voltage (≈V1) is applied to the drive circuit unit 3.

  At this time, the potential of the terminal T3 (the potential of the node N4) also rises due to the influence of the coupling of the parasitic capacitance Ca (see the timing in FIG. 5C). However, as shown in FIG. 5, when the source potential of the transistor Tr1 reaches the inverter operation lower limit voltage Vsmin of the on / off output circuit 4, the gate potential Vg of the transistor Tr3 is adjusted so as not to reach the threshold voltage Vt3. If this is the case, the transistor Tr3 will not be turned on (false point).

  FIG. 6 shows a comparative example of FIG. In this comparative example, a timing chart of each node voltage when a circuit without the gate voltage adjusting circuit 5 is used is shown. When the power supply voltage V1 rises, the power supply reference voltage V7 also rises along with this, but the source potential of the transistor Tr1 of the source follower configuration rises accordingly. Until the source potential of the transistor Tr1 reaches the operation lower limit voltage of the inverter (≈Vt5 / Vt6, where Vt5 and Vt6 are the threshold voltages of the transistors Tr5 and Tr6, respectively), the gate line of the transistor Tr3 becomes floating, and the on / off output circuit 4 The gate potential Vg of the transistor Tr3 rises due to the coupling of the parasitic capacitance Ca between the power supply input terminal and the output terminal.

  Therefore, as also employed in the present embodiment, although the rise of the gate voltage can be suppressed by inserting the resistor R1 between the gate and the source of the transistor Tr3, when the action of raising the gate voltage is large according to the capacitive coupling, It is necessary to reduce the resistance value of the resistor R1. At this time, since the drive circuit unit 3 supplies current to the resistor R1, the current consumption of the drive circuit unit 3 may increase.

  Also, if the output logic of the preceding circuit of the on / off output circuit 4 is unstable when the power is turned on, the source potential of the transistor Tr1 is the inverter operation of the on / off output circuit 4 in the circuit without the gate voltage adjustment circuit 5. When the lower limit voltage Vsmin is reached, the gate potential of the transistor Tr3 may exceed the threshold voltage Vt3.

  In the present embodiment, as shown in FIG. 5, at the timing when the source potential of the transistor Tr1 reaches the inverter operation lower limit voltage Vsmin of the on / off output circuit 4, the gate potential of the transistor Tr3 is adjusted so as not to exceed the threshold voltage Vt3. Therefore, even if the logic of the preceding circuit of the on / off output circuit 4 is unstable at the time of turning on the power, the increase in the potential of the node N4 can be suppressed and the transistor Tr3 can be prevented from being turned on accidentally. it can. Since it is not necessary to reduce the resistance value of the resistor R1, the current consumption of the drive circuit unit 3 can be suppressed.

  In the present embodiment, the capacitance circuit C2 serving as the drain-gate capacitance Cgd of the transistor Tr4 is set to a capacitance value larger than the parasitic capacitance of the normal transistor Tr1 or Tr4, and the operation of the capacitance circuit C2 when the power is turned on is amplified. C2 is operated as a mirror capacitor. As a result, an increase in the gate potential of the transistor Tr1 can be suppressed, and thus, malfunction of the drive circuit unit 3 can be prevented and the transistor Tr3 can be prevented from being turned on by mistake.

In addition, the area required in the semiconductor integrated circuit device 1 can be reduced as compared with the case where the voltage fluctuation delay circuit of the power supply reference voltage generation circuit 7 is configured using a general RC filter circuit.
In addition, after the power supply voltage V1 is stabilized after the power is turned on, when the power supply reference voltage V7 fluctuates relatively slowly as compared to when the power is turned on, the fluctuation of the power supply reference voltage V7 is blocked by the capacitor circuit C2. Accordingly, since the capacitance circuit C2 is a circuit that cuts off the energization path other than the path to the gate of the transistor Tr1 in a steady state, the capacitance circuit C2 constitutes the high impedance circuit 8 in the present embodiment. At this time, the capacitance circuit C2 does not produce a mirror effect. Therefore, the influence of the fluctuation of the power supply reference voltage V7 is almost directly applied from the power supply reference voltage generation circuit (first energization circuit) 7 to the gate of the transistor Tr1, and can follow the fluctuation of the power supply reference voltage V7.

  Therefore, when it is desired to make the output of the power supply voltage V1 follow the power supply reference voltage V7 at a high speed, the configuration of this embodiment is adopted, compared with a configuration in which an RC filter is simply inserted in the output energization path of the power supply reference voltage V7. The followability to the fluctuation of the power supply reference voltage V7 can be improved.

  Since the generation voltage V6 of the constant voltage generation circuit 6 is provided, the transistor Tr1 is turned on before the on-timing of the transistor Tr4. In order to adjust the time length of the mirror section Y1, the generation voltage V6 of the constant voltage generation circuit 6 may be adjusted.

(Second Embodiment)
7 to 8 show a second embodiment of the present invention. The difference from the previous embodiment is that a source follower transistor is provided on the low side and a drive circuit section is provided on the high side, and the driving is performed. It is in the place where the power supply is supplied to the circuit part. Parts that are the same as or similar to those in the previous embodiment are given the same or similar reference numerals (for example, the suffix “a” is added), and different parts from the previous embodiment will be mainly described.

  A power supply circuit 2a is configured in the semiconductor integrated circuit device 1a shown in FIG. The power supply circuit 2a is configured by connecting a P-channel type MOS transistor Tr1a to the output in the form of a source follower. The transistor Tr1a has a drain connected to the ground GND and a source connected to the DC power supply output terminal T2a. A capacitor C1a is connected to the DC power supply output terminal T2a outside the semiconductor integrated circuit device 1a.

  A drive circuit unit 3a is configured in the semiconductor integrated circuit device 1a, and a DC power supply output terminal T2a is connected to the negative power supply terminal of the drive circuit unit 3a. The DC power supply voltage V1a is supplied to the positive power supply terminal of the drive circuit unit 3a. The drive circuit unit 3a outputs a drive control signal from the drive output terminal T3a to the gate (control terminal) of a switching transistor (hereinafter referred to as transistor) Tr3 to be driven using the supplied DC power supply voltage Vout.

  The power supply circuit 2a is configured by connecting a gate voltage adjusting circuit 5a to the gate of the transistor Tr1a. The gate voltage adjusting circuit 5a is formed by connecting a constant voltage generating circuit 6a, a P-channel MOS transistor (hereinafter referred to as a transistor) Tr4a and a current source I1a in series between a supply terminal of the DC power supply voltage V1a and the ground GND. Composed. The transistor Tr4a is configured as a replica transistor having the same shape and size as the transistor Tr1a. A capacitive circuit C2a is formed between the drain and gate of the transistor Tr4a.

  Similarly to the capacitance circuit C2 of the above-described embodiment, the capacitance circuit C2a is connected in parallel with a capacitor newly formed in the semiconductor integrated circuit device 1 in addition to the parasitic capacitance parasitic on the normal transistor Tr4a, for example. Increased composition (for example, several tens to several hundreds pF). Further, the power supply reference voltage generation circuit 7a applies the DC voltage V7a from the DC power supply voltage V1a to the control terminal (gate) of the transistor Tr4a through the resistor R2a. Details of each circuit will be omitted if it is easy to refer to the description of the above embodiment.

  As shown in FIG. 8, when the power is turned on, the power supply reference voltage generation circuit 7a applies a voltage (V1a-V7a) to the gate of the transistor Tr4a, so that the gate potential of the transistor Tr4a falls below the DC power supply voltage V1a.

  Assuming that the threshold voltage of the transistor Tr4a is Vt4a and the generation voltage of the constant voltage generation circuit 6a is V6a, the transistor Tr1a is turned on when the gate potential of the transistor Tr1a becomes V1a-Vt1 when the DC power supply voltage V1a is supplied from the outside. Then, power supply to the drive circuit unit 3a is started. The gate potentials of the transistors Tr1a and Tr4a drop from the DC power supply voltage V1a due to the influence of the power supply reference voltage generation circuit 7a, but first drop to the DC power supply voltage V1a− (threshold voltage Vt4 + constant voltage V6a). At this time, when the gate potential of the transistor Tr4 is equal to or lower than the power supply voltage V1- (threshold voltage Vt4a + constant voltage V6a of the constant voltage generation circuit 6a), a drain current flows through the transistor Tr4a. When the gain of the transistor Tr4a is -Av, the capacitance circuit C2a between the drain and gate of the transistor Tr4a is multiplied by (1 + Av) according to the Miller effect.

  Therefore, the capacitance circuit C2a between the drain and gate appears to be larger than the actual capacitance formed between the normal drain and gate. The gate potential of the transistor Tr4 reaches the power supply voltage V1- (threshold voltage Vt4a + constant voltage V6a), and enters the voltage sudden rise suppression section (mirror section Y2) due to the action of the capacitor circuit C2a. As in the previous embodiment, the fluctuation of the gate potential Vg of the transistor Tr3a is also suppressed in the mirror period Y2 (see the periods (D) to (E) in FIG. 8). Since the subsequent operation description is the same as that of the above-described embodiment, the description thereof is omitted. According to the present embodiment, the same effect can be obtained when the high-side transistor Tr3a is driven.

(Third embodiment)
9 and 10 show a third embodiment of the present invention. The difference from the first embodiment is that a gate protection circuit such as a Zener diode is inserted to protect the withstand voltage of the transistor control terminal (gate). However, the protection terminal of the transistor is being protected. In addition, a feature is that a level shift circuit is inserted. Parts having the same or similar functions as those in the previous embodiment are given the same reference numerals or similar reference numerals, and descriptions thereof are omitted.

  As shown in FIG. 9, a power supply reference voltage generation circuit 17 is configured in place of the power supply reference voltage generation circuit 7. The power supply reference voltage generation circuit 17 is configured by combining, for example, diodes such as Zener diodes D8 to D10 in the forward direction and / or reverse direction with the current source I2, and when the power supply voltage V1 is turned on, the power supply reference voltage V17 is stabilized. Is applied to the gate of the transistor Tr1 through the resistor R2.

  When the forward voltage of the Zener diodes D8 to D10 is Vf and the Zener voltage is Vz, the power supply reference voltage generation circuit 17 outputs a power supply reference voltage V17 of 2Vf + 1Vz according to the circuit shown in FIG. Although the power supply reference voltage generation circuit 17 is used in place of the power supply reference voltage generation circuit 7 described above, a circuit similar to the power supply reference voltage generation circuit 7 (that is, a diode-connected MOS transistor or the like) is used. Also good.

  As shown in FIG. 9, a Zener diode D11 is connected in the reverse direction between the gate and source of the transistor Tr4. This Zener diode D11 protects the gate voltage of the transistor Tr4. A diode-connected transistor Tr8 and a diode D12 are connected in the forward direction between the source of the transistor Tr4 and the ground GND.

  In addition, a current source I3 is connected to the control terminal (gate) of the transistor Tr4, and when the power is turned on, a constant current is applied to the diodes D11 to D12 and the diode connection transistor Tr8.

  In this case, the gate potential of the transistor Tr4 after power-on is 2Vf + 1Vz according to the voltage drop of the diodes D11 to D12 and the transistor Tr8. That is, the gate potential of the transistor Tr4 is substantially the same as the output of the power supply reference voltage generation circuit 17 described above.

  The emitter and collector of the PNP transistor Tr9 are connected between the gate and ground of the transistor Tr4. The base of the transistor Tr9 is connected to one terminal of the capacitor circuit C2 and to the gate of the transistor Tr1. The transistor Tr9 is a replica transistor having the same shape and the same size as the transistor Tr8, and forms a level shift circuit and a high impedance circuit 8 in this embodiment.

  The power supply reference voltage generation circuit 17 generates a power supply reference voltage V17 by energizing the diodes D8 to D10 with the current source I2. However, after the output of the power supply voltage V1 is stabilized, the generated voltage V17 of the power supply reference voltage generating circuit 17 is all paths that flow into the one terminal side of the gate of the transistor Tr1, the base of the transistor Tr9, and the capacitor circuit C2. The energization path is cut off. If a circuit configuration that directly energizes the gate of the transistor Tr4 without using the transistor Tr9 is used, the power supply reference voltage V17 generated by the power supply reference voltage generation circuit 17 is applied to the diodes D11 and D12 and the transistor Tr8. End up.

  In this embodiment, since the transistor Tr9 is provided as at least a part of the high impedance circuit 8, it is possible to prevent the generation voltage V17 of the power supply reference voltage generation circuit 17 from being energized to at least a circuit subsequent to the transistor Tr9. Even if the generation voltage V17 of the power supply reference voltage generation circuit 17 varies in accordance with the variation of the power supply voltage V1, the influence of the variation voltage does not affect the subsequent circuit of the transistor Tr9. Will be given directly to the gate.

  Therefore, after the power supply voltage V1 is stabilized, the output voltage (2Vf + 1Vz) of the power supply reference voltage generation circuit 17 can be stably applied to the control terminal (gate) of the transistor Tr1. When the fluctuation of the power supply reference voltage V17 generated by the power supply reference voltage generation circuit 17 occurs, the influence of this fluctuation affects only the reference voltages of the diodes D8 to D10. Therefore, the influence of the power supply output according to the fluctuation of the stable power supply voltage V1 after the power is turned on is directly transmitted to the drive circuit unit 3 through the transistor Tr1, and the followability to the fluctuation of the power supply voltage V1 can be improved.

  Since the transistor Tr9 constituting the level shift circuit is a replica transistor of the transistor Tr8, the forward voltage Vf similarly changes according to this temperature characteristic or the like. After power-on, when the power supply voltage V1 rises, the current source I3 energizes the diodes D11 and D12 and the transistor Tr8, but the gate potential of the transistor Tr1 rises through the current source I3.

  When the current source I3 is energized between the emitter base of the transistor Tr8 and the emitter-base voltage of the transistor Tr9 reaches the level shift voltage (threshold voltage Vt9 of the transistor Tr9), the forward voltage Vf between the emitter base of the transistor Tr8. Since the mirror section Y1 is generated as in the above-described embodiment, an increase suppressing action of the gate potential Vg of the transistor Tr3 is obtained.

  Since the current supplied to the gate protection diode D11 is only due to the current source I3 (see the arrow in FIG. 9), the constant current value of the current source I3, the diodes D11 and D12, the transistor Tr8, and the transistor Tr4 The gate protection circuit of the transistor Tr4 can be designed only with various design parameters, and the design freedom can be improved and the design can be facilitated.

  In the present embodiment, an example using the N-channel MOS transistor Tr1 as in the first embodiment has been described. However, the present invention is not limited to this, and a P-channel MOS transistor is used as in the second embodiment. You may comprise using Tr1a.

  In the present embodiment, the transistor Tr9 is used so that the impedance of the circuit viewed from the output side of the power supply reference voltage generation circuit 17 becomes high impedance. For example, as shown in FIG. 10, a high impedance input buffer X1 may be used instead of the transistor Tr9 and the current source I3 shown in FIG. In this case, both the level shift transistors Tr8 and Tr9 are unnecessary.

(Fourth embodiment)
FIG. 11 shows a fourth embodiment of the present invention. The difference from the previous embodiment is that the power supply reference voltage of the first energization circuit and a predetermined voltage are differentially input and the capacitance circuit is transiently turned on when the power is turned on. Is provided with a differential amplifier having a mirror capacity. Parts that are the same as or similar to those in the previous embodiment are given the same or similar reference numerals, and descriptions thereof are omitted. Hereinafter, different parts will be described.

  One terminal of the capacitor circuit C2 is connected to the gate of the transistor Tr1, and the other terminal of the capacitor circuit C2 is connected to the output terminal of a differential amplifier (corresponding to a transient potential starting circuit) X2. In the differential amplifier X2, the reference voltage (corresponding to a predetermined voltage) V10 of the reference voltage generation circuit 10 is input to the non-inverting input terminal, and the common connection node N1 of the resistor R2 and the gate of the transistor Tr1 is connected to the inverting input terminal. Configured.

  Immediately after the power is turned on, when the power supply reference voltage V7 rises, the capacitor circuit C2 is charged and the gate potential of the transistor Tr1 (potential of the node N1) rises. On the other hand, the generated reference voltage V10 of the reference voltage generating circuit 10 gives the reference voltage V10 of the reference voltage generating circuit 10 to the non-inverting input terminal of the differential amplifier X2. For this reason, when the output of the differential amplifier X2 fluctuates transiently after the power is turned on, a mirror effect is generated in the capacitance circuit C2, the apparent capacitance is multiplied by (1 + Av), and the rising slew rate can be limited in substantially the same manner as in the previous embodiment. . Since it can be made larger than the actual capacity in accordance with the mirror effect, the mounting area for separately configuring the capacity in the semiconductor integrated circuit device 1 can be suppressed.

  When the output of the differential amplifier X2 is finally stabilized, the steady state is obtained. Thereafter, even if the power supply reference voltage V7 of the power supply reference voltage generation circuit 7 changes, it directly affects the gate potential of the transistor Tr1, and the change in the power supply reference voltage V7 immediately affects the source follower output of the transistor Tr1. Will be affected. Therefore, as in the above-described embodiment, the power supply output can be changed immediately according to the change in the power supply reference voltage V7, and the followability can be improved.

(Fifth embodiment)
FIG. 12 shows a fifth embodiment of the present invention. The difference from the previous embodiment is that a zener diode or the like is inserted to protect the control terminal of the transistor in order to protect the control terminal (gate). Is where you are. In addition, the power supply reference voltage is set to be equal to or lower than the voltage obtained by adding the protection voltage of the protection circuit and the specified voltage of the potential specifying circuit, thereby eliminating the need to provide the level shift circuit according to the above-described embodiment. Features. Parts having the same or similar functions as those in the previous embodiment are given the same reference numerals or similar reference numerals, and descriptions thereof are omitted.

  As shown in FIG. 12, a constant voltage generation circuit 16 instead of the constant voltage generation circuit 6 is configured by connecting Zener diodes D12a to D12z in the forward direction and / or the reverse direction, and the power supply voltage V1 is turned on to enter a steady state. Then, the specified potential V16 is applied to the source of the transistor Tr4.

  Further, Zener diodes D11a to D11z constituting a gate protection circuit are connected in series in the forward direction and / or the reverse direction between the gate and source of the transistor Tr4. When the protection voltage at this time is V11, it is desirable that the power supply reference voltage V17 is set to be less than the protection voltage V11 + the specified potential V16. This is because the current based on the power supply reference voltage V17 does not flow through the Zener diodes D11a to D11z and D12a to D12z. That is, it is not necessary to provide the level shift circuit used in the above embodiment.

(Other embodiments)
The present invention can be modified or expanded as follows in addition to the configuration of the embodiment described above. In the embodiment described above, the current source I1 is used to supply current to the drain of the transistor Tr4. However, a circuit in which a resistor is connected to the power supply voltage V1 may be used instead of the current source I1.

  In the above-described embodiment, the gate protection circuit (zener diode D11) and the level shift circuits Tr8 and Tr9 are provided. However, in the first place, when the power supply voltage V1 is lower than the gate breakdown voltage of the transistor Tr4, the gate protection is performed. There is no need to provide a circuit.

  In the drawing, C2 is a capacitor circuit, 2 and 2a are power supply circuits (starting circuits), 3 is a drive circuit section, 6 and 6a are constant voltage generation circuits (potential regulation circuits), and 7 and 17 are power supply reference voltage generation circuits (first circuit). 1 energization circuit), I1 is a current source (second energization circuit, start-up potential holding circuit), X1 is a buffer (high impedance circuit), X2 is a differential amplifier, Tr1 and Tr1a are first transistors, Tr3 is a switching transistor, Tr4 and Tr4a are second transistors, and Tr8 and Tr9 are transistors (level shift circuits).

Claims (9)

A start circuit (2 or 2a) including a first transistor (Tr1 or Tr1a) having a control terminal and energizing the power supply target circuit from the first transistor in response to energization of the control terminal when the power is turned on. )
The starting circuit is
A first energization circuit (7 or 7a) for energizing a power supply reference voltage (V7) to the control terminal of the first transistor through an output energization path (N1 or N1a) when power is turned on;
The first transistor is connected to the control terminal of the first transistor, and is configured by adding capacitance in addition to the parasitic capacitance parasitic to the first transistor. When the power is turned on, the control terminal of the first transistor is connected to the first conduction circuit. A capacitor circuit (C2) that is charged as a mirror capacitor when the power supply reference voltage is transiently set to a predetermined potential by applying the power supply reference voltage ;
A second transistor (Tr4 or Tr4a) whose control terminal is commonly connected to the control terminal of the first transistor;
A circuit for differentiating an on threshold reference potential of the second transistor from an on threshold reference potential of the first transistor, and a potential defining circuit (6 or 6a) that turns on the first transistor before the second transistor when power is turned on; , Tr8 and D12),
A second energization circuit for energizing the power input terminal (N2) of the second transistor when the power is turned on,
It said capacitive circuit (C2) is constructed as a two-terminal circuit, connected to a power supply circuit according to claim Rukoto between the output current path to the power supply input terminal by the second energizing circuit the first power supply circuit. A start circuit (2 or 2a) including a first transistor (Tr1 or Tr1a) having a control terminal and energizing the power supply target circuit from the first transistor in response to energization of the control terminal when the power is turned on. )
The starting circuit is
A first energization circuit (7 or 7a) for energizing a power supply reference voltage (V7) to the control terminal of the first transistor through an output energization path (N1 or N1a) when power is turned on;
The first transistor is connected to the control terminal of the first transistor, and is configured by adding capacitance in addition to the parasitic capacitance parasitic to the first transistor. When the power is turned on, the control terminal of the first transistor is connected to the first conduction circuit. A capacitor circuit (C2) that is charged as a mirror capacitor when the power supply reference voltage is transiently set to a predetermined potential by applying the power supply reference voltage;
The capacitor circuit is composed of a two-terminal circuit,
When the capacitor circuit is charged as a mirror capacitor, the potential change direction of a terminal energized and connected to the capacitor circuit from the first energization circuit is opposite to the change direction of the terminal potential on the opposite side of the terminal. And a reverse energization circuit ( X2 )
The reverse energization circuit includes a differential amplifier (X2) that is supplied with a reference voltage at one terminal and connects the output energization path (N1) of the first energization circuit to the other terminal and the output terminal. A featured power supply circuit.   When the power is turned on, the capacitor circuit is energized from the output energization path of the first energization circuit, and in a steady state, the energization path other than the energization path from the first energization circuit to the control terminal of the first transistor is shut off. The power supply circuit according to claim 1 or 2, further comprising an impedance circuit (8). The power supply circuit according to claim 1, wherein the second transistor (Tr4) is a replica transistor of the first transistor (Tr1) . 5. The power supply circuit according to claim 1, further comprising a gate protection circuit including a Zener diode (D11) for protecting a control terminal of the second transistor (Tr4 or Tr4a) . The power supply reference voltage (V7) of the first energization circuit (7) is set to a voltage less than the sum of the protection voltage of the second transistor (Tr4 or Tr4a) by the gate protection circuit and the regulation voltage of the potential regulation circuit. The power supply circuit according to claim 5 . A high impedance circuit (8) for cutting off a current energization path other than energizing the capacitor circuit (C2) when power is turned on from the output energization path (N1) of the first energization circuit (7);
The power supply according to any one of claims 1 to 4, wherein at least a part of the high impedance circuit (8) is configured in front of a control terminal of the second transistor (Tr4 or Tr4a). circuit. A gate protection circuit including a Zener diode (D11) for protecting the control terminal of the second transistor (Tr4);
Level shift circuits (Tr8 and Tr9) for level-shifting the on-threshold reference potential by the potential defining circuit (6) according to the power supply reference voltage (V7) of the first energization circuit (7) and the protection voltage of the gate protection circuit The power supply circuit according to claim 1, further comprising : A power supply target circuit of the power supply circuit according to any one of claims 1 to 8, comprising a drive circuit unit (3) for applying a drive signal to a drive target,
The drive circuit unit includes a parasitic capacitance between a power supply terminal and an output terminal, and when the power is turned on, a current is supplied from the first transistor of the activation circuit to the control terminal of the switching transistor (Tr3) to be driven through the parasitic capacitance. Drive circuit .

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