JP5839892B2 - Solder material and semiconductor device - Google Patents

Description

  The present invention relates to a solder material and a semiconductor device, and more particularly to a solder material suitable for use in incorporating a semiconductor element into a semiconductor device and a semiconductor device using the solder material.

  Conventionally, a semiconductor device in which a semiconductor element is soldered to a base plate and sealed with a resin is used. Such a semiconductor device is disclosed as a conventional power module in, for example, the paper “Large-capacity resin-encapsulated power module using lead bonding” (Non-Patent Document 1). In this power module, a semiconductor element is mounted on a ceramic substrate, and the ceramic substrate is soldered to a base plate. The base plate is bonded to the resin case. The space in the case is filled with insulating gel.

  The semiconductor device as described above is generally assembled through the following processes. That is, a solder material is disposed between the semiconductor element and the substrate, and a solder material is disposed between the substrate and the base plate. After the whole is heated to a temperature equal to or higher than the melting point of the solder material and the solder material is melted, the solder material is cooled to solidify the solder material. As a result, the semiconductor element and the substrate, or the substrate and the base plate are joined.

  As the solder material, for example, Sn-37Pb (lead) alloy solder whose main component is Sn (tin) is used. A solder paste may be supplied as the solder material, or a plate-shaped solder material may be supplied. Regardless of which solder material is used, the solder material is once melted to wet the surfaces of the semiconductor element, substrate, and base plate, which are materials to be joined, to cause an alloy reaction, and then the solder material solidifies to join. There is no change in achieving.

  In general, a metal material shrinks by several percent when it solidifies from a molten state and transforms into a solid. Similarly, the solder material used in the semiconductor device as described above has a solidification shrinkage rate of about 3%. Therefore, when the solder material is once melted and then solidified, the solder material contracts. If the solder material supplied to the joint portion shrinks uniformly as a whole, a sound joint portion is formed. However, when the size of the joint portion increases, it becomes difficult to solidify the whole joint portion at the same time.

  In the solder material, the solidified phase sequentially expands from the portion where the temperature first decreased, and the portion where the temperature decrease occurred most slowly becomes the final solidified portion. In this case, in the initial stage of solidification, the solidification proceeds while the liquid solder that has not yet solidified moves to compensate for the solidification shrinkage in a portion where the volume has decreased due to solidification. For this reason, solidification shrinkage occurs intensively around the final solidified portion, and as a result, solidification shrinkage cracks are formed.

  As a technique for solving such a problem of solidification shrinkage, for example, in Japanese Patent Laid-Open No. 2005-186160 (Patent Document 1), the solder is solidified by managing the Ag (silver) concentration and the Cu (copper) concentration of the solder. A method has been proposed in which the surface of the solder is not uneven and the gloss can be maintained and at the same time the shrinkage can be prevented.

JP-A-2005-186160

Yasushi Nakajima et al., “High-capacity resin-encapsulated power module using lead bonding”, “Procedure of 11th Micro-Joint and Packaging Technology Symposium Vol.11 2005”, Japan Welding Society, 2005, pp . 433-436

  When the joint size is sufficiently smaller than, for example, 10 mm × 10 mm, solidification occurs substantially simultaneously, so that remarkable solidification shrinkage cracks are rarely generated. However, in the case of a joint having a size of 10 mm × 10 mm or more, for example, As shown in FIG.

  Even when the solder material used in the technique described in Japanese Patent Application Laid-Open No. 2005-186160 is applied to a minute joint, generation of shrinkage nests can be suppressed, but a large joint having a size of, for example, 10 mm × 10 mm or more. When applied to the part, there is a problem in that solidification shrinkage is concentrated around the final solidification part as described above, and solidification shrinkage cracks still occur.

  The present invention has been made in view of the above problems, and an object thereof is to provide a solder material capable of suppressing the occurrence of solidification shrinkage cracking and a semiconductor device using the solder material.

  The solder material of the present invention has a composition with a solid phase ratio of 30% or more at a temperature immediately above the solid phase line.

  According to the solder material of the present invention, the solid phase ratio at a temperature immediately above the solidus becomes 30% or more, so the amount of primary crystals becomes 30% or more before the solder material reaches the solidus temperature. For this reason, it is possible to reduce the amount of solder material that goes from the liquid phase to the solid phase at the solidus temperature. Therefore, it is possible to reduce the amount of the liquid phase solder material that solidifies while moving so as to compensate for the solidification shrinkage. Thereby, it can suppress that the solidification shrinkage concentrates around the last solidification part and the solidification shrinkage crack occurs.

It is a schematic sectional drawing of the semiconductor device in one embodiment of this invention. It is sectional drawing which showed typically the soldering part of the semiconductor device in one embodiment of this invention. It is a schematic sectional drawing of the semiconductor device of a comparative example. It is sectional drawing which showed typically the soldering part of the semiconductor device of a comparative example. It is a figure which shows the X-ray photograph of the soldering part of the semiconductor device of the comparative example 1 in an Example. It is a figure which shows the X-ray photograph of the soldering part of the semiconductor device of the comparative example 2 in an Example. It is a figure which shows the X-ray photograph of the soldering part of the semiconductor device of the example 1 of this invention in an Example. It is a figure which shows the X-ray photograph of the soldering part of the semiconductor device of the example 2 of this invention in an Example. It is a figure which shows the X-ray photograph of the soldering part of the semiconductor device of the example 3 of this invention in an Example. It is a figure which shows the X-ray photograph of the soldering part of the semiconductor device of the example 4 of this invention in an Example.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a configuration of a solder material and a semiconductor device using the solder material according to an embodiment of the present invention will be described.

  Referring to FIG. 1, a semiconductor device 10 according to an embodiment of the present invention mainly includes a semiconductor element 1, a substrate 2, a base material 3, a solder material 4, a case 5, and a gel 6. doing. The semiconductor element 1 is an element using a substrate made of, for example, Si (silicon). The semiconductor element 1 has a square shape of, for example, 7 mm × 7 mm.

  The substrate 2 is for mounting the semiconductor element 1. The board | substrate 2 has the core material 2a and the conductor part 2b. Core material 2a is a ceramic substrate made of, for example, AlN (aluminum nitride). The conductor portion 2b is provided on one surface (upper surface) and the other surface (lower surface) of the core member 2a. The material of the conductor portion 2b is, for example, Cu. The conductor portion 2b has a rectangular shape of 15 mm × 20 mm, for example. The base material 3 is a base plate for fixing the substrate 2. The material of the base material 3 is, for example, a Cu alloy.

  The solder material 4 has a composition in which the solid phase ratio at a temperature immediately above the solid phase line is 30% or more. The temperature immediately above the solidus is slightly higher than the solidus and 1 ° C. higher than the solidus. The solid phase ratio is the ratio of the mass of the solid phase to the mass of the solid phase and the liquid phase. The solder material 4 is, for example, a solder alloy containing 7 mass% Sn (tin), 7.5 mass% Sb (antimony), 1 mass% Ag and the balance being Pb and inevitable impurities (hereinafter, the alloy composition is as follows) Pb-7Sn-7.5Sb-1Ag).

  The solder material 4 should just contain 2 or more types chosen from the group which consists of Sn, Pb, Bi (bismuth), In (indium), Zn (zinc), Ag, Cu, and Ni (nickel). The solidus temperature of the solder material 4 is 238 ° C., for example, and the liquidus temperature is 257 ° C., for example. The solidus temperature of the solder material 4 is preferably higher than 183 ° C.

The semiconductor element 1 and the substrate 2 are joined via a solder material 4. Two semiconductor elements 1 are soldered to the substrate 2 at respective solder joints. The joint area of the solder material 4 at each solder joint is 100 mm ² or more. The substrate 2 and the base material 3 are joined via a solder material 4. The joint area of the solder material 4 at the solder joint between the substrate 2 and the base material 3 is also 100 mm ² or more. Note that it is only necessary that at least one of the semiconductor element 1 and the base material 3 and the substrate 2 are bonded via the solder material 4.

  The case 5 is a container and is attached to the base material 3. The material of the case 5 is, for example, an epoxy resin. The gel 6 seals the semiconductor element 1. The gel 6 is an insulating material. The material of the gel 6 is, for example, a silicone resin.

Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described.
A solder material 4 is disposed between the semiconductor element 1 and the substrate 2, and a solder material 4 is disposed between the substrate 2 and the base material 3. After the whole is heated to a temperature equal to or higher than the melting point (liquidus) of the solder material 4 and the solder material 4 is completely melted, the solder material 4 is cooled and the solder material 4 is solidified. The substrate 2 and the substrate 2 and the base material 3 are joined. Further, in a later step, a component may be added by soldering using Sn—Pb eutectic solder having a melting point of 183 ° C.

  As the solder material 4, a mixture of solder powder having a particle diameter of about 0.01 mm to 0.1 mm, which is called a solder paste, and a flux such as rosin may be supplied, or about 0.03 mm to 0.5 mm. Thick plate-shaped solder may be supplied. In the case of plate-like solder, it is necessary to supply a liquid flux separately or to remove the oxide film on the surface of the member to be joined and the solder material itself using a reducing material such as hydrogen gas. Even when the solder material 4 is supplied in any form, the solder material 4 is once melted to wet the surfaces of the semiconductor element 1, the substrate 2, and the base material 3, which are to be joined, to cause an alloy reaction, There is no change in achieving the joining by solidifying the material 4.

Next, the effect of one embodiment of the present invention will be described in comparison with a comparative example.
Referring to FIG. 2, solder material 4 used in semiconductor device 10 according to the embodiment of the present invention has primary crystal 21 and final solidified portion 22. The primary crystal 21 is a crystal that is first solidified and grown. The final solidified portion 22 is a portion that is finally solidified at a temperature near the solidus. In addition, fine voids 23 are formed in the solder material 4.

  When the solder material 4 is used for assembling the semiconductor device 10, the temperature of the solder material 4 is once increased to melt the solder material 4. Thereafter, the solidification gradually proceeds from the stage where the solder material 4 is cooled to the liquidus temperature or lower, and the primary crystal 21 grows. When the solder material 4 reaches a temperature (for example, 239 ° C.) slightly higher than the solidus temperature (for example, 238 ° C.), the amount of the primary crystal 21 has already become 30%.

  At this stage, the growth of the primary crystal 21 starts restraint on the entire solder joint surface between the semiconductor element 1 and the substrate 2 and between the substrate 2 and the base material 3. Therefore, in the case of the solder material 4 according to the embodiment of the present invention, the solidification shrinkage of about 3% occurs as in the conventional case, but the solidification shrinkage occurs uniformly on the entire solder joint surface as the solidification progresses. . For this reason, it is suppressed that solidification shrinkage concentrates on a partial region of the solder material 4 to cause solidification shrinkage cracking.

  On the other hand, in the semiconductor device 10 of the comparative example of the embodiment of the present invention with reference to FIG. 3, the composition of the solder material 4 is different from that of the semiconductor device 10 of the embodiment of the present invention. In the comparative example, a solder alloy of Pb-8Sn-10Sb-1Ag is used as the solder material 4. This solder alloy has a melting point close to the solder material 4 of Pb-7Sn-7.5Sb-1Ag according to the embodiment of the present invention described above, the solidus temperature is 238 ° C., and the liquidus The temperature is 240 ° C. Further, in the solder material 4 of the comparative example, the solid phase ratio immediately above the solid phase line is 10%.

  As shown in FIG. 3, in the semiconductor device 10 of the comparative example 4, remarkable solidification shrinkage cracks 7 occur in the solder material 4. In Comparative Example 4, the reason why the solidification shrinkage crack 7 occurs in the solder material 4 will be described. Referring to FIG. 4, in the solder material 4 of the comparative example, the amount of the primary crystal 21 at a temperature immediately above the solidus temperature of the solder material 4 is not sufficient. Therefore, solidification shrinkage when the final solidified portion 22 is solidified concentrates on a part, and solidification shrinkage cracks 8 occur in the solder joint portion.

  According to the solder material 4 of the present embodiment, the solid phase ratio at the temperature immediately above the solidus becomes 30% or more, so the amount of primary crystals is 30 before the solder material 4 reaches the solidus temperature. % Or more. For this reason, it is possible to reduce the amount of the solder material 4 from the liquid phase to the solid phase at the solidus temperature. Therefore, it is possible to reduce the amount of the liquid phase solder material 4 that solidifies while moving so as to compensate for the solidification shrinkage. Thereby, it can suppress that the solidification shrinkage concentrates around the last solidification part and the solidification shrinkage crack occurs. Therefore, a normal solder joint can be obtained.

  When the solid phase ratio at a temperature immediately above the solidus is further increased from 30% or more to 35% or more, the occurrence of solidification shrinkage cracks can be suppressed more stably. For example, when the solder material 4 is Pb-6.7Sn-7.1Sb-0.95Ag, the solidus temperature is 238 ° C., similar to the solder material 4 of the above-described embodiment of the present invention. The solid phase ratio at a temperature just above the phase line is 35%. Therefore, when the larger substrate 2 and the base material 3 are joined, for example, even when the size of the solder joint is 50 mm × 60 mm, the occurrence of solidification shrinkage cracking can be suppressed.

  In the above description, the case where Pb-7Sn-7.5Sb-1Ag and Pb-6.7Sn-7.1Sb-0.95Ag are used as the solder material 4 has been described. It goes without saying that the same effect as described above can be obtained if the solid phase ratio at a temperature immediately above is 30% or more. For example, Pb-6.7Sn-7.1Sb-0.95A having a solid phase ratio of 44% at a temperature immediately above the solidus line, and Pb- having a solid phase ratio of 66% at a temperature immediately above the solid line. Even with 27Sn-3Sb, the same effect as described above can be obtained.

  The solder material 4 according to one embodiment of the present invention includes two or more selected from the group consisting of Sn, Pb, Bi, In, Zn, Ag, Cu and Ni. Thereby, it is possible to obtain a solder material 4 having an appropriate melting point, wettability with an object to be joined (alloy forming property), mechanical characteristics of the joint after soldering, and the like. When Bi, In, and Zn are added in an amount of about 0.5% by mass, a particularly suitable solder material 4 can be obtained. In general, since Cu and Ni are contained in the material to be bonded, the solder material 4 which does not contain Cu and Ni can be an appropriate solder material 4 containing Cu and Ni after being soldered. .

  The solder material 4 of one embodiment of the present invention preferably has a solidus temperature higher than 183 ° C. Thereby, in a later process, the heat resistance to the heating in the soldering in the case where a component is added can be given by using a Sn—Pb eutectic solder having a melting point of 183 ° C. for soldering. The solidus temperature of the solder material 4 is more preferably higher than 190 ° C. Thereby, heat resistance can be further provided.

  In the semiconductor device 10 according to an embodiment of the present invention, at least one of the semiconductor element 1 and the base material 3 and the substrate 2 are joined via the solder material 4. Thereby, since generation | occurrence | production of the solidification shrinkage crack of the solder material 4 can be suppressed, the semiconductor device 10 which has a normal solder junction part can be obtained. Therefore, the reliability of the semiconductor device 10 can be improved.

In the semiconductor device 10 according to one embodiment of the present invention, the bonding area at one location of the solder material 4 may be 100 mm ² or more. Even if the bonding area at one location of the solder material 4 is 100 mm ² or more, the occurrence of solidification shrinkage cracking can be suppressed. Therefore, a normal solder joint can be obtained in the semiconductor device 10 having a large solder joint.

  Although the case where an element made of Si is used as the semiconductor element 1 is described above, the present invention is not limited to this, and the case where an element made of a compound semiconductor such as SiC (silicon carbide) or GaAs (gallium arsenide) is also used. The same effect can be obtained.

Although the case where an AlN substrate is used as the substrate 2 has been described above, the same effect as described above can be obtained when a ceramic such as Al ₂ O ₃ (aluminum oxide) or Si ₃ N ₄ (silicon nitride) is used. It is done.

Examples of the present invention will be described below.
In this example, after assembling the above semiconductor device using six kinds of solder materials having different solid phase ratios at a temperature immediately above the solid phase line, the semiconductor device was viewed from the upper surface of each semiconductor device using an X-ray observation apparatus. A transmission image of the soldering part was taken. 5 to 10 are diagrams showing X-ray photographs of the semiconductor device 10 using six different solder materials.

  FIG. 5 shows a soldered portion of the semiconductor device 10 of Comparative Example 1 using a solder material having a composition of Pb-8Sn-10Sb-1Ag having a solid phase ratio of 10% at a temperature immediately above the solid phase line. ing. In FIG. 6, the soldering part of the semiconductor device 10 of Comparative Example 2 using a solder material having a composition of Pb-7Sn-8.5Sb-1Ag having a solid phase ratio of 20% at a temperature immediately above the solid phase line is shown. It is shown.

  In FIG. 7, the soldering of the semiconductor device 10 of the present invention example 1 using a solder material having a composition of Pb-7Sn-7.5Sb-1Ag having a solid fraction of 30% at a temperature immediately above the solid phase line. The parts are shown. In FIG. 8, the semiconductor device of Example 2 of the present invention using a solder material having a composition of Pb-6.7Sn-7.1Sb-0.95Ag having a solid phase ratio of 35% at a temperature immediately above the solid phase line. Ten soldered portions are shown. In FIG. 9, the semiconductor device 10 of Example 3 of the present invention using a solder material having a composition of Pb-6Sn-6.4Sb-0.85 Ag with a solid fraction of 44% at a temperature immediately above the solidus line. The soldering part is shown. FIG. 10 shows a soldering portion of the semiconductor device 10 of Example 4 of the present invention using a solder material having a composition of Pb-27Sn-3Sb having a solid phase ratio of 66% at a temperature immediately above the solid phase line. Yes. Inventive Examples 1 to 4 have Sb of 7.5% by mass or less.

  Referring to FIGS. 5 to 10, the portion that appears white in the soldering portion is a portion that appears bright because the attenuation when X-rays pass through the solder layer is small. That is, a portion that appears white in the drawing in the soldering portion indicates that a void exists in the solder material. In Comparative Example 1 and Comparative Example 2 in which the solid phase ratio at a temperature immediately above the solid phase line was low, many portions that appeared white in the soldered portion were observed. That is, in Comparative Example 1 and Comparative Example 2, it was found that solidification shrinkage cracks 7 occurred.

  On the other hand, in Example 1 of the present invention in which the solid fraction directly above the solid phase line was 30%, it was found that no solidification shrinkage cracks 7 occurred because there was no white portion at the soldered portion. Moreover, it turned out that the solidification shrinkage crack 7 does not occur in the present invention examples 2 to 4 having a higher solid phase ratio at a temperature just above the solidus than in the present invention example 1 because there is no white portion in the soldered portion. .

  From the above, it was found that solidification shrinkage cracking did not occur in the solder materials of Invention Examples 1 to 4 having a composition in which the solid phase ratio immediately above the solid phase line was 30% to 66%. In other words, it was found that solidification shrinkage cracking did not occur in the solder material having a composition with a solid fraction of 30% or more immediately above the solid phase line.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 Semiconductor element, 2 board | substrate, 2a core material, 2b conductor part, 3 base material, 4 solder material, 5 case, 6 gel, 7 solidification shrinkage crack, 10 semiconductor device, 21 primary crystal, 22 final solidification part, 23 space | gap.

Claims (5)

Has a composition solid fraction at 1 ℃ temperature higher than the solidus temperature is 66% to 30% or more or less, have a composition of Pb-Sn-Sb system, a 6 wt% or more 27 wt% or less of Sn A solder material containing 3% by mass to 7.5% by mass of Sb . B i, comprising In, Zn, Ag, at least one member selected from the group consisting of Cu and Ni, the solder material according to claim 1.   The solder material according to claim 1 or 2, wherein the solidus temperature is higher than 183 ° C. The solder material according to any one of claims 1 to 3,
A semiconductor element;
A substrate for mounting the semiconductor element;
A base material for fixing the substrate;
A semiconductor device, wherein at least one of the semiconductor element and the base material is bonded to the substrate via the solder material. The semiconductor device according to claim 4, wherein a bonding area at one place of the solder material is 100 mm ² or more.