JP5841356B2 - Solid-state imaging device, control method for solid-state imaging device, and imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device, a control method for a solid-state imaging device, and an imaging device.

In recent years, CMOS (Complementary Metal Oxide Semiconductor) solid-state imaging devices (hereinafter referred to as “MOS-type solid-state imaging devices”) have attracted attention and have been put to practical use as solid-state imaging devices.
Unlike a CCD (Charge Coupled Device) type solid-state imaging device, this MOS type solid-state imaging device can be driven by a single power source. In addition, while a CCD type solid-state imaging device requires a dedicated manufacturing process, a MOS type solid-state imaging device can be manufactured using the same manufacturing process as other LSIs, so that the SOC (System On Chip). The solid-state imaging device can be made multifunctional.
In addition, since the MOS solid-state imaging device amplifies signal charges in each pixel by providing an amplification circuit in each pixel, the MOS-type solid-state imaging device is configured not to be affected by noise from a signal transmission path. Further, the signal charge of each pixel can be selected and taken out (selection method), and in principle, the signal accumulation time and readout order can be freely controlled for each pixel.

  Conventionally, a line exposure method and a global exposure method are known as exposure methods for a general MOS solid-state image pickup device (hereinafter also referred to as “solid-state image pickup device”). In the line exposure method, a large number of pixels arranged two-dimensionally in the solid-state imaging device are exposed at different timings for each row. In this method, a video signal of a subject is obtained by sequentially reading out signal charges generated by photoelectric conversion elements in pixels in the row after performing exposure of a certain row. In the case of the line exposure method, exposure and reading can be continuously performed in units of rows. For this reason, the video signal of the subject can be obtained in a state where the influence of noise generated in the storage unit that stores the signal charge generated by the photoelectric conversion element is minimized. However, when a subject moving with the line exposure method is photographed, the subject cannot be imaged correctly because the exposure timing differs for each row. That is, in the line exposure method, there is a problem that an image in which the subject is distorted is obtained depending on the moving direction of the subject.

  On the other hand, the global exposure method is a method in which all pixels arranged two-dimensionally in the solid-state imaging device are exposed at the same timing. In the case of the global exposure method, since all the pixels are exposed at the same timing, there is no problem that a distorted image is obtained even when a moving subject is photographed. However, in the global exposure method, after all the pixels are exposed, the signal charges generated by the photoelectric conversion elements in the pixels are sequentially read out, so it takes time to start reading the signal charges after the exposure is completed. In the required pixel, it is difficult to suppress the influence of noise generated in the storage unit. For this reason, a global exposure type solid-state imaging device often provides a noisy video signal as compared to a line exposure type solid-state imaging device.

  In the global exposure type solid-state imaging device, by adding a circuit for suppressing the influence of noise generated in the storage unit as described above to the solid-state imaging device, even in the solid-state imaging device adopting the global exposure method, the influence of noise is reduced. A video signal that is minimized can be obtained. However, by adding a circuit that suppresses the influence of such noise to the solid-state imaging device, there is a problem that the entire area of the solid-state imaging device increases and the solid-state imaging device itself increases in size.

  As a technique for solving such a problem, for example, as in Patent Document 1, a pixel circuit unit of a MOS type solid-state imaging device is manufactured as a pixel circuit chip, while a signal processing unit is manufactured as a signal processing chip, A method of stacking these separately manufactured chips is disclosed. In the technique disclosed in Patent Document 1, a separately manufactured pixel circuit chip and a signal processing chip are connected via bumps.

JP 2006-49361 A

  By the way, it is known that the following two problems occur when high-intensity light is incident on the MOS type solid-state imaging device. One problem is that a pixel on which high-intensity light is incident outputs a pixel signal corresponding to a black level. Hereinafter, this phenomenon is referred to as “black sun phenomenon”. The other is that the pixel signal output from the pixel arranged in the same row as the pixel to which the high-intensity light is incident is a pixel signal that is brighter than the original pixel signal that exposed the subject. It is a malfunction that ends. As a result, horizontal stripes appear in the video signal of the subject. Hereinafter, this phenomenon is referred to as a “lateral stripe phenomenon”.

  The black sun phenomenon and the horizontal stripe phenomenon due to the high luminance light as described above can be suppressed by adding a countermeasure circuit to the pixel circuit chip. However, in the case of a MOS type solid-state imaging device that employs a method of joining chips as disclosed in Patent Document 1, a countermeasure circuit is provided at all the locations where the pixel circuit chip and the signal processing chip are connected, that is, at the bump locations. It is necessary to provide. For this reason, an increase in the area of the pixel circuit chip cannot be avoided. Further, by providing the countermeasure circuit in the pixel circuit chip, the area occupation ratio of the pixels in the pixel circuit chip is reduced. As a result, there is a problem in that the dynamic range of the pixel is reduced, circuit noise of the pixel is increased, and the video signal (image) of the subject is deteriorated.

  The present invention has been made on the basis of the above-mentioned problem recognition, and in a solid-state imaging device configured by connecting a plurality of chips, even when high-intensity light is incident, it has good noise and good global An object of the present invention is to provide a solid-state imaging device capable of acquiring an exposure-type image, a control method for the solid-state imaging device, and an imaging device.

In order to solve the above-described problem, a solid-state imaging device according to an aspect of the present invention includes a connection unit that electrically connects the first substrate and the second substrate, and the first substrate and the second substrate. A solid-state imaging device that is electrically connected to a substrate, wherein a pixel portion included in the solid-state imaging device is included in the first substrate, includes a photoelectric conversion element, and generates a pixel signal ; a signal line for supplying to said second substrate a No. field Motoshin, included in the second substrate, a signal storage circuit for storing the pixel signals supplied via the signal line, the second included in the substrate, and an output circuit for outputting the pixel signal stored in the signal storage circuit, included in the second substrate, the voltage of the pixel No. signal is clipped so as not fall below a predetermined voltage It has a clip circuit which, the.

According to another aspect of the present invention, there is provided a method for controlling a solid-state imaging device, wherein the first substrate and the second substrate are connected by a connection unit that electrically connects the first substrate and the second substrate. A method for controlling a solid-state imaging device to be electrically connected, the pixel signal generated in a pixel including a photoelectric conversion element included in the first substrate of a pixel portion included in the solid-state imaging device being the second Outputting to a signal line supplied to the substrate; storing a pixel signal supplied via the signal line in a signal storage circuit included in the second substrate; and an output circuit included, the step of outputting the pixel signals accumulated in the signal accumulating circuit, a clip circuit included in the second substrate, so that the voltage of the pixel No. signal is not below the predetermined voltage To clip to Tsu including and up, the.

An imaging device according to an aspect of the present invention electrically connects the first substrate and the second substrate by a connection unit that electrically connects the first substrate and the second substrate. an imaging apparatus for a pixel portion of the imaging apparatus has, the included in the first substrate, comprising a photoelectric conversion element, and a pixel for generating the pixel signal, the second of the picture No. Motoshin A signal line supplied to the substrate, a signal storage circuit included in the second substrate and storing the pixel signal supplied via the signal line, and a signal storage circuit included in the second substrate. an output circuit for outputting the pixel signals stored in the circuit, included in the second substrate, the voltage of the pixel No. signal has and a clipping circuit which clips so as not fall below a predetermined voltage.

Further, the solid-state imaging equipment in accordance with aspects of the present invention, the connecting portion for electrically connecting the first substrate and the second substrate, electrically and said second substrate and said first substrate The pixel unit included in the solid-state imaging device is included in the first substrate, includes a pixel including a photoelectric conversion element, and a first signal line connected to the pixel. , A transistor included in the second substrate and having one end connected to the first signal line, a capacitor included in the second substrate and connected to the first signal line, and the capacitor And the transistor clips so that the voltage of the first signal line does not become a predetermined voltage or less.

According to another aspect of the present invention, there is provided a method for controlling a solid-state imaging device, wherein the first substrate and the second substrate are connected by a connection unit that electrically connects the first substrate and the second substrate. A method for controlling an electrically connected solid-state imaging device, wherein a signal generated in a pixel including a photoelectric conversion element included in the first substrate of a pixel portion included in the solid-state imaging device is connected to the pixel And outputting to the first signal line, and storing the signal output to the first signal line in a capacitor included in the second substrate and connected to the first signal line. And a step of outputting a signal accumulated in a second signal line connected to the capacitor, the transistor being included in the second substrate and having one end connected to the first signal line The voltage of the first signal line is equal to or lower than a predetermined voltage The step of clipping so as not, further comprising.

An imaging device according to an aspect of the present invention electrically connects the first substrate and the second substrate by a connection unit that electrically connects the first substrate and the second substrate. The pixel unit included in the imaging device is included in the first substrate and includes a pixel including a photoelectric conversion element, a first signal line connected to the pixel, and the second One end of which is connected to the first signal line , one end of which is connected to the first signal line, and one end of the transistor connected to the first signal line. A second signal line, and the transistor clips so that a voltage of the first signal line does not become a predetermined voltage or less.

1 is a block diagram showing a schematic configuration of a digital camera according to an embodiment of the present invention. 1 is an overview diagram illustrating a schematic configuration of an image sensor according to an embodiment. It is a circuit diagram showing a schematic configuration of a pixel chip in the image sensor of the present embodiment. It is the circuit diagram which showed schematic structure of the pixel signal processing chip in the image sensor of this embodiment. It is a circuit diagram showing a schematic configuration of a unit pixel in a pixel chip provided in the image sensor of the present embodiment. It is the circuit diagram which showed schematic structure of the unit pixel memory in the pixel signal processing chip with which the image sensor of this embodiment was equipped. It is a timing chart showing the timing of each drive when high brightness light is not incident on the image sensor of the present embodiment. 6 is a timing chart showing the timing of each drive when high-luminance light is incident during the reset period of the image sensor of the present embodiment. It is a figure explaining the effect when high-intensity light injects during the reset period of the image sensor of this embodiment. 6 is a timing chart showing the timing of each drive when high-luminance light is incident during the transfer period of the image sensor of the present embodiment. It is a figure explaining the effect when high-intensity light injects during the transfer period of the image sensor of this embodiment. It is the circuit diagram which showed an example of schematic structure of the unit pixel memory in the pixel signal processing chip relevant to suppression of the horizontal stripe phenomenon by the high-intensity light in the image sensor of this embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following description includes specific details for illustrative purposes. However, those skilled in the art will understand that even if various modifications are made to the detailed contents described below, the scope of the present invention is not exceeded. Accordingly, the exemplary embodiments of the invention described below are set forth without loss of generality or limitation to the claimed invention. .

  FIG. 1 is a block diagram illustrating a schematic configuration of a digital camera (for example, a single-lens reflex digital camera) according to the present embodiment. Each component shown here can be realized in terms of hardware by elements such as a CPU and a memory of a computer, and in terms of software, it can be realized by a computer program. These are shown as functional blocks realized by these linkages. Therefore, those skilled in the art will understand that these functional blocks can be realized in various forms by a combination of hardware and software.

  A digital camera 1 shown in FIG. 1 includes a lens unit 2, an image sensor 3, a light emitting device 4, a memory 5, a recording device 6, a display device 7, an image signal processing circuit 8, a lens control device 9, and an image sensor control device 10. , A light emission control device 11 and a camera control device 12. The digital camera 1 shown in FIG. 1 is a digital camera that does not have a mechanical shutter for shielding the image sensor 3 and performs global exposure that exposes all pixels simultaneously.

The lens unit 2 is driven and controlled by the lens control device 9 such as zoom, focus, and diaphragm, and forms a subject image on the image sensor 3.
The image sensor 3 is a MOS solid-state imaging device that is driven and controlled by the image sensor control device 10 and converts subject light incident on the image sensor 3 through the lens unit 2 into an image signal. In the following description, an image sensor refers to a MOS type solid-state imaging device. A detailed description of the image sensor 3 will be described later.
The light-emitting device 4 is a device such as a strobe or a flash that is driven and controlled by the light-emission control device 11 and adjusts the light reflected from the subject by applying the light emitted from the light-emitting device 4 to the subject.

The image signal processing circuit 8 performs processing such as signal amplification, conversion to image data, various corrections, and image data compression on the image signal output from the image sensor 3. The image signal processing circuit 8 uses the memory 5 as temporary storage means for image data in each process.
The recording device 6 is a detachable recording medium such as a semiconductor memory, and records or reads image data.
The display device 7 is a display device such as a liquid crystal that displays an image based on the image data imaged on the image sensor 3 and processed by the image signal processing circuit 8 or the image data read from the recording device 6.

  The camera control device 12 is a control device that performs overall control of the digital camera 1. In addition, the camera control device 12 controls the image sensor control device 10 and the light emission control device 11 to cooperatively control the image sensor 3 and the light emission device 4.

  Next, the image sensor 3 of this embodiment will be described. FIG. 2 is an overview diagram showing a schematic configuration of the image sensor 3 according to the present embodiment. In FIG. 2, the image sensor 3 includes a pixel chip 31, a pixel signal processing chip 32, a chip connection unit 33, and an external wiring connection unit 34.

The pixel chip 31 is a chip in which pixels including a photoelectric conversion unit, which will be described later, are two-dimensionally arranged and converts incident subject light into an electrical signal. The pixel chip 31 is driven and controlled by a signal transmitted from the pixel signal processing chip 32. Then, the pixel chip 31 transmits the converted electric signal to the pixel signal processing chip 32.
The pixel signal processing chip 32 is a chip that performs temporary storage of the electrical signal transmitted from the pixel chip 31 and processing such as simple calculation on the electrical signal. The pixel signal processing chip 32 transmits a signal for driving and controlling the pixel chip 31 to the pixel chip 31.

  The chip connection unit 33 is a connection unit for electrically connecting the pixel chip 31 and the pixel signal processing chip 32. For the chip connection portion 33, for example, bumps produced by vapor deposition or plating are used. Note that the space existing between the pixel chip 31 and the pixel signal processing chip 32 may be filled with an insulating member such as an adhesive. The pixel chip 31 and the pixel signal processing chip 32 transmit and receive signals via the chip connection unit 33.

  The external wiring connection part 34 is a connection part for electrically connecting the image sensor 3 and another block. The input / output signals of the image sensor 3 are transmitted / received to / from other components (blocks) in the digital camera 1 via the external wiring connection unit 34. For example, a configuration in which a package (not shown) for protecting the image sensor 3 and the external wiring connection portion 34 are connected by a wire and input / output signals of the image sensor 3 are transmitted / received outside the package is conceivable.

  In the image sensor 3 of the present embodiment, global exposure for simultaneously exposing all the pixels in the pixel chip 31 is performed, and an electrical signal obtained by converting incident subject light is transmitted to the pixel signal processing chip 32. The pixel signal processing chip 32 temporarily stores the electrical signal transmitted from the pixel chip 31 and sequentially outputs the electrical signal from the external wiring connection unit 34 to the outside of the image sensor 3.

  Next, the pixel chip 31 of this embodiment will be described. FIG. 3 is a circuit diagram showing a schematic configuration of the pixel chip 31 in the image sensor 3 of the present embodiment. In FIG. 3, a pixel chip 31 includes a pixel chip vertical scanning circuit 311, a pixel array unit 312, a unit pixel 313, a pixel signal line 314, a pixel chip vertical scanning circuit signal line 315, a pixel reset line 316, a pixel transfer line 317, a pixel. It consists of a selection line 318. In the pixel chip 31 illustrated in FIG. 3, an example of a pixel array unit 312 in which a plurality of unit pixels 313 are two-dimensionally arranged in 10 rows and 10 columns is illustrated. With the configuration of the pixel chip 31, an operation is performed at a readout timing described later.

  In the pixel chip 31 shown in FIG. 3, the numbers and symbols in “(): parentheses” shown after each symbol are a row number and a column number corresponding to the unit pixel 313 arranged in the pixel chip 31. Represents. The first number in “(): brackets” indicates the row number, and the last number indicates the column number. For example, the unit pixel 313 in the second row and the third column is represented as a unit pixel 313 (2, 3). In addition, when only one of the row number or column number, that is, the same row number or column number is represented, the same row number or column number is represented by a number, and the non-identical row number or column number is designated as “ *: Represented by an asterisk. For example, the pixel reset line 316 in the third row is represented as a pixel reset line 316 (3, *). Further, when both the row number and the column number are not specified, “(): parenthesis” after each code is not written.

  The pixel chip vertical scanning circuit 311 controls each unit pixel 313 in the pixel array unit 312 and outputs a pixel signal of each unit pixel 313 to the pixel signal line 314. The pixel chip vertical scanning circuit 311 includes a control signal line (a pixel reset line 316, a pixel transfer line 317, a pixel selection line 318) and a control signal for controlling the unit pixel 313 that is a unit arranged in the pixel array unit 312. Output for each row of pixels 313.

Each unit pixel 313 in the pixel array unit 312 outputs a reset signal when reset and an electric signal corresponding to the amount of received light of the subject light to the pixel signal line 314 as a pixel signal.
The pixel signal line 314 and the pixel chip vertical scanning circuit signal line 315 are connected to the pixel signal processing chip 32 via the chip connection unit 33. The pixel chip 31 and the pixel signal processing chip 32 include various signals necessary for driving and controlling the pixel chip 31 and each unit pixel in the pixel chip 31 through the pixel signal line 314 and the pixel chip vertical scanning circuit signal line 315. The pixel signal output from 313 is transmitted and received.

  Next, the pixel signal processing chip 32 of this embodiment will be described. FIG. 4 is a circuit diagram showing a schematic configuration of the pixel signal processing chip 32 in the image sensor 3 of the present embodiment. In FIG. 4, a pixel signal processing chip 32 includes a pixel signal processing chip vertical scanning circuit 321, a pixel memory array unit 322, a unit pixel memory 323, a pixel memory signal line 324, a pixel signal processing chip vertical signal line 325, and a pixel signal processing chip. Column processing circuit 326, pixel signal processing chip horizontal scanning circuit 327, pixel signal processing chip horizontal scanning circuit signal line 328, image sensor control circuit 329, image sensor control circuit signal line 3210, pixel memory reset line 3211, pixel memory transfer line 3212 , A pixel memory selection line 3213, a clip reference line 3214, and a clip enable line 3215. In the pixel signal processing chip 32 illustrated in FIG. 4, an example of a pixel memory array unit 322 in which a plurality of unit pixel memories 323 are two-dimensionally arranged in 10 rows and 10 columns is illustrated. With the configuration of the pixel signal processing chip 32, an operation at a readout timing described later is performed.

  In the pixel signal processing chip 32 shown in FIG. 4, numbers and symbols in “(): parentheses” shown after each symbol correspond to the unit pixel memory 323 arranged in the pixel signal processing chip 32. The row number and the column number are represented, and the way of representing them is the same as that of the pixel chip 31 shown in FIG.

  The pixel signal processing chip vertical scanning circuit 321 controls each unit pixel memory 323 in the pixel memory array unit 322 and outputs a pixel memory signal of each unit pixel memory 323 to the pixel signal processing chip vertical signal line 325. The pixel signal processing chip vertical scanning circuit 321 controls the unit pixel memory 323 to control signal lines (pixel memory reset line 3211, pixel memory transfer line 3212, pixel memory selection line 3213, clip reference line 3214, clip enable line 3215). A control signal for output is output for each row of the unit pixel memory 323 arranged in the pixel memory array unit 322.

  Each unit pixel memory 323 in the pixel memory array unit 322 is transmitted from each unit pixel 313 in the pixel array unit 312 provided in the pixel chip 31 to the pixel memory signal line 324 through the chip connection unit 33. A pixel signal is input. Each unit pixel memory 323 outputs an electrical signal corresponding to the input pixel signal to the pixel signal processing chip vertical signal line 325 as a pixel memory signal.

  The pixel signal processing chip column processing circuit 326 performs processing on the pixel memory signal transmitted from the unit pixel memory 323. In the processing on the pixel memory signal by the pixel signal processing chip column processing circuit 326, signal subtraction (difference processing) described later is performed based on the clamp pulse ΦCL and the sample hold pulse ΦSH input from the image sensor control circuit 329. Further, processing by the pixel signal processing chip column processing circuit 326 includes processing such as signal amplification and comparison. The pixel signal processing chip column processing circuit 326 includes a current source load connected to the pixel signal processing chip vertical signal line 325.

The pixel signal processing chip horizontal scanning circuit 327 sequentially reads out the processed signals output from the pixel signal processing chip column processing circuit 326 based on the horizontal scanning pulse ΦH input from the image sensor control circuit 329.
The image sensor control circuit 329 controls the pixel signal processing chip vertical scanning circuit 321, the pixel signal processing chip column processing circuit 326, the pixel signal processing chip horizontal scanning circuit 327, and the pixel chip vertical scanning circuit 311 in the pixel chip 31.

  The pixel memory signal line 324 and the image sensor control circuit signal line 3210 are connected to the pixel chip 31 via the chip connection unit 33. The pixel chip 31 and the pixel signal processing chip 32 include various signals necessary for driving and controlling the pixel chip 31 and each unit pixel in the pixel chip 31 through the pixel memory signal line 324 and the image sensor control circuit signal line 3210. The pixel signal output from 313 is transmitted and received.

  The image sensor 3 is controlled by the image sensor control circuit 329, the pixel signal processing chip vertical scanning circuit 321, the pixel signal processing chip column processing circuit 326, the pixel signal processing chip horizontal scanning circuit 327, and the pixel chip vertical scanning circuit 311. An image signal of incident subject light is output.

Next, the unit pixel 313 of this embodiment will be described. Figure 5 is a circuit diagram showing a schematic configuration of a unit of a pixel 313 in the pixel chip 31 having the image sensor 3 of this embodiment. The unit pixel 313 is a circuit that converts incident light into an electrical signal and outputs it to the pixel signal line 314. Each unit pixel 313 includes a photodiode PD, a pixel charge storage unit FD, a pixel transfer transistor PM1, a pixel reset transistor PM2, a pixel amplification transistor PM3, and a pixel selection transistor PM4.

  The pixel charge storage unit FD is a capacitor associated with a node connected to the gate terminal of the pixel amplification transistor PM3, and is indicated by a capacitor symbol in the schematic configuration of the unit pixel 313 shown in FIG. The schematic configuration of the unit pixel 313 shown in FIG. 5 is the same as the unit pixel of the conventional image sensor.

  The photodiode PD is a photoelectric conversion unit that photoelectrically converts incident light to generate signal charges. The pixel charge accumulation unit FD is a capacitor that accumulates signal charges. Based on the pixel transfer pulse ΦPT input from the pixel chip vertical scanning circuit 311, the pixel transfer transistor PM1 converts the signal charge generated by the photodiode PD into a pixel charge storage unit FD connected to the gate terminal of the pixel amplification transistor PM3. Forward to. The signal charge transferred by the pixel transfer transistor PM1 is accumulated in the pixel charge accumulation unit FD. The pixel amplification transistor PM3 outputs a voltage corresponding to the signal charge accumulated in the pixel charge accumulation unit FD. The pixel reset transistor PM2 resets the pixel charge accumulation unit FD to the power supply potential VDDP based on the pixel reset pulse ΦPR input from the pixel chip vertical scanning circuit 311. Based on the pixel selection pulse ΦPS input from the pixel chip vertical scanning circuit 311, the pixel selection transistor PM 4 outputs the voltage output from the pixel amplification transistor PM 3 to the pixel signal line 314 as the output of the unit pixel 313. The pixel signal line 314 is connected to the chip connection unit 33.

  Next, the unit pixel memory 323 of this embodiment will be described. FIG. 6 is a circuit diagram showing a schematic configuration of the unit pixel memory 323 in the pixel signal processing chip 32 provided in the image sensor 3 of the present embodiment. The unit pixel memory 323 is a circuit that holds a signal input from the pixel memory signal line 324 and outputs the signal to the pixel signal processing chip vertical signal line 325. The unit pixel memory 323 includes a pixel memory coupling capacitor CC, a pixel memory charge storage unit MC, a pixel memory transfer transistor MM1, a pixel memory reset transistor MM2, a pixel memory amplification transistor MM3, a pixel memory selection transistor MM4, and a pixel memory clip reference transistor. MM5, pixel memory clip enable transistor MM6, and pixel memory current load CS.

  The pixel memory charge storage portion MC is a capacitance associated with a node connected to the gate terminal of the pixel memory amplification transistor MM3, and is indicated by a capacitor symbol in the schematic configuration of the unit pixel memory 323 shown in FIG.

  One of the pixel memory coupling capacitors CC is a coupling capacitor connected to the chip connection unit 33 and the other connected to the source terminal of the pixel memory transfer transistor MM1. The pixel memory charge storage unit MC is a capacitive load that stores signal charges. The pixel memory transfer transistor MM1 converts a signal charge generated in one of the pixel memory coupling capacitors CC based on the pixel memory transfer pulse ΦMT input from the pixel signal processing chip vertical scanning circuit 321 to the gate terminal of the pixel memory amplification transistor MM3. Is transferred to the pixel memory charge storage portion MC connected to. The signal charge transferred by the pixel memory transfer transistor MM1 is accumulated in the pixel memory charge accumulation unit MC. The pixel memory amplification transistor MM3 outputs a voltage corresponding to the signal charge accumulated in the pixel memory charge accumulation unit MC. The pixel memory reset transistor MM2 resets the pixel memory charge accumulation unit MC to the power supply potential VDDM based on the pixel memory reset pulse ΦMR input from the pixel signal processing chip vertical scanning circuit 321. The pixel memory selection transistor MM4 uses the voltage output from the pixel memory amplification transistor MM3 based on the pixel memory selection pulse ΦMS input from the pixel signal processing chip vertical scanning circuit 321 as the output of the unit pixel memory 323, and the pixel signal processing chip. Output to the vertical signal line 325.

  The pixel memory clip reference transistor MM5 is connected to the pixel memory signal line 324, and limits the voltage of the pixel memory signal line 324 based on the potential of the pixel memory clip reference pulse ΦCR input from the pixel signal processing chip vertical scanning circuit 321. To do. The pixel memory clip enable transistor MM6 is connected to the pixel memory clip reference transistor MM5, and limits the voltage of the pixel memory signal line 324 based on the pixel memory clip enable pulse ΦCE input from the pixel signal processing chip vertical scanning circuit 321. Whether the function of the pixel memory clip reference transistor MM5 is valid or invalid is determined. The pixel memory clip reference transistor MM5 and the pixel memory clip enable transistor MM6 suppress the black sun phenomenon and the horizontal stripe phenomenon caused by the pixels to which the high luminance light is incident.

  One of the pixel memory current loads CS is connected to the pixel memory signal line 324, and the other is connected to the ground of the pixel signal processing chip 32. The pixel memory current load CS drives the signal line connected to the chip connection unit 33 with a constant current. The pixel memory signal line 324 is connected to the chip connection unit 33. The pixel memory current load CS may be configured such that one is connected to the pixel signal line 314 of the pixel chip 31 and the other is connected to the ground of the pixel chip 31.

  In the image sensor 3 of the present embodiment, global exposure is performed in which all the unit pixels 313 in the pixel chip 31 are exposed at the same time, and a pixel signal based on a signal charge generated according to subject light incident on the photodiode PD is obtained. The data is output to the pixel signal processing chip 32 via the chip connection unit 33. The pixel signal processing chip 32 temporarily stores the pixel signal input from the pixel chip 31, performs processing such as difference processing, and sequentially outputs the processed signals. 2 to 4, the image sensor 3 includes each unit pixel 313 in the pixel array unit 312 and each unit pixel memory 323 in the pixel memory array unit 322. Are connected via the chip connecting portion 33. That is, it is a structure provided with the chip | tip connection part for every pixel. However, the configuration of the image sensor 3 is not limited to the configuration of the image sensor 3 illustrated in FIGS. 2 to 4, and a configuration in which a chip connection unit is provided for each predetermined number of pixels may be employed. . In this case, after all the pixels in the pixel chip simultaneously perform global exposure, the pixels sharing the chip connection unit sequentially output pixel signals.

<Normal timing>
Next, the drive timing of the image sensor 3 of this embodiment will be described. In the timing chart shown below, the timing when the unit pixels 313 and the unit pixel memory 323 for two rows are continuously processed in the configuration of the image sensor 3 shown in FIGS. 2 to 4 is shown. In actual operation, the number of unit pixels 313 and unit pixel memory 323 rows that are continuously processed, the unit pixels 313, and the unit pixels, depending on parameters of the image sensor 3, such as the number of pixels and the thinning rate in thinning readout, for example. The number of thinning out lines of the memory 323 changes. The control pulses (pixel reset pulse ΦPR, pixel transfer pulse ΦPT, pixel selection pulse ΦPS, pixel memory reset pulse ΦMR, pixel memory transfer pulse output from the pixel chip vertical scanning circuit 311 and the pixel signal processing chip vertical scanning circuit 321 are also shown. The timing of ΦMT, pixel memory selection pulse ΦMS, pixel memory clip reference pulse ΦCR, and pixel memory clip enable pulse ΦCE) can be changed according to the driving method.

  In the timing chart shown below, only the control pulse in the first row is shown for ease of explanation. In the configuration of the image sensor 3 of the present embodiment shown in FIGS. 2 to 4, each of the unit pixels 313 in the pixel array unit 312 and each of the unit pixel memories 323 in the pixel memory array unit 322 are respectively They are connected via the respective chip connection portions 33. For this reason, for example, when the digital camera 1 performs global exposure in which all pixels are exposed simultaneously, control pulses from time t1 to time t5 described later are applied to all rows of the pixel array unit 312 and the pixel memory array unit 322. By outputting, all lines are controlled simultaneously. Therefore, in the following description, regarding the operations common to all the rows, “(): parentheses” after each symbol is not written, and only “(): The parentheses are indicated.

In the timing chart shown below, the PD potential V _PD indicates the potential due to the signal charge generated by the photodiode PD. The FD potential V _FD indicates the potential of the pixel charge accumulation unit FD. The pixel signal line potential V ₃₁₄ indicates the potential of the pixel signal line 314. Since the pixel signal line 314 of each unit pixel 313 is connected to the pixel memory signal line 324 of each unit pixel memory 323 via the chip connection unit 33, the pixel signal line potential V ₃₁₄ is the pixel memory signal line. It is also the potential of 324. The pixel memory potential _VMC indicates the potential of the pixel memory charge storage unit MC. The power supply potential VDDP and the power supply potential VDDM indicate the power supply potentials of the pixel chip 31 and the pixel signal processing chip 32, respectively. The FD reset potential _VFDRS indicates the reset potential of the pixel charge accumulation unit FD. The FD signal potential V _FDSIG indicates a signal potential depending on the subject in the pixel charge accumulation unit FD. The pixel signal line reset potential V _314RS indicates the reset potential of the pixel signal line 314. The pixel signal line signal potential V 314 _SIG indicates a signal potential depending on the subject in the pixel signal line 314. The first reference potential VREF1 and the second reference potential VREF2 respectively indicate potentials used for suppressing a black sun phenomenon and a horizontal stripe phenomenon due to high-intensity light described later. The pixel memory reset potential V _MCRS indicates a reset potential of the pixel memory charge accumulation unit MC. The pixel memory signal potential V _MCSIG indicates a signal potential depending on the subject in the pixel memory charge accumulation unit MC.

  First, the drive timing when high-luminance light is not incident on the image sensor 3, that is, when normal level subject light is incident on the image sensor 3, will be described. FIG. 7 is a timing chart showing the timing of each drive when high-luminance light is not incident on the image sensor 3 of the present embodiment.

At time t1, the pixel chip vertical scanning circuit 311 sets the pixel reset pulse ΦPR to “High” level, thereby turning on the pixel reset transistor PM2 of the unit pixel 313 in the pixel array unit 312. As a result, the pixel charge storage portion FD of the unit pixel 313 in the pixel array portion 312 is reset, and the FD potential V _FD becomes the potential of the power supply potential VDDP. Further, the pixel chip vertical scanning circuit 311 sets the pixel selection transistor PM4 of the unit pixel 313 in the pixel array unit 312 to the ON state by setting the pixel selection pulse ΦPS to the “High” level. Accordingly, the pixel signal line potential V ₃₁₄ is reset to a potential in the vicinity of the power supply potential VDDP corresponding to the FD potential V _FD .

At time t1, the pixel signal processing chip vertical scanning circuit 321 sets the pixel memory clip reference pulse ΦCR to the level of the first reference potential VREF1, so that the voltage range of the pixel memory signal line 324, that is, the pixel signal line potential. The voltage range of V ₃₁₄ is limited to a potential corresponding to the first reference potential VREF1. In addition, the pixel signal processing chip vertical scanning circuit 321 sets the pixel memory clip enable pulse ΦCE to “High” level, thereby turning on the pixel memory clip enable transistor MM6 of the unit pixel memory 323 in the pixel memory array unit 322. To do. As a result, the clipping function of the pixel memory signal line 324 according to the level of the pixel memory clip reference pulse ΦCR, that is, the pixel signal line potential V ₃₁₄ is validated.

At time t1, the pixel signal processing chip vertical scanning circuit 321 turns on the pixel memory transfer transistor MM1 of the unit pixel memory 323 in the pixel memory array unit 322 by setting the pixel memory transfer pulse ΦMT to the “High” level. Put it in a state. Accordingly, the path from the pixel charge storage unit FD of the unit pixel 313 in the pixel array unit 312 to the pixel memory charge storage unit MC of the unit pixel memory 323 in the pixel memory array unit 322 is made conductive. In addition, the pixel signal processing chip vertical scanning circuit 321 turns the pixel memory reset transistor MM2 of the unit pixel memory 323 in the pixel memory array unit 322 into the ON state by setting the pixel memory reset pulse ΦMR to the “High” level. This will reset the pixel memory charge storage portion MC of the unit pixel memory 323 in the pixel memory array portion 322, the pixel memory potential V _MC is the potential of the power supply potential VDDM.

Subsequently, at time t2, the pixel chip vertical scanning circuit 311 sets the pixel reset pulse ΦPR to the “Low” level, thereby turning off the pixel reset transistor PM2 of the unit pixel 313 in the pixel array unit 312 and the FD potential. to end the reset operation to the potential of the power supply potential VDDP of V _FD. Then, a period for stabilizing the FD potential V _FD and the pixel signal line potential V ₃₁₄ at the reset potential (a period until time t3 in FIG. 7) is started. During the period during which the reset potential is stabilized, the potentials of the FD potential V _FD and the pixel signal line potential V ₃₁₄ are decreased by the reset noise of the unit pixel 313. The FD potential V _FD is _{stabilized at} the potential of the FD reset potential V _FDRS , and the pixel signal line potential V ₃₁₄ is stabilized at the potential of the pixel signal line reset potential V _314RS . Note that the FD reset potential _VFDRS and the pixel signal line reset potential _V314RS are potentials that are lower than the power supply potential VDDP by the amount of noise generated in the unit pixel 313.

Subsequently, at time t3, the pixel chip vertical scanning circuit 311 sets the pixel transfer pulse ΦPT to the “High” level, thereby turning on the pixel transfer transistor PM1 of the unit pixel 313 in the pixel array unit 312, and the photodiode. The signal charge generated by the PD is transferred to the pixel charge storage unit FD. Thereby, the FD potential V _FD becomes a potential corresponding to the PD potential V _PD at the time t3. At this time, since the pixel selection pulse ΦPS is at the “High” level, the potential of the pixel signal line potential V ₃₁₄ also drops by an amount corresponding to the signal charge transferred to the pixel charge storage portion FD.

At time t3, the pixel signal processing chip vertical scanning circuit 321 sets the pixel memory clip reference pulse ΦCR to the level of the second reference potential VREF2, so that the voltage range of the pixel memory signal line 324, that is, the pixel signal line potential. The voltage range of V ₃₁₄ is limited to a potential corresponding to the second reference potential VREF2.

At time t3, the pixel signal processing chip vertical scanning circuit 321 turns off the pixel memory reset transistor MM2 of the unit pixel memory 323 in the pixel memory array unit 322 by setting the pixel memory reset pulse ΦMR to the “Low” level. the state to end the reset operation to the power supply potential VDDM of the pixel memory potential _{V MC.} Thus, the pixel memory potential V _MC will potential corresponding to the pixel signal line potential V ₃₁₄ was lowered in accordance with the transfer to the pixel charge storage portion FD of the signal charges by the photodiode PD has occurred.

Subsequently, at time t4, the pixel chip vertical scanning circuit 311 sets the pixel transfer pulse ΦPT to the “Low” level, thereby turning off the pixel transfer transistor PM1 of the unit pixel 313 in the pixel array unit 312, and the photodiode. The transfer operation of the signal charge generated by the PD to the pixel charge accumulation unit FD is finished. Then, a period for stabilizing the FD potential V _FD and the pixel signal line potential V ₃₁₄ to the signal potential (period until time t5 in FIG. 7) is started. During the period during which the signal potential is stabilized, the potentials of the FD potential V _FD and the pixel signal line potential V ₃₁₄ are lowered due to the influence when the pixel transfer transistor PM1 is turned off. The FD potential V _FD is _{stabilized at} the potential of the FD signal potential V _FDSIG and the pixel signal line potential V ₃₁₄ is stabilized at the potential of the pixel signal line signal potential V _314SIG . Note that the FD signal potential V _FDSIG and the pixel signal line signal potential V _314SIG are potentials that depend on parasitic capacitance or the like due to the transmission path of each signal.

At this time, since the pixel selection pulse ΦPS and the pixel memory transfer pulse ΦMT are at “High” level, the unit pixel in the pixel memory array unit 322 is changed from the pixel charge storage unit FD of the unit pixel 313 in the pixel array unit 312. The path to the pixel memory charge storage portion MC of the memory 323 is conductive. Therefore, during the period during which the signal potential is stabilized (the period up to time t5 in FIG. 7), the pixel memory potential _VMC is also a potential corresponding to the pixel signal line potential _V314 that has dropped depending on the parasitic capacitance due to the transmission path. Go down. The pixel memory potential _{V MC} is stabilized to the potential of the pixel memory signal potential _{V MCSIG.}

Subsequently, at time t5, the pixel chip vertical scanning circuit 311 sets the pixel selection pulse ΦPS to the “Low” level, thereby turning off the pixel selection transistor PM4 of the unit pixel 313 in the pixel array unit 312. Accordingly, the pixel signal line potential V ₃₁₄ becomes a potential independent of the FD potential V _FD .

  At time t5, the pixel signal processing chip vertical scanning circuit 321 turns off the pixel memory transfer transistor MM1 of the unit pixel memory 323 in the pixel memory array unit 322 by setting the pixel memory transfer pulse ΦMT to the “Low” level. Put it in a state. As a result, the conduction of the path from the pixel charge storage unit FD of the unit pixel 313 in the pixel array unit 312 to the pixel memory charge storage unit MC of the unit pixel memory 323 in the pixel memory array unit 322 is terminated, that is, the path is Cut off.

In addition, the pixel signal processing chip vertical scanning circuit 321 sets the pixel memory selection pulse ΦMS (1, *) to “High” level, so that the pixel memory of the unit pixel memory 323 in the first row in the pixel memory array unit 322 is obtained. The selection transistor MM4 is turned on. As a result, the unit pixel memory 323 of the first row in the pixel memory array unit 322 is selected, and the pixel memory potential V _MC , that is, the pixel signal processing chip vertical signal line 325 of the selected unit pixel memory 323 of the first row is selected. A pixel memory signal having a voltage corresponding to the pixel memory signal potential _VMCSIG is output. Here, it is assumed that the pixel memory signal potential _VMCSIG is output as a pixel memory signal to the pixel signal processing chip vertical signal line 325.

At time t5, the image sensor control circuit 329 sets the clamp pulse ΦCL and the sample hold pulse ΦSH to the “High” level, thereby causing the pixel signal processing chip column processing circuit 326 to transfer from the unit pixel memory 323 in the first row. Preparation for holding the transmitted pixel memory signal potential _VMCSIG is performed.

Subsequently, at time t <b> 6, the image sensor control circuit 329 sets the clamp pulse ΦCL to the “Low” level, whereby the pixel signal transmitted from the unit pixel memory 323 in the first row to the pixel signal processing chip column processing circuit 326. The memory signal potential V _MCSIG is clamped (held).

  At time t6, the pixel signal processing chip vertical scanning circuit 321 sets the pixel memory clip enable pulse ΦCE to the “Low” level, so that the pixel memory clip enable transistor MM6 of the unit pixel memory 323 in the pixel memory array unit 322 is set. Is turned off, and the clipping function of the potential of the pixel memory signal line 324 according to the level of the pixel memory clip reference pulse ΦCR is invalidated.

At time t6, the pixel signal processing chip vertical scanning circuit 321 sets the pixel memory reset pulse ΦMR (1, *) to the “High” level, so that the unit pixel memory in the first row in the pixel memory array unit 322 is set. reset the 323 pixel memory charge storage portion MC of the potential of the power supply potential VDDM pixel memory potential _{V MC,} that is, the pixel memory reset potential _{V MCRS.} The pixel memory reset potential V _MCRS is output to the pixel signal processing chip vertical signal line 325 as a pixel memory signal.

Subsequently, at time t7, the image sensor control circuit 329 transmits the sample hold pulse ΦSH to the pixel signal processing chip column processing circuit 326 from the unit pixel memory 323 in the first row by setting the sample hold pulse ΦSH to the “Low” level. The pixel memory reset potential V _MCRS is sampled. As a result, the pixel signal processing chip column processing circuit 326 _performs difference processing between the pixel memory signal potential V _MCSIG clamped at time t6 and the pixel memory reset potential V _MCRS sampled at time t7, and noise is removed. A pixel memory signal of the unit pixel memory 323 in the first row can be obtained. Then, the image sensor control circuit 329 repeatedly inputs the “High” level and the “Low” level of the horizontal scanning pulse ΦH to the pixel signal processing chip horizontal scanning circuit 327 until time t8, thereby the pixel memory array unit 322. The pixel memory signals after noise removal of each column of the unit pixel memory 323 in the first row are sequentially read out from the pixel signal processing chip horizontal scanning circuit signal line 328.

Further, at time t7, the pixel signal processing chip vertical scanning circuit 321, the pixel memory reset pulse ΦMR (1, *) to "Low" level, the reset state of the pixel memory reset potential _{V MCRS} pixel memory potential _{V MC} Open. In addition, the pixel signal processing chip vertical scanning circuit 321 sets the pixel memory selection pulse ΦMS (1, *) to the “Low” level, so that the pixel memory of the unit pixel memory 323 in the first row in the pixel memory array section 322 is obtained. The selection transistor MM4 is turned off, and the selection of the unit pixel memory 323 in the first row is released. Thereby, the output of the pixel memory signal to the pixel signal processing chip vertical signal line 325 is stopped.

Subsequently, at time t8, the pixel signal processing chip vertical scanning circuit 321 sets the pixel memory selection pulse ΦMS (2, *) to the “High” level, and the unit pixel memory 323 in the second row in the pixel memory array unit 322. _And a pixel memory signal having a voltage corresponding to the pixel memory signal potential V _MCSIG of the unit pixel memory 323 in the second row is output to the pixel signal processing chip vertical signal line 325.

At time t8, the image sensor control circuit 329 sets the clamp pulse ΦCL and the sample hold pulse ΦSH to the “High” level, and is transmitted from the unit pixel memory 323 in the second row to the pixel signal processing chip column processing circuit 326. Preparation for holding the pixel memory signal (pixel memory signal potential V _MCSIG ) is performed.

Subsequently, at time t9, the image sensor control circuit 329 sets the clamp pulse ΦCL to the “Low” level, and the pixel memory signal transmitted from the unit pixel memory 323 in the second row to the pixel signal processing chip column processing circuit 326. The potential V _MCSIG is clamped (held).

At time t <b> 9, the pixel signal processing chip vertical scanning circuit 321 sets the pixel memory reset pulse ΦMR (2, *) to “High” level, and the unit pixel memory 323 in the second row in the pixel memory array unit 322. A pixel memory signal having a voltage corresponding to the pixel memory reset potential V _MCRS is output to the pixel signal processing chip vertical signal line 325.

Subsequently, at time t10, the image sensor control circuit 329 sets the sample hold pulse ΦSH to the “Low” level, and the pixel memory transmitted from the unit pixel memory 323 in the second row to the pixel signal processing chip column processing circuit 326. The reset potential V _MCRS is sampled. Accordingly, the pixel memory signal of the unit pixel memory 323 in the second row from which noise has been removed can be obtained from the pixel signal processing chip column processing circuit 326. Then, after time t10, the image sensor control circuit 329 inputs the horizontal scanning pulse ΦH in which the “High” level and the “Low” level are repeated, to the pixel signal processing chip horizontal scanning circuit 327, and the pixel memory array unit 322 The pixel memory signals after noise removal in each column of the unit pixel memory 323 in the second row are sequentially read out from the pixel signal processing chip horizontal scanning circuit signal line 328.

At time t10, the pixel signal processing chip vertical scanning circuit 321 sets the pixel memory reset pulse ΦMR (2, *) to the “Low” level to reset the pixel memory potential V _{MC to} the pixel memory reset potential V _MCRS . , The pixel memory selection pulse ΦMS (2, *) is set to the “Low” level, the selection of the unit pixel memory 323 in the second row is canceled, and the pixel memory signal to the pixel signal processing chip vertical signal line 325 is released. Output stops.

  Thereafter, by controlling in the same manner as at time t5 to time t8, the pixel memory signals after noise removal are sequentially applied to the pixel signal processing chip horizontal scanning circuit signal line 328 from the unit pixel memories 323 in all rows after the third row. read out. In this manner, the image sensor 3 can output an image signal obtained by performing noise removal processing on the pixel signal corresponding to the incident subject light.

<Suppression timing of black sun phenomenon>
Next, drive timing when high-luminance light is incident during the reset period of the image sensor 3 will be described. FIG. 8 is a timing chart showing the timing of each drive when high-luminance light is incident during the reset period of the image sensor 3 of the present embodiment. FIG. 9 is a diagram for explaining the effect when high-luminance light is incident during the reset period of the image sensor 3 of the present embodiment.

  Normally, in a MOS type solid-state imaging device, a black sun phenomenon occurs when high-luminance light is incident during a reset period. In the image sensor 3 of the present embodiment, as described above, the pixel memory clip reference transistor MM5 and the pixel memory clip enable transistor MM6 suppress the black sun phenomenon caused by the pixels on which high-intensity light is incident. In the timing chart shown in FIG. 8, the potential of each part when the black sun phenomenon occurs is indicated by a broken line, and the potential of each part when the black sun phenomenon is suppressed is indicated by a solid line. In addition, at the timing of each drive shown in FIG. 8, the image sensor 3 is controlled similarly to the timing of each drive shown in FIG. However, since the high-intensity light is incident during the reset period of the image sensor 3, the potential of each signal is different. Therefore, in the description of the timing of each drive shown in FIG. 8, a detailed description of the same operation as the timing of each drive shown in FIG. 7 will be omitted, and the description will focus on the change in the potential of each signal. I do.

In the timing chart shown in FIG. 8, the high-intensity light during the reset period is indicated by the level of the PD potential V _PD up to time t3. In the timing chart shown in FIG. 8, the FD saturation potential V _FDSAT indicates the lowest potential that the pixel charge accumulation unit FD can take. The pixel signal line saturation potential V _314SAT indicates the lowest potential that the pixel signal line 314 can take. The pixel memory signal potential _VMCSIG1 indicates the potential at the pixel memory charge storage portion MC when the black _sun phenomenon occurs. The pixel memory signal potential V _MCSIG2 indicates a potential at the pixel memory charge accumulation unit MC when the black _sun phenomenon is suppressed by the configuration of the image sensor 3 of the present embodiment.

  An image 201 shown in FIG. 9A is an image obtained by photographing a high-brightness point light source and a black sun phenomenon occurs, and an image 202 shown in FIG. 9B is a high-brightness point light source. And an image when the black sun phenomenon is suppressed in the image sensor 3 of the present embodiment is shown. Further, in the image 201 shown in FIG. 9A and the image 202 shown in FIG. 9B, the image coordinates 203 are picked up with high-intensity light that does not cause a black sun phenomenon, but the image sensor The output of 3 indicates a saturated part. In the image 201 shown in FIG. 9A, an image coordinate 204 indicates a part where a defect due to a black sun phenomenon occurs. In the image 202 shown in FIG. 9B, the image coordinate 205 indicates the same part as the image coordinate 204 after the black sun phenomenon is suppressed by the image sensor 3 of the present embodiment.

  First, the case where the black sun phenomenon occurs as indicated by a broken line in the timing chart shown in FIG. 8 will be described. In the image sensor 3 of the present embodiment, when the black sun phenomenon occurs as in the conventional MOS type solid-state imaging device, the pixel memory clip reference transistor MM5 and the pixel memory clip enable transistor MM6 are not controlled. As shown by the broken line in FIG. 8, the pixel memory clip enable pulse ΦCE is kept at the “Low” level and the clip function is disabled.

At time t1, the pixel charge accumulation unit FD of the unit pixel 313 in the pixel array unit 312 is reset by performing the same control as the timing of each drive illustrated in FIG. 7, and the FD potential V _FD is the potential of the power supply potential VDDP. The pixel signal line potential V ₃₁₄ is reset to a potential in the vicinity of the power supply potential VDDP corresponding to the FD potential V _FD . Note that the clipping function of the pixel signal line potential V ₃₁₄ is disabled. Further, the pixel memory of the unit pixel memory 323 in the pixel memory array unit 322 is changed from the pixel charge storage unit FD of the unit pixel 313 in the pixel array unit 312 by controlling in the same manner as the timing of each drive shown in FIG. to conduct a route to the charge storage portion MC, by resetting the pixel memory charge storage portion MC of the unit pixel memory 323 in the pixel memory array portion 322, the pixel memory potential V _MC is the potential of the power supply potential VDDM.

Subsequently, at time t2, similarly to the timing of each drive shown in FIG. 7, the pixel chip vertical scanning circuit 311 sets the pixel reset pulse ΦPR to the “Low” level, so that the power supply potential VDDP of the FD potential V _FD. The reset operation to the potential of is terminated. At this time, if high-intensity light is incident on the image sensor 3, a large amount of charge is generated in the photodiode PD as shown in the PD potential V _PD , and the charge generated by the photodiode PD is converted into the pixel charge storage unit. There is a phenomenon in which leakage occurs in the FD, or a phenomenon in which a large amount of charges are generated in the pixel charge storage unit FD due to direct light incident on the pixel charge storage unit FD. When such a phenomenon occurs, the pixel charge accumulation unit FD after the pixel reset pulse ΦPR is set to the “Low” level cannot keep the potential at the reset potential, as shown after time t2 in FIG. At the same time, the FD potential V _FD starts to drop. As the FD potential V _FD decreases, the pixel signal line potential V ₃₁₄ also decreases as indicated by a broken line after time t2 in FIG.

At time t3, the FD potential V _FD drops to the FD saturation potential V _FDSAT . Further, the pixel signal line potential V ₃₁₄ also drops to the pixel signal line saturation potential V _314SAT . Then, at the time t3 when the pixel memory clip enable pulse ΦCE is set to the “Low” level, that is, when the clipping function is disabled, the pixel chip vertical scanning circuit 311 sets the pixel transfer pulse ΦPT to the “High” level. However, the pixel signal line potential V ₃₁₄ does not change. This is because the FD potential V _FD does not change to a potential lower than the FD saturation potential V _FDSAT .

Further, at time t3, the pixel signal processing chip vertical scanning circuit 321, and the "Low" level pixel memory reset pulse FaiMR, be terminated reset operation to the power supply potential VDDM of the pixel memory potential _{V MC,} the pixel signal since the line voltage _{V 314} does not change, it does not change the pixel memory potential _{V MC.} That is, the pixel memory potential _{V MC,} as shown at time t3 after the broken line in FIG. 8, the pixel memory signal potential _{V MCSIG1} similar potential as the pixel memory reset potential _{V MCRS.}

At the time t3, the PD potential V _PD is transferred to the pixel charge accumulation unit FD by the pixel chip vertical scanning circuit 311 setting the pixel transfer pulse ΦPT to the “High” level. Once, the signal charge accumulated in the photodiode PD becomes empty. However, if high-intensity light continues to enter, a large amount of charge is generated again in the photodiode PD, so that the potential changes like the PD potential V _PD after time t3 in FIG.

In this state, the control after time t4 is performed similarly to the timing of each drive shown in FIG. 7, the pixel memory signal potential _VMCSIG1 is clamped (held) at time t6, and the pixel memory at time t7. Even if the reset potential V _MCRS is sampled, the pixel memory signal after noise removal obtained by the difference processing by the pixel signal processing chip column processing circuit 326 is about “0”. For this reason, as the obtained image, an image of the black sun phenomenon in which the part of the image coordinate 204 irradiated with the high-intensity light is black like the image 201 shown in FIG. 9A is captured. A portion where the pixel memory signal after noise removal is “0” is indicated by the image coordinates 204 shown in FIG.

  Next, the case of suppressing the black sun phenomenon shown by the solid line in the timing chart shown in FIG. 8 will be described. In the image sensor 3 of the present embodiment, the case of suppressing the black sun phenomenon is the same as the timing of each drive shown in FIG. 7, that is, as shown by the solid line in FIG. This is a case where the clipping function is enabled by controlling the transistor MM5 and the pixel memory clip enable transistor MM6. In the suppression of the black sun phenomenon in the image sensor 3 of the present embodiment, the pixel memory clip enable pulse ΦCE is set to “High” level for a predetermined time, and the pixel memory clip reference pulse ΦCR is controlled to a predetermined voltage.

At time t1, the pixel charge accumulation unit FD of the unit pixel 313 in the pixel array unit 312 is reset by performing the same control as the timing of each drive illustrated in FIG. 7, and the FD potential V _FD is the potential of the power supply potential VDDP. The pixel signal line potential V ₃₁₄ is reset to a potential in the vicinity of the power supply potential VDDP corresponding to the FD potential V _FD . Also, the clipping function of the pixel signal line potential V ₃₁₄ is enabled, and the voltage range of the pixel signal line potential V ₃₁₄ is limited to a potential corresponding to the first reference potential VREF1. Further, the path from the pixel charge storage unit FD of the unit pixel 313 in the pixel array unit 312 to the pixel memory charge storage unit MC of the unit pixel memory 323 in the pixel memory array unit 322 is made conductive, and the inside of the pixel memory array unit 322 is established. by pixel memory charge storage portion MC of the unit pixel memory 323 is reset, the pixel memory potential V _MC is the potential of the power supply potential VDDM.

Subsequently, at time t2, similarly to the timing of each drive shown in FIG. 7, the pixel chip vertical scanning circuit 311 sets the pixel reset pulse ΦPR to the “Low” level, so that the power supply potential VDDP of the FD potential V _FD. The reset operation to the potential of is terminated. At this time, since the high-intensity light is incident on the image sensor 3, as in the case where the black sun phenomenon described above occurs, the charge generated by the photodiode PD leaks into the pixel charge storage portion FD, A phenomenon in which a large amount of charges are generated in the pixel charge storage unit FD occurs due to direct light incident on the charge storage unit FD. As a result, at time t3 after the pixel reset pulse ΦPR is set to the “Low” level, the FD potential V _FD drops to the FD saturation potential V _FDSAT as in the case where the black _sun phenomenon occurs.

However, the pixel signal line potential V ₃₁₄ has a voltage range of the first reference potential VREF1 by the pixel memory clip reference transistor MM5 and the pixel memory clip enable transistor MM6 controlled by the pixel memory clip reference pulse ΦCR and the pixel memory clip enable pulse ΦCE. It is limited to the potential corresponding to. For this reason, the pixel signal line potential V ₃₁₄ does not decrease with the decrease of the FD potential V _FD , and is not lower than the potential corresponding to the first reference potential VREF 1 as shown by the solid line after time t 2 in FIG. Do not descend. Therefore, at time t3, when the pixel chip vertical scanning circuit 311 sets the pixel transfer pulse ΦPT to the “High” level, the signal charge generated by the photodiode PD is transferred to the pixel charge storage unit FD, and the pixel signal line potential V _{314 is obtained.} Falls from the potential corresponding to the first reference potential VREF1 by the amount corresponding to the signal charge transferred to the pixel charge storage portion FD. Then, during the period during which the FD potential V _FD and the pixel signal line potential V ₃₁₄ from time t4 are stabilized to the signal potential (period until time t5 in FIG. 8), the pixel signal line potential V ₃₁₄ is the pixel signal line saturation potential. The potential varies up to V _314SAT .

At time t3, the pixel signal processing chip vertical scanning circuit 321, and the pixel memory clip reference pulse ΦCR the level of the second reference potential VREF2, corresponding to the voltage range of the pixel signal line potential _{V 314} to the second reference potential VREF2 The potential is limited. Therefore, at time t3, the pixel signal processing chip vertical scanning circuit 321, when the "Low" level pixel memory reset pulse FaiMR, pixel memory potential _{V MC,} along with the fluctuation of the potential of the pixel signal line potential _{V 314} The pixel memory signal potential _VMCSIG2 changes.

In this state, similarly to the timing of each drive shown in FIG. 7, the control after time t5 is performed, the pixel memory signal potential _VMCSIG2 is clamped (held) at time t6, and the pixel memory at time t7. The reset potential V _MCRS is sampled. As a result, the pixel signal processing chip column processing circuit 326 performs a difference process between the pixel memory signal potential V _MCSIG2 clamped at time t6 and the pixel memory reset potential V _MCRS sampled at time t7. The pixel memory signal does not become about “0”, and a signal similar to the saturation signal amount of the photodiode PD can be obtained. For this reason, the obtained image does not become black at the position of the image coordinate 205 irradiated with the high-intensity light like the image 202 shown in FIG. An image in which the output is saturated, that is, an image in which the black sun phenomenon is suppressed can be taken. Note that a part that becomes a signal similar to the saturation signal amount due to suppression of the black sun phenomenon is indicated by an image coordinate 205 shown in FIG.

As described above, in the image sensor 3 of the present embodiment, the pixel memory clip reference transistor MM5 and the pixel memory clip enable transistor MM6 are used to reset the image sensor 3 (the period from time t1 to time t3 in FIG. 8). the voltage range of the pixel signal line potential _{V 314} in), to limit the potential corresponding to the first reference potential VREF1. Thereby, the black sun phenomenon can be suppressed even when high-intensity light is incident during the reset period.

  In the image sensor 3 of the present embodiment, in the solid-state imaging device configured by connecting a plurality of chips, the pixel memory clip reference transistor MM5 and the pixel memory clip enable transistor MM6 for suppressing the black sun phenomenon Is provided in the pixel signal processing chip 32, it is possible to suppress the black sun phenomenon without reducing the area of the unit pixel 313 in the pixel chip 31. In the digital camera 1 equipped with the image sensor 3 of the present embodiment, it is possible to acquire a good global exposure method image with less noise, in which the black sun phenomenon due to high luminance light is suppressed.

<Suppression timing of transverse muscle phenomenon>
Next, drive timing when high-luminance light is incident during the transfer period of the image sensor 3 will be described. FIG. 10 is a timing chart showing the timing of each drive when high-luminance light is incident during the transfer period of the image sensor 3 of the present embodiment. Moreover, FIG. 11 is a figure explaining the effect when high-intensity light injects in the transfer period of the image sensor 3 of this embodiment. FIG. 12 is a circuit diagram showing an example of a schematic configuration of the unit pixel memory 323 in the pixel signal processing chip 32 related to suppression of the horizontal stripe phenomenon by the high luminance light in the image sensor 3 of the present embodiment.

  Normally, in a MOS type solid-state imaging device, a horizontal stripe phenomenon occurs when high-intensity light is incident during a transfer period. In the image sensor 3 of the present embodiment, as described above, the horizontal stripe phenomenon caused by the pixel to which high-intensity light is incident is suppressed by the pixel memory clip reference transistor MM5 and the pixel memory clip enable transistor MM6. In the timing chart shown in FIG. 10, the potential of each part when the transverse stripe phenomenon occurs is indicated by a broken line, and the potential of each part when the transverse stripe phenomenon is suppressed is indicated by a solid line. In addition, at the timing of each drive shown in FIG. 10, the image sensor 3 is controlled similarly to the timing of each drive shown in FIG. However, since high-intensity light is incident during the transfer period of the image sensor 3, the potential of each signal is different. Therefore, in the description of the timing of each drive shown in FIG. 10, a detailed description of the operation similar to the timing of each drive shown in FIG. 7 will be omitted, and the description will focus on the change in the potential of each signal. I do.

In the following description, the unit pixel 313 (1, 0) is incident on the unit pixel 313 (1, 0) with high-luminance light that does not reach the black sun phenomenon and is disposed in the same row as the unit pixel 313 (1,0). An example in the case where light hardly enters the pixel 313 (1, 5) will be described. In the timing chart shown in FIG. 10, FIG. 10 (a) shows the drive timing for the unit pixel 313 (1,0), and FIG. 10 (b) shows the drive timing for the unit pixel 313 (1,5). Yes. In the timing chart shown in FIG. 10, a pixel signal line signal potential V _314SIG1 indicates a potential at the pixel signal line 314 when the horizontal _stripe phenomenon occurs. The pixel signal line signal potential V _314SIG2 indicates a potential at the pixel signal line 314 when the horizontal _stripe phenomenon is suppressed by the configuration of the image sensor 3 of the present embodiment. The pixel memory signal potential _VMCSIG1 indicates the potential at the pixel memory charge storage portion MC when the horizontal _stripe phenomenon occurs. The pixel memory signal potential _VMCSIG2 indicates a potential at the pixel memory charge accumulation unit MC when the horizontal _stripe phenomenon is suppressed by the configuration of the image sensor 3 of the present embodiment.

  An image 211 shown in FIG. 11A is an image when a high-intensity light source having a certain width is photographed and a horizontal stripe phenomenon occurs, and an image 212 shown in FIG. 11B has a certain width. An image is shown when a high-intensity light source is photographed and the horizontal stripe phenomenon is suppressed in the image sensor 3 of the present embodiment. Further, in the image 211 shown in FIG. 11A and the image 212 shown in FIG. 11B, the image coordinate 213 is a portion where the output of the image sensor 3 is saturated due to the imaging of high luminance light. (For example, a part where the unit pixel 313 (1,0) is arranged). In the image 211 shown in FIG. 11A, the image coordinates 214 indicate a part where a defect due to the horizontal stripe phenomenon occurs (for example, a part where the unit pixels 313 (1, 5) are arranged). In the image 212 shown in FIG. 11B, the image coordinate 215 indicates the same part as the image coordinate 214 after the horizontal stripe phenomenon is suppressed by the image sensor 3 of the present embodiment.

  An example of the schematic configuration of the unit pixel memory 323 shown in FIG. 12 is a unit pixel memory 323 (1,0) related to a unit pixel 313 (1, 0) and a unit pixel 313 (1, 5) described below. And the unit pixel memory 323 (1, 5), which are two unit pixel memories 323 shown in FIG. In FIG. 12, the wiring resistance RCS is parasitic on the common ground wiring 3216 connected to the pixel memory current load CS provided in each of the unit pixel memory 323 (1, 0) and the unit pixel memory 323 (1, 5). It is resistance to do. The configuration of the unit pixel memory 323 (1, 0) and the unit pixel memory 323 (1, 5) shown in FIG. 12 is the same as that of the unit pixel memory 323 shown in FIG. Detailed description is omitted.

First, the case where the horizontal stripe phenomenon shown by the broken line in the timing chart shown in FIG. 10 occurs will be described. In the image sensor 3 of the present embodiment, when the horizontal stripe phenomenon occurs as in the conventional MOS type solid-state imaging device, the pixel memory clip reference transistor MM5 and the pixel memory clip enable transistor MM6 are not controlled. as shown in 1 0 dashed, leave the pixel memory clips enable pulse ΦCE "Low" level, is a case where the disable flag function.

At time t1, the pixel charge accumulation unit FD of the unit pixel 313 in the pixel array unit 312 is reset by performing the same control as the timing of each drive illustrated in FIG. 7, and the FD potential V _FD is the potential of the power supply potential VDDP. The pixel signal line potential V ₃₁₄ is reset to a potential in the vicinity of the power supply potential VDDP corresponding to the FD potential V _FD . Note that the clipping function of the pixel signal line potential V ₃₁₄ is disabled. Further, the pixel memory of the unit pixel memory 323 in the pixel memory array unit 322 is changed from the pixel charge storage unit FD of the unit pixel 313 in the pixel array unit 312 by controlling in the same manner as the timing of each drive shown in FIG. to conduct a route to the charge storage portion MC, by resetting the pixel memory charge storage portion MC of the unit pixel memory 323 in the pixel memory array portion 322, the pixel memory potential V _MC is the potential of the power supply potential VDDM.

Subsequently, at time t2, similarly to the timing of each drive shown in FIG. 7, the pixel chip vertical scanning circuit 311 sets the pixel reset pulse ΦPR to the “Low” level, so that the power supply potential VDDP of the FD potential V _FD. The reset operation to the potential of is terminated. Accordingly, the FD potential V _FD and the pixel signal line potential V ₃₁₄ are set to the unit pixel 313 during a period during which the FD potential V _FD and the pixel signal line potential V ₃₁₄ are stabilized at the reset potential (a period until time t3 in FIG. 10). The potential is lowered by the amount of reset noise, and the FD potential V _FD is _{stabilized at} the potential of the FD reset potential V _FDRS , and the pixel signal line potential V ₃₁₄ is stabilized at the potential of the pixel signal line reset potential V _314RS .

Subsequently, at time t3, when the pixel chip vertical scanning circuit 311 sets the pixel transfer pulse ΦPT to the “High” level, the signal charge generated by the photodiode PD is transferred to the pixel charge storage unit FD. Thus, FD potential V _{FD (1, 0)} and FD potential V _{FD (1, 5)} are changed to PD potential V _{PD (1, 0)} and PD potential V _{PD (1, 5)} at time t3, respectively. The corresponding potential is obtained. Further, the pixel signal line potential V _{314 (1, 0)} and the pixel signal line potential V _{314 (1, 5)} also drop in potential by the amount corresponding to the signal charge transferred to each pixel charge storage portion FD. .

At time t3, the pixel signal processing chip vertical scanning circuit 321, and the "Low" level pixel memory reset pulse FaiMR, terminates the reset operation to the power supply potential VDDM of the pixel memory potential _{V MC.} As a result, the pixel memory potential _{VMC (1, 0)} and the pixel memory potential _{VMC (1, 5)} decrease in response to the transfer of the signal charge generated by the photodiode PD to the pixel charge storage unit FD. The respective potentials correspond to the line potential V _{314 (1, 0)} and the pixel signal line potential V _{314 (1, 5)} .

At the time t3, the PD potential V _PD is transferred to the pixel charge accumulation unit FD by the pixel chip vertical scanning circuit 311 setting the pixel transfer pulse ΦPT to the “High” level. Once, the signal charge accumulated in the photodiode PD becomes empty. However, since a large amount of charge is generated again in the photodiode PD of the unit pixel 313 (1, 0) on which the high luminance light continues to enter, the PD potential V _{PD (1} after time t3 in FIG. _{, 0)} , the potential changes. Note that a large amount of charge is not generated in the photodiode PD of the unit pixel 313 (1, 5) in which almost no light is incident. Therefore, the PD potential V _{PD (1, 5} ) after time t3 in FIG. ₎ , The potential changes.

Then, during the period in which the FD potential V _FD and the pixel signal line potential V ₃₁₄ from the time t4 are stabilized to the signal potential (period until the time t5 in FIG. 10), the unit pixel 313 (1 , 0) of the FD potential V _{FD (1} , 0) drops to the FD saturation potential V _FDSAT . In addition, as the FD potential V _{FD (1,0)} decreases, the pixel signal line potential V _{314 (1,0)} also changes as shown by the broken line after time t4 in FIG. The potential drops to the saturation potential V _314SAT . Further, the FD potential V _{FD (1,} 5) of the unit pixel 313 (1, 5) where light hardly enters is stabilized at the potential of the FD signal potential V _FDSIG , and accordingly, the pixel signal line potential V _{314 (1 , 5)} once becomes the potential of the pixel signal line signal potential V _{314 SIG 2} . Further, the pixel memory potential _{VMC (1, 5)} also temporarily becomes the potential of the pixel memory signal potential _VMCSIG2 .

However, since the pixel signal line potential V _{314 (1, 0)} has dropped to the pixel signal line saturation potential V _314SAT , in the unit pixel memory 323 (1,0) connected to the unit pixel 313 (1,0). The transistor included in the pixel memory current load CS _{(1, 0)} enters the non-saturation region, and the amount of current flowing through the pixel memory current load CS _{(1, 0)} decreases. Due to the decrease in the amount of current of the pixel memory current load CS _{(1, 0)} , the amount of voltage drop due to the wiring resistance RCS shown in FIG. 12 decreases.

Therefore, in the unit pixel 313 (1, 5) arranged in the same row as the unit pixel 313 (1, 0), the unit pixel memory 323 (1, 5) connected to the unit pixel 313 (1, 5). The amount of current that the pixel memory current load CS (1, 5) flows is increased. The increase in the amount of current of the pixel memory current load CS (1, 5) also increases the amount of current flowing through the pixel signal line 314 (1, 5) of the unit pixel 313 (1, 5). As the amount of current flowing through the pixel signal line 314 (1,5) increases, the voltage between the gate and the source of the pixel amplification transistor PM3 in the unit pixel 313 (1,5) increases, and the pixel signal line potential V314 ( 1,5) drops. At time t5, the pixel signal line potential V314 (1, 5) becomes the potential of the pixel signal line signal potential V314SIG1, as indicated by a broken line after time t4 in FIG. 10B. Further, the pixel memory potential VMC (1, 5) is also the pixel memory as shown by the broken line after time t4 in FIG. 10B in accordance with the variation of the pixel signal line potential V314 (1, 5). want intends to become the potential of the signal potential VMCSIG1.

In this state, similarly to the timing of each drive shown in FIG. 7, the control after time t5 is performed, and the pixel memory signal potential _VMCSIG1 is clamped (held) at time t6 and the pixel memory at time t7. Even if the reset potential V _MCRS is sampled, a correct pixel memory signal after noise removal cannot be obtained by the difference processing by the pixel signal processing chip column processing circuit 326. More specifically, the pixel memory signal becomes a pixel memory signal that is increased by an increase in voltage between the gate and the source (pixel memory signal potential _VMCSIG2 −pixel memory signal potential _VMCSIG1 ). Note that the unit pixel 313 arranged in a different row from the unit pixel 313 (1, 0) does not have the above-described state. For this reason, the obtained image is a horizontal stripe in which the left and right image coordinates 214 of the image coordinates 213 irradiated with the high-intensity light are bright stripes as in the image 211 shown in FIG. An image of the phenomenon is captured. Note that the portion of the pixel memory signal that is increased by the increase in the gate-source voltage after noise removal is indicated by the image coordinates 214 shown in FIG.

Note that, as indicated by a broken line after time t3 in FIG. 10A, the pixel signal line potential V _{314 (1, 0)} has dropped to the pixel signal line saturation potential V _314SAT .
The potential of the pixel memory potential _{VMC (1, 0)} also drops. However, the high-intensity light incident on the unit pixel 313 (1, 0) is high-intensity light that does not reach the black sun phenomenon. For this reason, the pixel memory signal at the position of the image coordinate 213 irradiated with the high-intensity light is a signal similar to the saturation signal amount of the photodiode PD, but there is a black sun phenomenon in the portion of the image coordinate 213. Does not occur.

  Next, the case where the horizontal stripe phenomenon shown by the solid line in the timing chart shown in FIG. 10 is suppressed will be described. In the image sensor 3 of the present embodiment, the case of suppressing the horizontal stripe phenomenon is the same as the timing of each drive shown in FIG. 7, that is, as shown by the solid line in FIG. This is a case where the clipping function is enabled by controlling the MM5 and the pixel memory clip enable transistor MM6. In the suppression of the horizontal stripe phenomenon in the image sensor 3 of the present embodiment, the pixel memory clip enable pulse ΦCE is set to the “High” level for a predetermined time, and the pixel memory clip reference pulse ΦCR is controlled to a predetermined voltage.

At time t1, the pixel charge accumulation unit FD of the unit pixel 313 in the pixel array unit 312 is reset by performing the same control as the timing of each drive illustrated in FIG. 7, and the FD potential V _FD is the potential of the power supply potential VDDP. The pixel signal line potential V ₃₁₄ is reset to a potential in the vicinity of the power supply potential VDDP corresponding to the FD potential V _FD . Also, the clipping function of the pixel signal line potential V ₃₁₄ is enabled, and the voltage range of the pixel signal line potential V ₃₁₄ is limited to a potential corresponding to the first reference potential VREF1. Further, the path from the pixel charge storage unit FD of the unit pixel 313 in the pixel array unit 312 to the pixel memory charge storage unit MC of the unit pixel memory 323 in the pixel memory array unit 322 is made conductive, and the inside of the pixel memory array unit 322 is established. by pixel memory charge storage portion MC of the unit pixel memory 323 is reset, the pixel memory potential V _MC is the potential of the power supply potential VDDM.

Subsequently, at time t2, similarly to the timing of each drive shown in FIG. 7, the pixel chip vertical scanning circuit 311 sets the pixel reset pulse ΦPR to the “Low” level, so that the power supply potential VDDP of the FD potential V _FD. The reset operation to the potential of is terminated. Accordingly, the FD potential V _FD and the pixel signal line potential V ₃₁₄ are set to the unit pixel 313 during a period during which the FD potential V _FD and the pixel signal line potential V ₃₁₄ are stabilized at the reset potential (a period until time t3 in FIG. 10). The potential is lowered by the amount of reset noise, and the FD potential V _FD is _{stabilized at} the potential of the FD reset potential V _FDRS , and the pixel signal line potential V ₃₁₄ is stabilized at the potential of the pixel signal line reset potential V _314RS .

Subsequently, at time t3, when the pixel chip vertical scanning circuit 311 sets the pixel transfer pulse ΦPT to the “High” level, the signal charge generated by the photodiode PD is transferred to the pixel charge storage unit FD. Thus, FD potential V _{FD (1, 0)} and FD potential V _{FD (1, 5)} are changed to PD potential V _{PD (1, 0)} and PD potential V _{PD (1, 5)} at time t3, respectively. The corresponding potential is obtained. Further, the pixel signal line potential V _{314 (1, 0)} and the pixel signal line potential V _{314 (1, 5)} also drop in potential by the amount corresponding to the signal charge transferred to each pixel charge storage portion FD. .

At time t3, the pixel signal processing chip vertical scanning circuit 321, and the "Low" level pixel memory reset pulse FaiMR, terminates the reset operation to the power supply potential VDDM of the pixel memory potential _{V MC.} As a result, the pixel memory potential _{VMC (1, 0)} and the pixel memory potential _{VMC (1, 5)} decrease in response to the transfer of the signal charge generated by the photodiode PD to the pixel charge storage unit FD. The respective potentials correspond to the line potential V _{314 (1, 0)} and the pixel signal line potential V _{314 (1, 5)} .

Then, during the period in which the FD potential V _FD and the pixel signal line potential V ₃₁₄ from the time t4 are stabilized to the signal potential (period until the time t5 in FIG. 10), the unit pixel 313 (1 , 0) of the FD potential V _{FD (1} , 0) drops to the FD saturation potential V _FDSAT .

However, the pixel signal line potential V _{314 (1, 0)} and the pixel signal line potential V _{314 (1, 5)} are respectively controlled by the pixel memory clip reference pulse ΦCR and the pixel memory clip enable pulse ΦCE. The voltage range is limited to the potential corresponding to the second reference potential VREF2 by the transistor MM5 and the pixel memory clip enable transistor MM6. For this reason, the pixel signal line potential V _{314 (1, 0)} does not decrease with the decrease in the FD potential V _{FD (1,0)} , and the second signal line potential V _{314 (1, 0)} does not decrease as shown by the solid line after time t4 in FIG. It does not drop below the potential corresponding to the reference potential VREF2. This is because the transistor provided in the pixel memory current load CS _(1, 0) in the unit pixel memory 323 (1, 0) connected to the unit pixel 313 (1, 0) with the second reference potential VREF2 is not saturated. This is because the transistor in the pixel memory current load CS _{(1, 0)} is prevented from entering the non-saturated region by setting the potential so as not to enter the region. As a result, the amount of current flowing through the pixel memory current load CS _{(1, 0)} does not change, and the amount of voltage drop due to the wiring resistance RCS shown in FIG. 12 does not change.

For this reason, the unit pixel memory 323 (1, 5) connected to the unit pixel 313 (1, 5) also in the unit pixel 313 (1, 5) arranged in the same row as the unit pixel 313 (1, 0). The amount of current flowing through the pixel memory current load CS _{(1, 5)} does not change, and the amount of current flowing through the pixel signal line 314 (1, 5) of the unit pixel 313 (1, 5) does not change. As a result, the voltage between the gate and source of the pixel amplification transistor PM3 in the unit pixel 313 (1, 5) does not increase.

Therefore, at time t5, the potential of the pixel signal line potential V _{314 (1, 5)} drops to the potential of the pixel signal line signal potential V _314SIG1 as shown by the broken line after time t4 in FIG. Instead, the pixel signal line signal potential is V _{314 SIG 2} . Similarly, the pixel memory potential V _{MC (1, 5)} does not drop to the pixel memory signal potential V _MCSIG1 as shown by the broken line after time t4 in FIG. _{It becomes} the potential of _MCSIG2 .

In this state, similarly to the timing of each drive shown in FIG. 7, the control after time t5 is performed, the pixel memory signal potential _VMCSIG2 is clamped (held) at time t6, and the pixel memory at time t7. The reset potential V _MCRS is sampled. Thereby, in the differential processing by the pixel signal processing chip column processing circuit 326, a correct pixel memory signal after noise removal can be obtained. More specifically, it is possible to obtain a pixel memory signal similar to that when high-luminance light is not incident (pixel memory reset potential V _{MCRS −pixel} memory signal potential V _MCSIG2 ). For this reason, in the obtained image, like the image 212 shown in FIG. 11B, the left and right image coordinate 215 portions of the image coordinate 213 irradiated with the high-intensity light are not bright stripes. That is, an image in which the lateral stripe phenomenon is suppressed can be taken. Note that a portion that becomes a signal similar to the case where high-luminance light is not incident due to suppression of the lateral stripe phenomenon is indicated by an image coordinate 215 shown in FIG.

As described above, in the image sensor 3 of the present embodiment, the pixel memory clip reference transistor MM5 and the pixel memory clip enable transistor MM6 allow the transfer period of the image sensor 3 (the period from time t3 to time t6 in FIG. 10). the voltage range of the pixel signal line potential _{V 314} in), to limit the potential corresponding to the second reference potential VREF2. Thereby, even when high-intensity light is incident during the transfer period, it is possible to suppress the horizontal stripe phenomenon.

  In the image sensor 3 of the present embodiment, in the solid-state imaging device configured by connecting a plurality of chips, the pixel memory clip reference transistor MM5 and the pixel memory clip enable transistor MM6 for suppressing the horizontal stripe phenomenon are provided. By providing in the pixel signal processing chip 32, it is possible to suppress the horizontal stripe phenomenon without reducing the area of the unit pixel 313 in the pixel chip 31. In the digital camera 1 equipped with the image sensor 3 of the present embodiment, it is possible to acquire a good global exposure method image with less noise, in which the horizontal stripe phenomenon due to high-intensity light is suppressed.

  As described above, according to the embodiment for carrying out the present invention, the pixel memory clip reference transistor for limiting the voltage of the pixel memory signal line, and the pixel for determining whether the function of the pixel memory clip reference transistor is valid or invalid A memory clip enable transistor is provided in the pixel signal processing chip. Then, the voltage range of the pixel signal line (pixel memory signal line) for a predetermined period is limited to a predetermined potential. As a result, it is possible to suppress the black sun phenomenon and the horizontal stripe phenomenon due to the high-intensity light input to the solid-state imaging device.

  According to the embodiment for implementing the present invention, the solid-state imaging device is configured by connecting a plurality of chips, and the pixel memory clip reference transistor and the pixel memory clip enable transistor are provided in the pixel signal processing chip. Accordingly, it is possible to realize a solid-state imaging device capable of suppressing the black sun phenomenon and the horizontal stripe phenomenon due to the high-intensity light without reducing the area of the unit pixel in the pixel chip. As a result, an image pickup apparatus equipped with the solid-state image pickup apparatus according to the present embodiment can acquire a good global exposure method image with less noise, in which the black sun phenomenon and the horizontal stripe phenomenon due to high-intensity light are suppressed.

  In the present embodiment, the solid-state imaging device according to an aspect of the present invention corresponds to, for example, the image sensor 3, and the imaging device corresponds to, for example, the digital camera 1. In the present embodiment, the first substrate according to an aspect of the present invention corresponds to, for example, the pixel chip 31, the second substrate corresponds to, for example, the pixel signal processing chip 32, and the connection portion is For example, corresponding to the chip connection unit 33, the pixel unit corresponds to, for example, the pixel array unit 312 and the pixel memory array unit 322. In the present embodiment, a pixel according to an aspect of the present invention corresponds to, for example, the unit pixel 313, and a signal line corresponds to, for example, the pixel signal line 314 and the pixel memory signal line 324, The storage circuit corresponds to, for example, the pixel memory charge storage unit MC, the output circuit corresponds to, for example, the pixel memory amplification transistor MM3 and the pixel memory selection transistor MM4, and the clip circuit includes, for example, the pixel memory clip reference transistor. The output signal line corresponds to the pixel signal processing chip vertical signal line 325, for example, corresponding to the MM5 and the pixel memory clip enable transistor MM6.

  In the present embodiment, the current source load according to an aspect of the present invention corresponds to, for example, the pixel memory current load CS, and the storage unit corresponds to, for example, the pixel memory charge storage unit MC, and the storage unit signal The reset unit corresponds to, for example, the pixel memory reset transistor MM2, the storage unit signal selection unit corresponds to, for example, the pixel memory selection transistor MM4, and the storage unit signal amplification unit corresponds to, for example, the pixel memory amplification transistor MM3. The coupling capacitor corresponds to, for example, the pixel memory coupling capacitor CC. Further, the subtraction unit according to an aspect of the present invention corresponds to, for example, the pixel signal processing chip column processing circuit 326 in the present embodiment.

  In the present embodiment, the transfer circuit and the transfer transistor according to an aspect of the present invention correspond to, for example, the pixel transfer transistor PM1, and the first amplifier circuit and the first amplifier transistor are, for example, the pixel amplifier transistor PM3. Correspondingly, the first reset circuit and the first reset transistor correspond to, for example, the pixel reset transistor PM2. In the present embodiment, the analog memory circuit according to an aspect of the present invention corresponds to, for example, the pixel memory coupling capacitor CC, the pixel memory charge storage unit MC, and the pixel memory transfer transistor MM1, and the second amplification The circuit and the second amplification transistor correspond to, for example, the pixel memory amplification transistor MM3, and the second reset circuit and the second reset transistor correspond to, for example, the pixel memory reset transistor MM2.

  The first signal line according to an aspect of the present invention corresponds to, for example, the pixel signal line 314 and the pixel memory signal line 324 in the present embodiment, and the transistor is, for example, a pixel memory clip reference transistor. Corresponding to MM5, the capacitor corresponds to, for example, the pixel memory coupling capacitor CC, and the second signal line corresponds to, for example, the pixel signal processing chip vertical signal line 325.

  In addition, the specific configuration of the circuit configuration and the driving method in the present invention is not limited to the mode for carrying out the present invention, and various modifications can be made without departing from the spirit of the present invention. . For example, even when the pixel components and the driving method are changed, for example, the driving method can be changed according to the components and circuit configuration in the image sensor 3 and the unit pixel 313.

  Further, the arrangement of the pixels in the row direction and the column direction is not limited to the mode for carrying out the present invention, and the number of pixels in the row direction and the column direction in which the pixels are arranged without departing from the gist of the present invention. Can be changed.

  As described above, the description has been given based on the embodiment for carrying out the present invention. However, any combination of each component, each processing process, and the expression of the present invention converted into a computer program product or the like is also an aspect of the present invention. It is effective as Here, the computer program product includes a recording medium (DVD medium, hard disk medium, memory medium, etc.) on which a program code is recorded, a computer on which the program code is recorded, and an Internet system (for example, a server and the like) on which the program code is recorded. A recording medium, apparatus, device or system in which a program code is recorded, such as a system including a client terminal. In this case, each component and each processing process described above are mounted in each module, and a program code including the mounted module is recorded in a computer program product.

For example, the computer program product according to an aspect of the present invention electrically connects the first substrate and the second substrate by a connection unit that electrically connects the first substrate and the second substrate. A computer program product in which a program code for causing a computer to execute processing of a connected solid-state imaging device is recorded, which is included in the first substrate of a pixel portion included in the solid-state imaging device and includes a photoelectric conversion element a module for outputting the pixel signal generated by the pixel to the signal line to be supplied to the second substrate, the a signal storage circuit included in the second substrate, the pixel signals supplied via the signal line a module for storing, from the output circuit included in the second substrate, a module for outputting the pixel signal stored in the signal storage circuit, prior to Clip circuit included in the second substrate, the voltage of the pixel No. signal is a computer program product program code is recorded; and a module for clipping so as not fall below a predetermined voltage.

  Further, for example, a program for realizing processing by each component of the digital camera 1 shown in FIG. 1 is recorded on a computer-readable recording medium, and the program recorded on the recording medium is read into a computer system. By executing, the above-described various processes related to the digital camera 1 may be performed. Here, the “computer system” may include an OS and hardware such as peripheral devices. Further, the “computer system” includes a homepage providing environment (or display environment) if a WWW system is used. The “computer-readable recording medium” means a flexible disk, a magneto-optical disk, a ROM, a writable nonvolatile memory such as a flash memory, a portable medium such as a CD-ROM, a hard disk built in a computer system, etc. This is a storage device.

  Further, the “computer-readable recording medium” refers to a volatile memory (for example, DRAM (Dynamic) in a computer system serving as a server or a client when a program is transmitted via a network such as the Internet or a communication line such as a telephone line. Random Access Memory)) that holds a program for a certain period of time is also included. The program may be transmitted from a computer system storing the program in a storage device or the like to another computer system via a transmission medium or by a transmission wave in the transmission medium. Here, the “transmission medium” for transmitting the program refers to a medium having a function of transmitting information, such as a network (communication network) such as the Internet or a communication line (communication line) such as a telephone line. The program may be for realizing a part of the functions described above. Furthermore, what can implement | achieve the function mentioned above in combination with the program already recorded on the computer system, and what is called a difference file (difference program) may be sufficient.

  The embodiment of the present invention has been described above with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes various modifications within the scope of the present invention. It is.

The solid-state imaging device according to an aspect of the present invention electrically connects the first substrate and the second substrate by a connection unit that electrically connects the first substrate and the second substrate. a solid-state imaging device to be connected, a pixel means the solid-state imaging device has, the included in the first substrate, comprising a photoelectric conversion element, and a pixel for generating the pixel signal, the image No. Motoshin the A signal line to be supplied to a second substrate; a signal storage means for storing the pixel signal supplied via the signal line, included in the second substrate; and included in the second substrate; and output means for outputting the pixel signal stored in the signal storage unit, said included in the second substrate, the voltage of the pixel No. signal comprises a clipping means for clipping so as not fall below a predetermined voltage, the It may be a solid-state imaging device characterized by having

The imaging apparatus according to an aspect of the present invention electrically connects the first substrate and the second substrate by a connection unit that electrically connects the first substrate and the second substrate. the imaging apparatus of a pixel unit in which the imaging apparatus has, the included in the first substrate, comprising a photoelectric conversion element, and a pixel for generating the pixel signal, the second of the picture No. Motoshin A signal line to be supplied to the substrate; a signal storage unit that is included in the second substrate and that stores the pixel signal supplied via the signal line; and that is included in the second substrate and stores the signal and output means for outputting the pixel signals stored in the unit, included in the second substrate, the voltage of the pixel No. signal has and a clip means for clipping so as not fall below a predetermined voltage, it The imaging device characterized by this may be used.

The solid-state imaging device according to an aspect of the present invention electrically connects the first substrate and the second substrate by a connection unit that electrically connects the first substrate and the second substrate. A solid-state imaging device to be connected, wherein the pixel means included in the solid-state imaging device is included in the first substrate and includes a pixel including a photoelectric conversion element, a first signal line connected to the pixel, A transistor included in the second substrate and having one end connected to the first signal line; a capacitor included in the second substrate connected to the first signal line; and the capacitor A solid-state imaging device, wherein the transistor clips so that a voltage of the first signal line does not become a predetermined voltage or less. Also good.

The imaging apparatus according to an aspect of the present invention electrically connects the first substrate and the second substrate by a connection unit that electrically connects the first substrate and the second substrate. The pixel means included in the imaging device is included in the first substrate and includes a photoelectric conversion element, a first signal line connected to the pixel, and the second One end of which is connected to the first signal line , one end of which is connected to the first signal line, and one end of the transistor connected to the first signal line. The imaging device may include a second signal line, and the transistor may be clipped so that a voltage of the first signal line does not become a predetermined voltage or less.

  The embodiment of the present invention has been described above with reference to the drawings. However, the specific configuration is not limited to this embodiment, and various alternatives and modifications can be made without departing from the spirit of the present invention. The equivalent can also be changed. Accordingly, the scope of the invention should not be determined with reference to the above description, but should be determined by the claims, including the full scope of equivalents. In addition, any of the features described above may be combined with other features regardless of whether or not they are preferable. Also, in the claims, each component is one or more quantities unless explicitly stated otherwise. In addition, the claims should not be construed as including means-plus-function limitations unless explicitly stated in the claims using words such as “means for”.

  In the solid-state imaging device according to the embodiment of the present invention, two substrates may be connected by a connection unit, or three or more substrates may be connected by a connection unit. In the case of a solid-state imaging device in which three or more substrates are connected at the connection portion, two of them correspond to the first substrate and the second substrate according to the claims.

DESCRIPTION OF SYMBOLS 1 ... Digital camera 2 ... Lens unit part 3 ... Image sensor 4 ... Light-emitting device 5 ... Memory 6 ... Recording device 7 ... Display device 8 ... Image signal processing circuit DESCRIPTION OF SYMBOLS 9 ... Lens control apparatus 10 ... Image sensor control apparatus 11 ... Light emission control apparatus 12 ... Camera control apparatus 31 ... Pixel chip 32 ... Pixel signal processing chip 33 ... Chip connection part 34... External wiring connection portion 311... Pixel chip vertical scanning circuit 312... Pixel array portion 313... Unit pixel 314. Pixel reset line 317 ... Pixel transfer line 318 ... Pixel selection line 321 ... Pixel signal processing chip vertical scanning circuit 322 ... Pixel memory array unit 323 ... Unit pixel memory 324 ... Pixel memory signal line 325 ... Pixel signal processing chip vertical signal line 326 ... Pixel signal processing chip column processing circuit 327 ... Pixel signal processing chip horizontal scanning circuit 328 ... Pixel signal processing chip horizontal scanning circuit signal line 329 ... Image sensor control circuit 3210 ... Image sensor control circuit signal line 3211 ... Pixel memory reset line 3212 ... Pixel memory transfer line 3213 ... Pixel memory selection line 3214 ... Clip reference line 3215 ... Clip enable line PD ... Photodiode FD ... Pixel charge storage section PM1 ... Pixel transfer transistor PM2 ... Pixel reset transistor PM3 ... Pixel amplification transistor PM4 ... Pixel selection transistor CC ..Pixel memory coupling capacity MC ... Pixel memory charge storage MM1 ... Pixel memory transfer transistor MM2 ... Pixel memory reset transistor MM3 ... Pixel memory amplification transistor MM4 ... Pixel memory selection transistor MM5 ... Pixel memory clip reference transistor MM6 ... Pixel memory clip enable transistor CS: Pixel memory current load V _PD: PD potential V _FD: FD potential V _314: Pixel signal line potential V _MC: Pixel memory potential VDDP, VDDM: Power supply potential V _{FDRS ..FD} reset potential V _FDSIG ... FD signal potential V _314RS ... Pixel signal line reset potential V _314SIG ... Pixel signal line signal potential VREF1... First reference potential VREF2. _MCRS ··· pixel memory reset potential _{V MCS G} · · · pixel memory signal potential _{V FDSAT} ··· FD saturated potential _{V 314SAT} ··· pixel signal line saturation potential _{V MCSIG1} ··· pixel memory signal potential _{V MCSIG2} ··· pixel memory signal potential _{V 314SIG1} ··· pixels Signal line signal potential V _314SIG2 ... Pixel signal line signal potential V _MCSIG1 ... Pixel memory signal potential V _MCSIG2 ... Pixel memory signal potential 201, 211 ... Images 202, 212 ... Images 203, 213, ..Image coordinates 204, 214 ... Image coordinates 205,215 ... Image coordinates RCS ... Wiring resistance 3216 ... Ground wiring

Claims (31)

A solid-state imaging device that electrically connects the first substrate and the second substrate by a connecting portion that electrically connects the first substrate and the second substrate,
The pixel portion included in the solid-state imaging device is
A pixel that is included in the first substrate, includes a photoelectric conversion element, and generates a pixel signal ;
A signal line for supplying said second substrate to said picture No. Motoshin,
A signal storage circuit that is included in the second substrate and stores the pixel signal supplied via the signal line;
An output circuit that is included in the second substrate and outputs the pixel signal stored in the signal storage circuit;
Included in the second substrate, the voltage of the pixel No. signal includes a clip circuit for clipping so as not fall below a predetermined voltage,
Having
A solid-state imaging device. Before Symbol second substrate,
Further comprising an output signal line for outputting the pixel signals accumulated before SL signal storage circuit,
The clip circuit is
The voltage of the output signal lines, clip so as not to be below the predetermined voltage,
The solid-state imaging device according to claim 1, wherein the this. A current source load is connected to the connection part.
The solid-state imaging device according to claim 2. The pixel is
The photoelectric conversion element for generating a signal charge according to the amount of incident light;
An accumulator that accumulates the signal charge generated by the photoelectric conversion element;
A reset unit for resetting the charge stored in the storage unit;
A transfer unit that transfers the signal charge to the storage unit;
An amplifying unit that amplifies the charge accumulated in the accumulating unit and outputs it as a pixel signal;
Have
The level of the predetermined voltage clipped by the clip circuit is:
The reset signal, which is the pixel signal output from the amplification unit according to the charge of the storage unit when reset by the reset unit, is output to the signal line, and the transfer unit outputs the reset signal. The subject signal, which is the pixel signal output from the amplifying unit according to the signal charge transferred to the storage unit, is different from the signal period output to the signal line,
The solid-state imaging device according to claim 3. The signal storage circuit includes:
A storage unit for storing the pixel signal;
A storage unit signal reset unit that resets a voltage of the pixel signal stored in the storage unit;
A storage unit signal selection unit for selecting the storage unit;
A storage unit signal amplification unit that amplifies and outputs the voltage of the pixel signal stored in the storage unit;
A coupling capacitor in which one is connected to the signal line of the pixel signal supplied via the signal line and the other is connected to the storage unit;
The solid-state imaging device according to claim 4, comprising: The second substrate is
A subtracting unit that outputs a signal obtained by subtracting the reset signal from the subject signal;
The solid-state imaging device according to claim 5. Enabling the clipping function of the voltage of the pixel signal supplied via the signal line by the clipping circuit during the reset period;
The solid-state imaging device according to claim 4. The predetermined voltage is
A saturation voltage of the reset signal;
The solid-state imaging device according to claim 7. Enabling the clipping function of the voltage of the pixel signal supplied via the signal line by the clipping circuit during the signal period;
The solid-state imaging device according to claim 4. The predetermined voltage is
A saturation voltage of the subject signal;
The solid-state imaging device according to claim 9. Simultaneously resetting the photoelectric conversion elements of all the pixels of the solid-state imaging device;
The solid-state imaging device according to claim 1. The pixel is
An amplifying circuit for amplifying a signal generated by the photoelectric conversion element;
The signal storage circuit includes:
Storing the amplified signal amplified by the amplifier circuit;
The solid-state imaging device according to claim 1. The pixel is
A noise reduction circuit for reducing noise in the amplified signal output from the amplification circuit;
The signal storage circuit includes:
Storing the amplified signal in which noise is reduced by the noise reduction circuit;
The solid-state imaging device according to claim 1 2, characterized in that. The amplifier circuit is
Including an amplification transistor that receives a signal generated by the photoelectric conversion element at a gate and outputs the amplified signal from one of a source and a drain;
The solid-state imaging device according to claim 13. The noise reduction circuit is:
A clamp capacitor connected to one of the source and drain of the amplification transistor directly or indirectly and for clamping the output amplified signal;
A sample and hold transistor connected directly or indirectly to the clamp capacitor to sample and hold the clamped amplified signal;
Including
The signal storage circuit includes:
Storing the amplified signal sampled and held by the sample and hold transistor;
The solid-state imaging device according to claim 1 4, characterized in that. The connection point on the first substrate side in the connection part and the connection point on the second substrate side in the connection part are:
Arranged at any position on the path from the output terminal of the photoelectric conversion element to the input terminal of the signal storage circuit,
The solid-state imaging device according to claim 1. The connecting portion is a bump.
The solid-state imaging device according to claim 1. The connecting portion is
A first electrode formed on the surface of the first substrate; and a second electrode formed on the surface of the second substrate and bonded to the first electrode;
The solid-state imaging device according to claim 1. The second substrate is
Connected to the surface opposite to the surface of the first substrate irradiated with light incident on the photoelectric conversion element;
The solid-state imaging device according to claim 1. The pixels of the first substrate are
The photoelectric conversion element;
A transfer circuit for transferring a signal generated by the photoelectric conversion element;
A first amplifier circuit for amplifying a signal generated by the photoelectric conversion element;
A first reset circuit for resetting an input unit of the first amplifier circuit;
Have
Signal storage circuit of the second substrate,
An analog memory circuit;
A second amplifier circuit for amplifying the signal of the analog memory circuit;
A second reset circuit for resetting an input unit of the second amplifier circuit;
Having
The solid-state imaging device according to claim 1. A control method for a solid-state imaging device in which the first substrate and the second substrate are electrically connected by a connection unit that electrically connects the first substrate and the second substrate,
Outputting a pixel signal included in the first substrate of the pixel portion included in the solid-state imaging device and generated in a pixel including a photoelectric conversion element to a signal line that supplies the second substrate;
Storing the pixel signal supplied via the signal line in a signal storage circuit included in the second substrate;
Outputting the pixel signal accumulated in the signal accumulation circuit from an output circuit included in the second substrate;
Clip circuit included in the second substrate, the voltage of the pixel No. signal comprises a step of clipping so as not fall below a predetermined voltage,
Including,
A control method for a solid-state imaging device. An imaging apparatus that electrically connects the first substrate and the second substrate by a connection unit that electrically connects the first substrate and the second substrate,
The pixel portion included in the imaging device is
A pixel that is included in the first substrate, includes a photoelectric conversion element, and generates a pixel signal ;
A signal line for supplying said second substrate to said picture No. Motoshin,
A signal storage circuit that is included in the second substrate and stores the pixel signal supplied via the signal line;
An output circuit that is included in the second substrate and outputs the pixel signal stored in the signal storage circuit;
Included in the second substrate, the voltage of the pixel No. signal includes a clip circuit for clipping so as not fall below a predetermined voltage,
Having
An imaging apparatus characterized by that. A solid-state imaging device that electrically connects the first substrate and the second substrate by a connecting portion that electrically connects the first substrate and the second substrate,
The pixel portion included in the solid-state imaging device is
A pixel included in the first substrate and including a photoelectric conversion element;
A first signal line connected to the pixel;
A transistor included in the second substrate and having one end connected to the first signal line;
A capacitor included in the second substrate and connected to the first signal line;
A second signal line connected to the capacitor;
Have
The transistor is
Clip so that the voltage of the first signal line does not become a predetermined voltage or lower,
A solid-state imaging device. The first signal line is
Supplying a signal generated in the pixel to the second substrate;
The capacity is
Accumulates the signal supplied via the first signal line;
The second signal line is
Outputting a signal accumulated in the capacity;
The solid-state imaging device according to claim 2 3, characterized in that. The pixel is
An amplification circuit including an amplification transistor that receives a signal generated by the photoelectric conversion element at a gate and outputs an amplification signal from one of a source and a drain;
The capacity is
Storing the amplified signal amplified by the amplification transistor;
The solid-state imaging device according to claim 2 3, characterized in that. The pixel is
A clamp capacitor connected to one of the source and drain of the amplification transistor directly or indirectly and for clamping the output amplified signal;
A sample and hold transistor connected directly or indirectly to the clamp capacitor to sample and hold the clamped amplified signal;
A noise reduction circuit including
The capacity is
Storing the amplified signal sampled and held by the sample and hold transistor;
26. The solid-state imaging device according to claim 25 . The pixels of the first substrate are
The photoelectric conversion element;
A transfer transistor for connecting a signal generated in the photoelectric conversion element to one of a source and a drain, and outputting a signal generated in the photoelectric conversion element to the other of the source and the drain;
A first amplification transistor that receives a signal output from the transfer transistor at a gate and outputs a first amplification signal from one of a source and a drain;
A first reset transistor for resetting a gate of the first amplification transistor;
Have
The second substrate,
An analog memory circuit having the capacity;
A second amplification transistor that receives a signal of the analog memory circuit at a gate and outputs a second amplified signal from one of a source and a drain;
A second reset transistor for resetting a gate of the second amplification transistor;
Having
The solid-state imaging device according to claims 2 to 4, characterized in that. During the reset period in which the first amplification transistor is reset by the first reset transistor, the transistor clips so that the voltage of the first signal line does not become lower than the first voltage.
The solid-state imaging device according to claim 2 7, characterized in that. A signal generated in the photoelectric conversion element is output from the other of the source and drain of the transfer transistor, and the first signal corresponding to the signal generated in the photoelectric conversion element from one of the source and drain of the first amplification transistor is output. during amplification signal that is output signal period, the voltage of the first signal line by the transistor, clipped so as not fall below the second voltage,
The solid-state imaging device according to claim 2 7, characterized in that. A control method for a solid-state imaging device in which the first substrate and the second substrate are electrically connected by a connection unit that electrically connects the first substrate and the second substrate,
Outputting a signal generated in a pixel including a photoelectric conversion element included in the first substrate of the pixel portion included in the solid-state imaging device to a first signal line connected to the pixel;
Storing the signal output to the first signal line in a capacitor included in the second substrate and connected to the first signal line;
Outputting a signal accumulated in a second signal line connected to the capacitor;
Including
A step of clipping the voltage of the first signal line so that the voltage of the first signal line does not become a predetermined voltage or less by a transistor included in the second substrate and having one end connected to the first signal line; ,
A control method for a solid-state imaging device. An imaging apparatus that electrically connects the first substrate and the second substrate by a connection unit that electrically connects the first substrate and the second substrate,
The pixel portion included in the imaging device is
A pixel included in the first substrate and including a photoelectric conversion element;
A first signal line connected to the pixel;
A transistor included in the second substrate and having one end connected to the first signal line;
A capacitor included in the second substrate and connected to the first signal line;
A second signal line connected to the capacitor;
Have
The transistor is
Clip so that the voltage of the first signal line does not become a predetermined voltage or lower,
An imaging apparatus characterized by that.