JP5845103B2 - Magnetic resonance imaging system - Google Patents

Description

  The present invention is a magnetic resonance imaging (MRI) technique that measures nuclear magnetic resonance (hereinafter referred to as “NMR”) signals from hydrogen, phosphorus, etc. in a subject and visualizes nuclear density distribution, relaxation time distribution, and the like. In particular, the present invention relates to an MRI technique in an MRI apparatus including a plurality of RF receiving coils.

  In an MRI apparatus equipped with a plurality of RF receiving coils (multiple RF receiving coils), reconfigurable CPU boards are arranged in a lattice shape so as to correspond to the number of RF receiving coils, and between adjacent boards in the horizontal and vertical directions There has been proposed a method for realizing the load distribution of the reconfiguration process and increasing the processing speed by enabling the communication (for example, see Patent Document 1).

  In the configuration disclosed in Patent Document 1, a CPU board that performs digital sampling (hereinafter referred to as a sampling board), a CPU board that performs Fourier transform and reconstructs an image (hereinafter referred to as a reconstruction board), and an image. A reconfiguration PC that performs the synthesis process is connected in series. One or more sampling boards and reconstruction boards are provided, and data of a predetermined RF receiving coil (channel) group is processed. The image data of each channel processed by each sampling board and reconstruction board is collected in the reconstruction PC, an image synthesis process is executed, and a final image is output.

JP 2006-218285 A

  In the technique disclosed in Patent Document 1, the load distribution of the reconstruction processing for a plurality of channels from AD data input to image data generation is realized by providing a sampling substrate and a reconstruction substrate for each channel. However, load distribution including image composition processing performed in the reconstruction PC is not considered. In other words, because data is transferred between the hardware connected in series via the network, a waiting time occurs in the CPU of the hardware on the receiving side depending on the processing status on the transmitting side, or conversely, the receiving side Data transfer may be delayed depending on the processing status of the hardware.

  The present invention has been made in view of the above circumstances, and in an MRI apparatus including a multiple RF receiving coil and a plurality of image processing PCs, realizes optimum load distribution in the entire image processing including the final image synthesis. The purpose is to provide technology.

  The present invention distributes processing to each image processing apparatus in consideration of the progress of image processing, the free space of a memory, and the like in an MRI apparatus including a multiple coil including a plurality of receiving coils and a plurality of image processing apparatuses. . The distribution is determined so that the load distribution of each image processing apparatus is optimized so that the processing load is equalized in each image processing apparatus and the stagnation of processing due to insufficient memory does not occur.

  Specifically, the magnetic resonance imaging apparatus includes a multiple coil including a plurality of reception coils and a control unit, wherein the control unit processes signals received by the reception coils, One or more signal processing devices that output data, and a plurality of image processing devices that generate images from data for each of the receiving coils, the one or more signal processing devices and the plurality of image processing devices, The image processing devices are connected so as to be able to transmit and receive data to each other, and each of the image processing devices includes image reconstruction means for reconstructing an image from data for each of the receiving coils, and at least one of the image processing devices For each data for each receiving coil, the load distribution of each image processing device is optimized for the transfer destination device that is an image processing device that reconstructs an image from the data. And further comprising a processing device determining means for notifying the signal processing device that has processed the data for each receiving coil, the signal processing device toward the transfer destination device determined by the processing device determining means, A magnetic resonance imaging apparatus is provided that outputs data for each of the receiving coils.

  According to the present invention, in an MRI apparatus including a multiple RF receiving coil and a plurality of image processing PCs, it is possible to realize optimal load distribution in the entire image processing including the final image synthesis.

It is a block diagram which shows the whole structure of the MRI apparatus of 1st embodiment. It is a system block diagram of the control system in the conventional MRI apparatus. It is explanatory drawing for demonstrating the processing timing of each hardware in the conventional MRI apparatus. It is explanatory drawing for demonstrating the memory overflow which generate | occur | produces when the transfer of data is delayed in the conventional MRI apparatus. It is a system configuration figure of the control processing system of a first embodiment. It is a functional block diagram of the control processing system of a first embodiment. It is a flowchart of processing PC decision processing of a first embodiment. It is a flowchart of the transfer destination PC determination process of 1st embodiment. It is explanatory drawing for demonstrating the processing timing of each image processing PC of 1st embodiment. It is explanatory drawing for demonstrating the processing timing of each hardware of the control processing system of 1st embodiment. It is a system block diagram of the control processing system of 2nd embodiment. It is a system block diagram of the control processing system of 2nd embodiment. It is a flowchart of processing PC decision processing of a second embodiment. It is explanatory drawing for demonstrating the processing timing of each hardware of the control processing system of 2nd embodiment.

<< First Embodiment >>
Hereinafter, a first embodiment to which the present invention is applied will be described. Hereinafter, in all the drawings for explaining the embodiments of the present invention, those having the same function are denoted by the same reference numerals, and repeated explanation thereof is omitted.

  First, an overall outline of an example of the MRI apparatus of the present embodiment will be described. FIG. 1 is a block diagram showing the overall configuration of the MRI apparatus of this embodiment. The MRI apparatus 100 of the present embodiment obtains a tomographic image of a subject using an NMR phenomenon. As shown in FIG. 1, a static magnetic field generation system 120, a gradient magnetic field generation system 130, a transmission system 150, A receiving system 160, a control processing system 170, and a sequencer 140.

  The static magnetic field generation system 120 generates a uniform static magnetic field in the direction perpendicular to the body axis in the space around the subject 101 if the vertical magnetic field method is used, and in the body axis direction if the horizontal magnetic field method is used. The apparatus includes a permanent magnet type, normal conduction type or superconducting type static magnetic field generation source disposed around the subject 101.

  The gradient magnetic field generating system 130 is a gradient magnetic field coil 131 wound in the three-axis directions of X, Y, and Z, which is a coordinate system (apparatus coordinate system) of the MRI apparatus 100, and a gradient magnetic field power source that drives each gradient magnetic field coil. 132, by driving the gradient magnetic field power supply 132 of each gradient coil 131 in accordance with a command from a sequencer 140 described later, gradient magnetic fields Gx, Gy, and Gz are generated in the three axial directions of X, Y, and Z. Apply.

  The transmission system 150 irradiates the subject 101 with a high-frequency magnetic field pulse (hereinafter referred to as “RF pulse”) in order to cause nuclear magnetic resonance to occur in the nuclear spins of the atoms constituting the living tissue of the subject 101. And a high-frequency oscillator (synthesizer) 152, a modulator 153, a high-frequency amplifier 154, and a high-frequency coil (transmission coil) 151 on the transmission side. The high frequency oscillator 152 generates an RF pulse and outputs it at a timing according to a command from the sequencer 140. The modulator 153 amplitude-modulates the output RF pulse, and the high-frequency amplifier 154 amplifies the amplitude-modulated RF pulse and supplies the amplified RF pulse to the transmission coil 151 disposed in the vicinity of the subject 101. The transmission coil 151 irradiates the subject 101 with the supplied RF pulse.

  The receiving system 160 detects a nuclear magnetic resonance signal (echo signal, NMR signal) emitted by nuclear magnetic resonance of the nuclear spin constituting the living tissue of the subject 101, and receives a high-frequency coil (receiving coil) on the receiving side. 161, a signal amplifier 162, a quadrature detector 163, and an A / D converter 164. The reception coil 161 is disposed in the vicinity of the subject 101 and detects an NMR signal of the response of the subject 101 induced by the electromagnetic wave irradiated from the transmission coil 151. The detected NMR signal is amplified by the signal amplifier 162 and then divided into two orthogonal signals by the quadrature phase detector 163 at the timing according to the command from the sequencer 140, and each is digitally converted by the A / D converter 164. It is converted into a quantity and sent to the control processing system 170.

  In this embodiment, the receiving coil 161 is a multiple RF receiving coil composed of a plurality of subcoils. Each subcoil includes a signal amplifier 162, a quadrature phase detector 163, and an A / D converter 164, and an NMR signal converted into a digital quantity is sent to the control processing system 170 for each subcoil.

  The sequencer 140 repeatedly applies RF pulses and gradient magnetic field pulses according to a predetermined pulse sequence. The pulse sequence describes a high-frequency magnetic field, a gradient magnetic field, signal reception timing and intensity, and is stored in the control processing system 170 in advance. The sequencer 140 operates in accordance with an instruction from the control processing system 170 and transmits various commands necessary for collecting tomographic image data of the subject 101 to the transmission system 150, the gradient magnetic field generation system 130, and the reception system 160.

  The control processing system 170 performs control of the entire MRI apparatus 100, calculations such as various data processing, display and storage of processing results, and the like, and includes a CPU. In addition, a storage device 172, a display device 173, and an input device 174 are connected to the control processing system 170. The storage device 172 includes an internal storage device such as a hard disk and an external storage device such as an external hard disk, an optical disk, and a magnetic disk. The display device 173 is a display device such as a CRT or a liquid crystal. The input device 174 is an interface for inputting various control information of the MRI apparatus 100 and control information of processing performed by the control processing system 170, and includes, for example, a trackball or a mouse and a keyboard. The input device 174 is disposed in the vicinity of the display device 173. The operator interactively inputs instructions and data necessary for various processes of the MRI apparatus 100 through the input device 174 while looking at the display device 173.

  Each process of the control processing system 170 is realized by the CPU executing a program held in advance in the storage device 172 in accordance with an instruction input by the operator. For example, when data from the reception system 160 is input to the control processing system 170, the control processing system 170 executes processing such as signal processing and image reconstruction, and displays the tomographic image of the subject 101 as a result thereof. The information is displayed on the device 173 and stored in the storage device 172.

  In the static magnetic field space of the static magnetic field generation system 120 into which the subject 101 is inserted, the transmission coil 151 and the gradient magnetic field coil 131 are opposed to the subject 101 in the case of the vertical magnetic field method and are in the horizontal magnetic field method. It is installed so as to surround the subject 101. Further, the receiving coil 161 is installed so as to face or surround the subject 101.

  Currently, the nuclide to be imaged by the MRI apparatus, which is widely used clinically, is a hydrogen nucleus (proton) that is a main constituent material of the subject 101. In the MRI apparatus 100, information on the spatial distribution of the proton density and the spatial distribution of the relaxation time of the excited state is imaged so that the form or function of the human head, abdomen, limbs, etc. can be expressed two-dimensionally or three-dimensionally. Take an image.

  Prior to description of the detailed configuration of the control processing system 170 of the present embodiment, the configuration of the control processing system 170 disclosed in Patent Document 1 will be described. FIG. 2 is an explanatory diagram for explaining a configuration of a control processing system disclosed in Patent Document 1. In FIG.

  The control processing system is a sampling board 901 that is a CPU board that performs sampling of echo data output from the A / D converter 164, and a CPU board that obtains a reconstructed image by performing Fourier transform on the sampled data. A reconstruction board 902, a measurement control PC 903 that gives an instruction to the sequencer 140, an image composition PC 904 that composes a reconstructed image for each subcoil, and a user interface PC 905 that serves as an interface with the user. Note that one or more sampling substrates 901 and one reconstruction substrate 902 are provided. FIG. 2 illustrates a case where four sampling substrates 901 and four reconstruction substrates 902 are provided. If it is necessary to distinguish the four sampling substrates 901 and the reconstructed substrate 902 from each other, 901 (1), 901 (2), 901 (3), 901 (4), 902 (1), 902 (2 ), 902 (3), and 902 (4), respectively.

  The sampling board 901, the reconstruction board 902, and the image composition PC 904 are connected by a dedicated bus. When a plurality of sampling boards 901 and reconfiguration boards 902 are provided, the image data of each channel processed by the respective sampling boards 901 and reconfiguration boards 902 are collected in the image composition PC 904 via a dedicated communication bus. Then, the image composition process is executed, and the final image is output.

  In the case of the technique disclosed in Patent Document 1, as shown in FIG. 2, three pieces of hardware including a sampling board 901, a reconstruction board 902, and an image composition PC 904 are connected in series. Mutual communication other than the connected hardware is difficult. Therefore, the processing in charge of each hardware is fixed, and the sharing of processing cannot be flexibly changed between hardware.

  The timing of processing of each hardware in this case is as shown in FIG. The data sampled by the sampling board 901 is sent to the reconfigurable board 902 connected thereto, and the image is reconstructed on the reconfiguring board 902 as the destination. Until the reconstruction of the image, the sampling substrate 901 and the reconstruction substrate 902 connected to each sub-coil share the processing. However, the image composition PC 904 cannot perform image composition processing unless image data is transferred from the reconstruction board 902. Therefore, in the technique disclosed in Patent Document 1, an idle time (waiting time) of the CPU as shown in FIG. 3 occurs during the image reconstruction process.

  Further, a reconstruction substrate 902 that performs image reconstruction and an image composition PC 904 that performs post-processing are separately connected in series. For this reason, for example, when parallel imaging development, image correction, and the like are performed as post-processing, the load is high, and thus the memory of the image composition PC 904 is occupied by these processing, and memory shortage may occur. This is shown in FIG.

  When a memory shortage occurs in the image composition PC 904, reception of image data from the reconstruction board 902 is interrupted, and processing of the current image composition PC 904 is preferentially executed. Therefore, image data that cannot be transferred is accumulated in the memory in the reconstruction substrate 902, and there is a possibility that the memory for receiving data from the sampling substrate 901 is insufficient. Also in the reconfigurable board 902, when the memory is insufficient, reception of data (echo) from the sampling board 901 is temporarily stopped. The sampling board 901 stops the echo transmission. Then, the flow of data is stopped, and eventually the memory in the sampling board 901 overflows, causing a system hang-up.

  In the present embodiment, the control processing system 170 reduces the occurrence of such a CPU waiting time and the occurrence of a hang-up due to a memory overflow. A configuration of the control processing system 170 of the present embodiment that realizes this will be described. FIG. 5 is an explanatory diagram for explaining the configuration of the control processing system 170 of the present embodiment. The control processing system 170 of this embodiment includes a DRF board 210, an image processing PC 220, and a user interface PC (UI-PC) 230.

  Each hardware constituting the control processing system 170 such as each DRF board 210, the image processing PC 220, and the UI-PC 230 is connected in a manner capable of transmitting / receiving data to / from each other. Here, the hardware is connected in a star topology with the hub 240 as the center. The DRF board 210 is connected to the A / D converter 164 through a digital data transmission path corresponding to the number of subcoils (channels).

  The DRF board 210 is a signal processing device that performs various signal processing operations on digital data for each subcoil (channel) received from the A / D converter 164 and transfers the digital data to the image processing PC 220. The destination image processing PC 220 is instructed by the specific image processing PC 220. Details of the transfer destination determination will be described later. In the present embodiment, data to be transmitted is packetized, information specifying the destination image processing PC 220 is attached, and the data is transmitted to the destination image processing PC 220 via the hub 240. The various signal processing operations performed here are, for example, QD detection, resampling, and addition of position information to resampling data. The position information is used for arranging in the k space. The DRF board 210 includes a memory mounted as a system area in which an OS and execution modules are stored and a primary area for computation used in signal processing computation.

  The control processing system 170 according to this embodiment includes the DRF board 210 in a number that can process data of all channels. Each DRF board 210 is connected to an A / D converter 164 for the number of channels processed by the DRF board 210. That is, when one DRF substrate 210 can process n channels and the number of all channels is N (n and N are both natural numbers), Ceil (N / n) (Ceil (x) is the minimum of x or more) The number of DRF substrates 210 is a function that returns an integer. In FIG. 5, as an example, the case where the number of subcoils (channels) is 20 and the DRF substrate 210 can process 5 channels is illustrated. Accordingly, four DRF substrates 210 are provided. The DRF substrate 210 that performs processing for each channel is determined in advance.

  The image processing PC 220 is an image processing apparatus that performs various image processing operations on data processed by the DRF board 210. In the present embodiment, for example, in addition to image processing such as image reconstruction processing, correction processing, and post-processing, measurement control is also performed. The image processing PC 220 according to the present embodiment includes the functions of the reconstruction substrate 902, the image composition PC 904, and the measurement control PC 903 disclosed in Patent Document 1. The control processing system 170 of this embodiment includes at least two image processing PCs 220. FIG. 5 illustrates a case where two are provided as an example.

  Further, the image processing PC 220 determines a transfer destination of data processed by the DRF board 210 and an image processing PC 220 that performs post-processing such as image composition processing for each channel. In order to realize this, as shown in FIG. 6, the image processing PC 220 of the present embodiment includes an image processing unit 221, a memory free space detection unit 222, a processing status detection unit 223, a processing PC determination unit 224, A measurement control unit 225.

  The image processing unit 221 performs various image processing operations on the data sent from the DRF board 210 to obtain an image. The image processing calculation performed here includes Fourier transform (image reconstruction processing), correction processing, post-processing, and the like. The image processing unit 221 stores the data for each channel transmitted from the DRF board 210 in the k-space memory area for each channel, performs Fourier transform, and reconstructs the image. As a result, the image processing unit 221 obtains images for the number of channels. Correction processing is performed on the obtained image as necessary.

  Furthermore, when the image processing PC 220 is determined to be a post-processing execution PC described later, the image processing unit 221 receives an image for each channel from the other image processing PC 220 and performs post-processing. The post-processing performed here is, for example, MAC synthesis or parallel imaging development.

  The memory free capacity detection unit 222 detects the free capacity of the memory 229 provided in its own image processing PC 220. The free space is detected, for example, using a request from the image processing PC 220 including the processing PC determination unit 224 described later as a trigger. Then, the detection result is notified to the requesting image processing PC 220. If the image processing PC 220 is the request source, the detection result is notified to the processing PC determination unit 224 of the request source.

  The processing status detection unit 223 determines whether or not a predetermined process is being executed in its own image processing PC 220. In the present embodiment, the process for which the execution status is to be determined is a process that may use a large memory capacity, such as an image reconstruction process or a post process. The process to be determined is determined in advance. For example, in the present embodiment, the processing to be determined is image reconstruction processing (Fourier transform) and post-processing.

  In response to the inquiry, the processing status detection unit 223 detects whether or not the image processing PC 220 of the image processing PC 220 executes the determination target process, and notifies the inquiry processing image processing PC 220 of a flag corresponding to the detection result. In response to the inquiry, the processing status detection unit 223 outputs, as a detection result, a flag indicating either of the image reconstruction processing or post-processing that is not being executed. The determination is performed using, for example, a request from the image processing PC 220 including the processing PC determination unit 224 described later as a trigger.

  The processing PC determination unit 224 determines, for each subcoil (channel), an image processing PC (transfer destination PC) 220 that performs image processing on data acquired by the subcoil, and also performs an image processing PC (postprocessing). Processing execution PC) 220 is determined. The processing for determining the image processing PC 220 (processing PC determination processing) is performed immediately before the start of measurement for each measurement.

  Image processing is performed on data after signal processing is performed on each DRF board 210. Accordingly, when the image processing PC (transfer destination PC) 220 that processes data for each channel is determined, the processing PC determination unit 224 sends the processed data to the DRF board 210 as the transfer destination of the processed data. Information specifying the determined transfer destination PC 220 is notified. Upon receiving this notification, the DRF board 210 sends the processed data with the transfer destination PC 220 as the destination.

  In addition, when the image processing PC (post-processing PC) 220 that performs post-processing is determined, the processing PC determination unit 224 transmits information specifying the determined post-processing PC 220 as a transfer destination of processed data to all the image processing PCs 220. Notice.

  The processing PC determination unit 224 performs the image reconstruction processing (Fourier transform processing), correction processing, and post-processing on the data for each channel so that the load on each image processing PC 220 is as even as possible and the memory is insufficient. Is assigned to each image processing PC 220 so as not to occur. That is, the processing is distributed so that the CPU idle time of each image processing PC 220 is reduced and resources are efficiently used. The sorting is performed according to the free capacity of the memory 229 of each image processing PC 220 and the processing status.

  In order to obtain information on the free capacity of the memory 229 and the processing status, the processing PC determination unit 224 inquires of all the image processing PCs 220 in the control processing system 170 about the free capacity and processing status of the memory 229. The processing PC determination unit 224 determines the image processing PC 220 to which the data of each channel is transferred and the image processing PC 220 to perform post-processing according to the inquiry result, and notifies each DRF board 210 of the determined result. Details of the determination method will be described later.

  The measurement control unit 225 controls measurement by the MRI apparatus 100. The image processing PC 220 including the measurement control unit 225 is directly connected to the sequencer 140. Then, a command is output to the sequencer 140 in accordance with the pulse sequence stored in the storage device 172 in advance and the imaging parameters input from the user.

  Note that each of the processing PC determination unit 224 and the measurement control unit 225 only needs to be included in one image processing PC 220. In FIG. 6, as an example, a case where the control processing system 170 includes two image processing PCs 220 and only one image processing PC 220 includes a processing PC determination unit 224 and a measurement control unit 225 is illustrated.

  Each function of the image processing PC 220 is realized by a CPU included in each image processing PC 220 loading a program stored in advance in the storage device 172 or the like into the memory and executing it.

  The UI-PC 230 is responsible for interface processing with the user. A display device 173 and an input device 174 are connected to the UI-PC 230. An instruction from the user to the control processing system 170 is received via the input device 174, and the processing result in the control processing system 170 is displayed on the display device 173 and presented to the user. The user uses the display device 173 and the input device 174 to input various instructions to the control processing system 170 and confirm the processing results in the control processing system 170.

  Next, processing PC determination processing by the processing PC determination unit 224 will be described. In this embodiment, each image processing PC 220 is inquired about the free capacity of the memory 229 and the processing status, and only the image processing PC 220 (hereinafter referred to as non-processing PC) 220 that is not executing the processing to be inquired has all channels. Distribute processing evenly. That is, in the present embodiment, the image processing PC 220 that is executing some processing continues to concentrate on the current processing. This process PC determination process is basically executed immediately before the start of each measurement (scan).

  If all the image processing PCs 220 are executing the processing to be inquired, or if the processing PC determination processing is performed based on the inquiry result and a result indicating that distribution is impossible is obtained, the scan is not started. , Wait. In the case of the waiting state, in this embodiment, the processing PC determination unit 224 inquires about the free space of the memory 229 and the processing status every predetermined time, and performs the processing PC determination process again.

  The above processing flow will be specifically described according to the processing flow. FIG. 7 is a processing flow of the processing PC determination processing of this embodiment.

  The processing PC determination unit 224 first determines the type of measurement from the set imaging parameter (step S1101). Then, the size (memory capacity) of the memory area required for the measurement is calculated (step S1102). Necessary memory areas are a memory area (k-space memory size Mk) for developing data for image reconstruction, and a memory area size Mo required for the measurement type.

  For example, when performing parallel imaging in which the acquired data is thinned out and measured, and the aliasing is expanded using the sensitivity distribution, it is necessary to enlarge the image size and create a sensitivity map for the number of slices for post-processing. These memory areas Mo are required. Note that data that can be calculated in these memory areas from the set imaging parameters is stored in the storage device 172 in advance.

  Next, the processing PC determination unit 224 inquires each image processing PC 220 about the current memory free capacity and processing status (step S1103). Here, each image processing PC 220 receives the inquiry, and the memory free space detector 222 detects the free space Ms of its own memory 229. The processing status detection unit 223 detects the execution status of a predetermined process. Then, the detection result is returned to the inquiring image processing PC 220 together with information specifying the image processing PC 220 of its own. At this time, also in the inquired image processing PC 220 itself, the memory free space detection unit 222 detects the free space and processing status of its own memory 229.

  Note that, in the image processing PC 220 that is determined in advance to perform processing necessary according to the measurement type, a capacity obtained by removing the memory size Mo required according to the measurement type from the free capacity Ms of the memory 229. The memory free capacity Ms. The processing required according to the measurement type is, for example, sensitivity map generation processing in the case of parallel imaging.

  When the notification of the free space Ms of the memory 229 and the detection result of the process being executed are received from each image processing PC 220 including itself (step S1104), the processing PC determination unit 224 uses these pieces of information for each channel. An image processing PC (transfer destination PC) 220 that performs image reconstruction processing and an image processing PC (post-processing PC) 220 that performs post-processing are determined from the data of the channel.

  In the present embodiment, the processing PC determination unit 224 first determines the presence / absence of an image processing PC (non-processing PC) 220 that is not executing any processing to be determined from the processing execution status reply (step S1105). ). If there is a non-processing PC 220, a transfer destination PC determination process for determining a data transfer destination PC 220 for each channel in the non-processing PC 220 is performed (step S1106). Details of the transfer destination PC determination process will be described later.

  If there is no non-processing PC 220 in step S1105, and if distribution is not possible and transfer destination PC 220 cannot be determined in step S1106 (distribution is impossible), after a predetermined time (T) (step S1110), Returning to step S1103, the non-processing PC 220 is again inquired about the free capacity of the memory 229 and the processing status.

  When the transfer destination is determined in the transfer destination PC determination process, the process PC determination unit 224 first performs a post process PC determination process for determining the post process PC 220 (step S1108). Details of the post-processing PC determination processing will be described later.

  Then, the processing PC determination unit 224 notifies the DRF board 210 that processes the data from each channel of the information (for example, identifier n) for specifying the determined transfer destination PC 220, and notifies the all image processing PCs 220 later. Information specifying the processing PC 220 is notified (step S1109). Then, the process ends.

  Next, details of the transfer destination PC determination processing in step S1106 by the processing PC determination unit 224 will be described. In this embodiment, the number of channels to be processed by each non-processing PC 220 is determined, each channel is assigned to each non-processing PC 220 in a predetermined order according to the determined number of channels, and each transfer destination PC 220 is determined. For example, in order from the non-processing PC 220 with the smallest identification number, the determined number of channels is assigned in order from the channel with the smallest identification number.

  The outline of the method for determining the number of channels to be processed by each non-processing PC 220 is as follows. First, the maximum number of channels Cmax that can be processed in each non-processing PC 220 is calculated from the free capacity Ms of the memory 229 of each non-processing PC 220 and the calculated memory size Mk of the k space. In addition, the number of channels Cproc to be processed by each non-processing PC 220 in the case of equally allocating to each non-processing PC 220 is calculated.

  When the maximum number of channels Cmax that can be processed by each non-processing PC 220 is equal to or larger than the number of channels Cproc to be processed by each non-processing PC 220, the number of channels Cporc to be processed is allocated to each non-processing PC 220. On the other hand, if there is a non-processed PC 220 whose maximum channel number Cmax is smaller than the channel number Cproc to be processed, the number of channels corresponding to the maximum number Cmax is allocated to the non-processed PC 220 whose Cmax is smaller than Cproc. The number of channels is evenly distributed to the remaining non-processing PCs 220.

  If the memory area is insufficient and distribution is not possible, the processing is terminated as allocation impossible.

  A specific flow of the above processing will be described. FIG. 8 is a processing flow of transfer destination PC determination processing. Here, M is the number of non-processing PCs 220 for which the number of processing channels has not been determined, and N is a counter that counts the number of unallocated channels.

  First, the processing PC determination unit 224 substitutes initial values for the counters M and N (step S1201). Here, the number of non-processing PCs 220 extracted in step S1105 is substituted for M. N substitutes the total number of channels. Each non-processing PC 220 is identified by an identifier m (m = 1, 2, 3,... M; M and m are integers of 1 or more).

Next, the processing PC determination unit 224 can process each non-processing PC 220 (m) according to the following equation (1) using the free capacity Ms (m) of the memory 229 of each non-processing PC 220 (m). The maximum number of channels Cmax (m) is calculated (step S1202).
Cmax (m) = Ceil (Ms (m) / Mk) (1)
Ceil (x) is a function that returns the smallest integer equal to or greater than x.

Next, the processing PC determination unit 224 uses the number N of unallocated channels and the number M of non-processing PCs 220 (m), and the channels to be processed by each non-processing PC 220 (m) according to the following equation (2). The number Cproc is calculated (step S1203).
Cproc = Ceil (N / M) (2)

Then, the processing PC determination unit 224 determines whether or not even distribution is possible (step S1204). Here, it is determined whether or not the following expression (3) is satisfied for all unprocessed PCs 220 (m).
Cmax (m) ≧ Cproc (3)

  When all the non-processing PCs 220 (m) satisfy the above formula (3), the processing PC determination unit 224 performs an even distribution in which channels are allocated to each non-processing PC 220 (m) by Cproc, which is the number of channels to be processed. In step S1205, according to a predetermined rule, the channel is associated with the image processing PC 220 of the transfer destination, and the image processing PC (transfer destination PC) 220 of the data transfer destination for each channel is determined.

  On the other hand, when there is a non-processing PC 220 (m) that does not satisfy Expression (3), that is, when there is a non-processing PC 220 (m) whose maximum number of channels Cmax (m) that can be processed is smaller than Cproc, the processing PC determination unit 224 Are assigned to each non-processing PC 220 (m) where Cmax (m) <Cproc is the maximum number of channels that can be processed by the non-processing PC 220 (m), that is, Cmax (m) (step S1206). Then, M and N are updated to the number of unprocessed non-processing PCs 220 and the number of unallocated channels, respectively (step S1207).

  Then, it is determined whether or not the number of undetermined non-processing PCs 220 is 0 and an unassigned channel remains (step S1208). If this is satisfied, that is, if M = 0 and N> 0, it is determined that distribution is not possible (step S1209), and the process ends. In other cases, the process returns to step S1203, and the process is repeated using the updated M and N.

  Next, details of the post-processing PC determination process by the processing PC determination unit 224 of this embodiment will be described.

  First, in the transfer destination PC determination process, when the transfer destination of data of all channels is determined to be one image processing PC 220, the image processing PC 220 that performs the process is also determined to perform post-processing. On the other hand, when the transfer destination is over a plurality of image processing PCs 220, it is determined that the transfer is performed by a predetermined image processing PC 220. The predetermined image processing PC 220 is, for example, the image processing PC 220 that performs processing PC determination processing.

  In this embodiment, for each measurement, the data transfer destination PC 220 of each channel obtained by the measurement is determined. During the measurement of 1, the transfer destination PC 220 is maintained without being changed.

  The distribution of processing to each hardware when performing multiple measurements by the control processing system 170 of the present embodiment having the above functions will be described with a specific example. Here, normal measurement is performed as the first measurement (Scan1), then parallel imaging is performed as the second measurement (Scan2), and normal measurement is performed as the third measurement (Scan3). An example will be described. Each measurement is executed according to a measurement start instruction from the UI-PC 230.

  Here, the receiving coil 161 is a 32-channel coil including 32 subcoils. In addition, four DRF boards 210 (210 (1), 210 (2), 210 (3), 210 (4)) are provided, and the DRF board 210 (1) digitally processes 1 to 8 channel data, The DRF board 210 (2) digitally processes 9-16 channel data, the DRF board 210 (3) digitally processes 17-24 channel data, and the DRF board 210 (4) 25-32 channels. These data are digitally processed.

  The number of image processing PCs 220 is two (220 (1), 220 (2)). It is assumed that the image processing PC 220 (2) includes the processing PC determination unit 224 and is set as the post-processing PC 220. Further, the free capacity of the memory 229 of each of the image processing PCs 220 (1) and 220 (2) when image processing such as image reconstruction and post-processing is not performed is represented by Ms (1) and Ms (2), respectively. To do. Ms (1) and Ms (2) are both capacities capable of image reconstruction processing for all channels (Mk × 32 or more memory capacity).

  FIG. 9 is a time chart of processing of each image processing PC 220 of the present embodiment. FIG. 10 is a time chart of the processing of each DRF substrate 210 and each image processing PC 220 in Scan1.

  When receiving an instruction to start measurement of Scan 1 via the UI-PC 230, the processing PC determination unit 224 of the image processing PC 220 (2) performs a processing PC determination process. First, as described above, the processing PC determination unit 224 inquires of all connected image processing PCs 220 about the free capacity of the memory 229 and the execution status of the processing. In the example of FIG. 9, the image processing PC 220 (1) is inquired to detect itself.

  Here, since the measurement process has not been executed immediately before, the execution status of the process receives a reply that neither the image processing PC 220 (1) nor the image processing PC 220 (2) is executing. . Also, Ms (1) and Ms (2) are received as the free memory capacity.

  The processing PC determination unit 224 determines the image processing PC 220 that processes the data of each channel. Here, since the maximum number of channels that can be processed by any of the image processing PCs 220 is equal to or greater than the total number of channels, they are equally distributed to both. In other words, the data transfer destination PC 220 from the 1st channel to the 16th channel is assigned as the image processing PC 220 (1), and the data transfer destination PC 220 from the 17th channel to the 32nd channel is assigned as the image processing PC 220 (2) (self). Then, according to the assignment, the transfer destination PC 220 is notified to the DRF board 210 that processes data from each channel.

  Further, the processing PC determination unit 224 determines the post-processing PC 220 by the above method and notifies each image processing PC 220 of the post-processing PC 220.

  When receiving the notification from the transfer destination PC 220, the DRF board 210 places the data received from the A / D converter 164 on the memory and executes digital filter processing such as QD detection and resampling. Then, after the digital filter processing is completed, the DRF board 210 transmits it to the transfer destination PC 220 notified in advance via the network.

  During measurement, data is continuously transferred from each DRF board 210 to the two image processing PCs 220 (1) and 220 (2) until the measurement is completed.

  Further, when the two image processing PCs 220 (1) and 220 (2) receive data from the DRF board 210, they are immediately stored in the k-space memory area, and the data necessary for generating one image is stored in the k-space. The Fourier transform (image reconstruction process) is performed at the timing when the filling is completed. Eventually, image data corresponding to the number of channels distributed equally is stored in each image processing PC 220.

  As shown in FIG. 10, each image processing PC 220 executes an image reconstruction process during measurement. Therefore, idle time does not occur during this period.

  When image reconstruction for all channels is completed, the other image processing PC 220 transmits all images to a predetermined post-processing PC 220. Here, since the post-processing PC 220 is determined as the image processing PC 220 (2), the image processing PC 220 (1) transmits all the reconstructed images to the image processing PC 220 (2).

  In response to this, the post-processing PC 220 (here, the image processing PC 220 (2)) performs post-processing (image synthesis processing in Scan1).

  When the scan start instruction for Scan2 is given after Scan1, the process PC determination unit 224 determines the process PC for Scan2. It is assumed that the image measurement processing for normal measurement is completed in this predetermined time.

  As described above, Scan2 is parallel imaging. Therefore, it is necessary to create a sensitivity map during measurement. The memory capacity Mo necessary for creating the sensitivity map is calculated. Here, the sensitivity map creation is performed by the image processing PC 220 (2). Accordingly, the free memory capacity Ms (2) of the image processing PC 220 (2) is obtained by subtracting the memory capacity Mo necessary for creating the sensitivity map from the detected free memory capacity Ms (2), that is, Ms (2) = Detected Ms (2) −calculated Mo.

  First, the processing PC determination unit 224 inquires all the image processing PCs 220 about the free capacity of the memory 229 and the execution status of the processing. As described above, since the image composition processing of Scan1 has been completed, there is no image processing PC 220 that performs any processing. Therefore, processing PC determination processing is performed according to the free memory capacity of all image processing PCs 220, and the data transfer destination PC 220 and post-processing PC 220 for each channel are determined. The determination result is notified to each DRF board 210 and each image processing PC 220.

  Here, it is assumed that the data transfer destination PC 220 for the 1 to 24 channel data is the image processing PC 220 (1), and the data transfer destination PC 220 for the 25 to 32 channel data is the image processing PC 220 (2). The image processing PC 220 (2) also generates a sensitivity map.

  When the image reconstruction processing is completed, the image processing PC 220 (1) transmits all the images to the image processing PC 220 (2). The image processing PC 220 (2) performs post-processing. Here, the expansion process is performed using the entire image and the sensitivity map.

  When the scan start instruction for Scan3 is given after Scan2, the process PC determination unit 224 performs the process PC determination process for Scan3. At this time, it is assumed that the expansion process has not ended.

  When determining the processing PC for Scan 3, the processing PC determination unit 224 inquires of each image processing PC 220 about the free capacity of the memory 229 and the execution status of the processing. Each image processing PC 220 returns the free capacity of the memory 229 at the time of receiving its inquiry and the execution status of the processing to the image processing PC 220 as the inquiry source.

  Here, the image processing PC 220 (1) returns Ms (1) as the free capacity of the memory 229. On the other hand, the memory free space detection unit 222 of the image processing PC 220 (2) detects the free space Ms (2) of the memory 229 at that time, and the processing status detection unit 223 has not yet performed the parallel imaging development of Scan2. Therefore, it is detected that post-processing is in progress.

  Accordingly, the processing PC determination unit 224 determines that the non-processing PC 220 is only the image processing PC 220 (1), and determines that the image processing PC 220 (1) performs the image reconstruction processing of the data of all channels. Then, the determination result is notified to each DRF board 210. In Scan 3, since the image reconstruction processing of all channel data is performed by the image processing PC 220 (1), it is determined that the composition processing (post-processing) is also performed by the image processing PC 220 (1).

  Upon receipt of the notification, the DRF board 210 performs digital signal processing and transmits it to the image processing PC 220 (1) each time it receives Scan 3 data from the A / D converter 164. The image processing PC 220 (1) arranges the data in the k space each time data is received, and when data that can reconstruct one image is filled, Fourier transform is performed to reconstruct the image. Furthermore, in Scan3, image composition processing as post-processing is also performed by the image processing PC 220 (1). Therefore, the image processing PC 220 (1) performs image composition processing as it is after completing the image reconstruction processing of all images.

  As described above, in this embodiment, the image reconstruction process is not assigned to the image processing PC 220 (2) performing some kind of processing. Therefore, the memory 229 of the image processing PC 220 (2) is occupied by the processing being performed, and reception of data from the DRF board 210 is not interrupted.

  As described above, the magnetic resonance imaging apparatus 100 according to the present embodiment includes the multiple coil 161 including a plurality of reception coils and the control processing system 170, and the control processing system 170 receives signals from the reception coils. One or more DRF boards 210 that respectively process signals and output data for each receiving coil, and a plurality of image processing PCs 220 that generate images from the data for each receiving coil, the one or more DRF boards 210 And the plurality of image processing PCs 220 are connected so as to be able to transmit / receive data to / from each other, and each of the image processing PCs 220 includes an image processing unit 221 that reconstructs an image from data for each of the receiving coils. For each measurement, the image processing PC 220 performs an image from the data for each reception coil. The processing PC determination unit 224 that determines the transfer destination PC 220, which is the image processing PC 220 to be reconfigured, to optimize the load distribution of each image processing PC 220 and notifies the DRF board 210 that has processed the data for each reception coil. The DRF board 210 outputs data for each reception coil toward the transfer destination PC 220 determined by the processing PC determination unit 224.

  Each of the image processing PCs 220 includes a memory free space detection unit 222 that detects the free space of the memory 229 included in the image processing PC 220 and notifies the processing PC determination unit 224 of the detection, and the processing PC determination unit 224 includes the image processing PC 220. The transfer destination PC 220 is determined on the basis of the free space notified from. The image processing PC 220 further includes a processing status detection unit 223 that detects a processing status of the image processing PC 220 and notifies the processing PC determination unit 224 of the detection result, and the processing PC determination unit 224 includes: The transfer destination PC 220 is determined in consideration of the processing status notified from each image processing PC 220.

  For this reason, according to the present embodiment, the image processing PC 220 that processes the data of each channel is determined for each measurement according to the processing status of each image processing PC 220 and the availability of the memory 229. It has a function for exchanging information on processing status and processing capability between the image processing PCs 220 and has a configuration capable of transferring data from any DRF board 210 to an arbitrary image processing PC 220. In addition, the optimum processing distribution can be determined flexibly. Accordingly, the CPU idle time of the image processing PC 220 can be reduced, and occurrence of memory shortage can be reduced.

  Thus, according to the present embodiment, in the control processing system 170, the hardware resources provided in the control processing system 170 can be efficiently used, and the overall processing time can be reduced. Therefore, optimal load distribution can be realized for the entire reconstructed image acquisition process from the output from the AD converter 164 to the final image generation.

  In this embodiment, when the free memory of all the non-processing PCs 220 satisfies Expression (3), channels are allocated to all the image processing PCs 200 evenly. However, the distribution of the processing channels is not limited to this. I can't. For example, the number of channels may be assigned according to the free memory capacity ratio of each image processing PC 220.

  In the present embodiment, the processing of data from all channels is distributed only to the non-processing PC 220, but the present invention is not limited to this. Including the image processing PC 220 that performs some processing, the number of channels may be distributed according to the free capacity ratio of the memory 229.

<< Second Embodiment >>
Next, a second embodiment to which the present invention is applied will be described. In this embodiment, a large-capacity storage is provided on the DRF board to avoid a system hang-up due to a memory shortage.

  The MRI apparatus 100 of this embodiment basically has the same configuration as that of the first embodiment. The configuration of the control processing system 170 of this embodiment is shown in FIG. The configuration of the control processing system 170 of this embodiment is basically the same as that of the first embodiment. However, as described above, in this embodiment, each DRF board 210 further includes a large-capacity storage 211. Therefore, in the present embodiment, the function relating to the large-capacity storage 211 is different from that in the first embodiment. Hereinafter, the present embodiment will be described focusing on the configuration different from the first embodiment.

  FIG. 12 is a functional block diagram of the image processing PC of the present embodiment. As shown in the figure, the image processing PC 220 of this embodiment includes an image processing unit 221, a memory free space detection unit 222, a processing PC determination unit 224, a measurement control unit 225, and a memory monitoring unit 226. Prepare. The image processing unit 221, the memory free space detection unit 222, and the measurement control unit 225 have the same functions and configurations as those of the first embodiment.

  Also in the present embodiment, the processing PC determination unit 224 and the measurement control unit 225 may each include one image processing PC 220. In FIG. 12, as an example, a case where the control processing system 170 includes two image processing PCs 220 and only one of the image processing PCs 220 includes a processing PC determination unit 224 and a measurement control unit 225 is illustrated.

  The memory monitoring unit 226 monitors a change in the free capacity of the memory 229 of the self-image processing PC 220, and detects shortage and elimination of the shortage. When the shortage of the free space in the memory 229 and the elimination thereof are detected, the memory monitoring unit 226 notifies the DRF board 210. Notification is made via the hub 240. Note that the DRF board 210 that is the notification partner is the DRF board 210 that is the data transfer destination.

  As in the first embodiment, the processing PC determination unit 224 according to the present embodiment determines an image processing PC 220 that performs image processing on data acquired by the sub-coil for each sub-coil (channel) and performs post-processing. An image processing PC is determined. However, in this embodiment, the determination method of the image processing PC 220 that processes data from each channel because the DRF board 210 includes the large-capacity storage 211 and the image processing PC 220 does not include the processing status detection unit 223. Is different.

  FIG. 13 shows the flow of processing PC determination processing by the processing PC determination unit 224 of this embodiment. The processing PC determination processing of this embodiment is basically the same as the processing flow of the first embodiment shown in FIG. However, since the processing status is not inquired, only the memory free capacity is inquired in step S1103. There is no step S1105.

  Further, in the transfer destination PC determination process of the present embodiment, only the answer of the free space in the memory 229 is used, the number of channels distributed to each image processing PC 220 is determined, and the transfer destination PC 220 is determined. For example, in the process of FIG. 8 of the first embodiment, all the image processing PCs 220 are set as non-processing PCs 220 and the transfer destination PC 220 is determined.

  The DRF substrate 210 includes the large-capacity storage 211 as described above. In addition to the function of the DRF board 210 of the first embodiment, the DRF board 210 of the present embodiment receives data from the memory monitoring unit 226 of the transfer destination PC 220 that the memory 229 is insufficient, and transfers data. Interrupt. In addition, upon receiving a notification of shortage resolution, data transfer is resumed. Furthermore, the DRF board 210 according to the present embodiment also monitors the free space of its own memory during data transfer, and changes the data storage destination to the large-capacity storage 211 if it becomes insufficient.

  Next, the processing by each hardware at the time of execution of multiple measurements by the control processing system 170 of the present embodiment will be described with a specific example. Here, a case where normal measurement is performed as the first measurement (Scan1) and the second measurement (Scan2) will be described as an example. However, it is assumed that the scan 1 has a large image size, a large number of slices, and takes time for Fourier transform processing (image reconstruction processing). The number of channels, the number of DRF substrates 210, and the number of image processing PCs 220 are the same as in the example of the first embodiment.

  Upon receiving an instruction to start Scan 1 via the UI-PC 230, the processing PC determination unit 224 performs processing PC determination processing, as in the first embodiment, and determines the data transfer destination PC 220 and post-processing PC 220 for each channel. . Then, the determination result is notified to each DRF board 210 and each image processing PC 220.

  Upon receiving the notification, each DRF board 210 performs a signal processing operation on the data received from the A / D converter 164 and sends it to the transfer destination PC 220. Further, when each image processing PC 220 receives data from the DRF board 210, each image processing PC 220 arranges the data in the k space, performs Fourier transform, and reconstructs the image (performs Fourier transform).

  In the present embodiment, as described above, since the size of the image data of Scan1 is large, the Fourier transform takes time. Accordingly, at the start of Scan2, any image processing PC 220 is in the process of image reconstruction.

  When it is time to start Scan2, the processing PC determination unit 224 inquires all the image processing PCs 220 about the availability of the memory 229 and determines the image processing PC 220 that processes data for each channel. As shown in FIG. 14, at the start of Scan2, each image processing PC 220 performs Fourier transform, and therefore the memory 229 is insufficient after a predetermined time.

  In each image processing PC 220, when the memory monitoring unit 226 detects that the free memory capacity is insufficient, the memory monitoring unit 226 instructs the DRF board 210 that is transferring data to the image processing PC 220 to stop the data transfer.

  Upon receiving the instruction, the DRF board 210 stops data transmission, and first stores the acquired data in a memory that is normally provided. When the memory becomes full (memory shortage occurs in the DRF board 210), the acquired data is temporarily stored in its own mass storage 211. The storage is continued until an instruction to resume data transmission is received from the memory monitoring unit 226.

  The memory monitoring unit 226 continues to monitor the free memory capacity. Then, when it is detected that the free memory capacity has become a sufficient amount for performing the Fourier transform, an instruction is issued to the DRF board 210 that is transferring data to the image processing PC 220 to resume data transfer. In response to the instruction, the DRF board 210 resumes data transfer.

  In FIG. 14, since the initial free memory capacity of each image processing PC 220 is the same amount and distributed so as to process data of the same number of channels, the timing at which the memory shortage of each image processing PC 220 occurs is the same. However, it is not limited to this.

  As described above, the magnetic resonance imaging apparatus 100 according to the present embodiment includes the multiple coil 161 including a plurality of reception coils and the control processing system 170, and the control processing system 170 receives signals from the reception coils. One or more DRF boards 210 that respectively process signals and output data for each receiving coil, and a plurality of image processing PCs 220 that generate images from the data for each receiving coil, the one or more DRF boards 210 And the plurality of image processing PCs 220 are connected so as to be able to transmit / receive data to / from each other, and each of the image processing PCs 220 includes an image processing unit 221 that reconstructs an image from data for each of the receiving coils. For each measurement, the image processing PC 220 performs an image from the data for each reception coil. The processing PC determination unit 224 that determines the transfer destination PC 220, which is the image processing PC 220 to be reconfigured, to optimize the load distribution of each image processing PC 220 and notifies the DRF board 210 that has processed the data for each reception coil. The DRF board 210 outputs data for each reception coil toward the transfer destination PC 220 determined by the processing PC determination unit 224.

  Each of the image processing PCs 220 includes a memory free space detection unit 222 that detects the free space of the memory 229 included in the image processing PC 220 and notifies the processing PC determination unit 224 of the detection, and the processing PC determination unit 224 includes the image processing PC 220. The transfer destination PC 220 is determined on the basis of the free space notified from. Further, the DRF board 210 further includes a large-capacity storage 211, and the image processing PC 220 detects the occurrence and elimination of a shortage of the free space of the memory 229 included in the DRF board 210, and the data transmission source of each reception coil The DRF board 210 further includes a memory monitoring unit 226 for notifying the DRF board 210. When the DRF board 210 receives a notification of insufficient free space in the memory 229 from the memory monitoring section 226, the processed data is transferred to the mass storage 211. When the storage is received and the notification of lack of memory is received from the memory monitoring unit 226, transmission is resumed from the data stored in the mass storage 211.

  Thus, according to the present embodiment, the image processing PC 220 that processes the data of each channel is determined for each measurement according to the availability of the memory 229 of each image processing PC 220. In addition to having a function for exchanging information on the free memory capacity between the image processing PCs 220, and having a configuration capable of transferring data from any DRF board 210 to any image processing PC 220, it is flexible and flexible for each measurement. The optimal processing distribution can be determined.

  In addition, according to the present embodiment, each DRF board 210 includes the large-capacity storage 211 and can temporarily store data, so that memory overflow in the DRF board 210 can be avoided. That is, the data from the A / D converter 164 does not overflow.

  Therefore, according to the present embodiment, the CPU idle time of the image processing PC 220 can be reduced, and the stagnation of processing due to a memory shortage can be reduced. Thus, according to the present embodiment, in the control processing system 170, the hardware resources provided in the control processing system 170 can be efficiently used, and the overall processing time can be reduced. Therefore, optimal load distribution can be realized for the entire reconstructed image acquisition process from the output from the AD converter 164 to the final image generation.

  The large-capacity storage 211 may be used for the purpose of executing a correction process after accumulating a certain amount of data in the DRF board 210 in addition to a function as a buffer for avoiding a mere overflow of memory. . Depending on the function, it may be advantageous to perform correction processing or the like in a certain unit of data in the DRF board 210 before transferring to the image processing PC 220. It is effective in such a case.

  Also in the present embodiment, the control processing system 170 includes the processing status detection unit 223 as in the first embodiment, and the processing PC determination unit 224 determines the processing PC as in the first embodiment. It may be configured.

  In each of the above-described embodiments, the processing PC determination unit 224 is configured to inquire the free capacity of the memory 229 from each image processing PC 220 and obtain the information, but is not limited thereto. For example, the maximum number of channels Cmax that can be processed may be inquired. In this case, each image processing PC 220 acquires in advance information on the memory size of the k-space area used for measurement, and calculates the maximum number of channels that can be processed from the detected free capacity of the memory 229.

  100: MRI apparatus, 101: subject, 120: static magnetic field generation system, 130: gradient magnetic field generation system, 131: gradient magnetic field coil, 132: gradient magnetic field power supply, 140: sequencer, 150: transmission system, 151: transmission coil, 152: high-frequency oscillator, 153: modulator, 154: high-frequency amplifier, 160: reception system, 161: reception coil, 162: signal amplifier, 163: quadrature phase detector, 164: AD converter, 170: control processing system, 172 : Storage device, 173: Display device, 174: Input device, 200: Image processing PC, 210: DRF board, 211: Mass storage, 220: Image processing PC, 221: Image processing unit, 222: Memory free space detection unit 223: processing status detection unit, 224: processing PC determination unit, 225: measurement control unit, 226: memory monitoring unit, 229: memory, 2 0: UI over PC, 240: hub 901: sampling substrate, 902: reconstituted substrate, 903: measurement control for PC, 904: image synthesizing PC, 905: User Interface PC

Claims (9)

A magnetic resonance imaging apparatus including a multiple coil including a plurality of receiving coils and a control unit,
The control unit processes one or more signals received by the receiving coils and outputs data for each receiving coil, and a plurality of image processing devices for generating an image from the data for each receiving coil. And
The one or more signal processing devices and the plurality of image processing devices are connected to each other so as to be able to transmit and receive data,
Each of the image processing devices includes image reconstruction means for reconstructing an image from data for each reception coil,
At least one of the image processing apparatuses is configured such that, for each measurement, for each data of each receiving coil, a transfer destination apparatus that is an image processing apparatus for reconstructing an image from the data is optimally distributed in load on each of the image processing apparatuses. Further comprising processing device determination means for notifying the signal processing device that has processed the data for each receiving coil,
The signal processing device outputs data for each reception coil toward the transfer destination device determined by the processing device determination means,
Each of the image processing devices includes a free space detection unit that detects a free space of a memory included in the image processing device and notifies the processing device determination unit of the free space.
The processing device determination means determines the transfer destination device based on the free space notified from each image processing device,
The signal processing device further includes storage means,
The image processing device further includes a memory monitoring unit that detects occurrence and resolution of a memory shortage included in the image processing device and notifies the signal processing device of a data transmission source of each reception coil,
When the signal processing device receives a memory shortage notification from the memory monitoring unit, it stores the processed data in the storage unit, and when it receives a memory shortage resolution notification from the memory monitoring unit, stores it in the storage unit. The magnetic resonance imaging apparatus is characterized in that transmission is resumed from the acquired data. A magnetic resonance imaging apparatus including a multiple coil including a plurality of receiving coils and a control unit,
The control unit processes one or more signals received by the receiving coils and outputs data for each receiving coil, and a plurality of image processing devices for generating an image from the data for each receiving coil. And comprising
The one or more signal processing devices and the plurality of image processing devices are connected to each other so as to be able to transmit and receive data,
Each of the image processing devices includes image reconstruction means for reconstructing an image from data for each reception coil,
At least one of the image processing apparatuses is configured such that, for each measurement, for each data of each receiving coil, a transfer destination apparatus that is an image processing apparatus for reconstructing an image from the data is optimally distributed in load on each of the image processing apparatuses. Further comprising processing device determination means for notifying the signal processing device that has processed the data for each receiving coil,
The signal processing device outputs data for each reception coil toward the transfer destination device determined by the processing device determination means,
Each of the image processing devices includes a free space detection unit that detects a free space of a memory included in the image processing device and notifies the processing device determination unit of the free space.
The processing device determination means determines the transfer destination device based on the free space notified from each image processing device,
The free space detecting means calculates the maximum number of data for each receiving coil that can be processed by the image processing device from the detected free space of the memory,
The magnetic resonance imaging apparatus characterized in that the processing device determining means determines the transfer destination device according to the maximum number of data that can be processed for each receiving coil instead of the free space. A magnetic resonance imaging apparatus including a multiple coil including a plurality of receiving coils and a control unit,
The control unit processes one or more signals received by the receiving coils and outputs data for each receiving coil, and a plurality of image processing devices for generating an image from the data for each receiving coil. And comprising
The one or more signal processing devices and the plurality of image processing devices are connected to each other so as to be able to transmit and receive data,
Each of the image processing devices includes image reconstruction means for reconstructing an image from data for each reception coil,
At least one of the image processing apparatuses is configured such that, for each measurement, for each data of each receiving coil, a transfer destination apparatus that is an image processing apparatus for reconstructing an image from the data is optimally distributed in load on each of the image processing apparatuses. Further comprising processing device determination means for notifying the signal processing device that has processed the data for each receiving coil,
The signal processing device outputs data for each reception coil toward the transfer destination device determined by the processing device determination means,
Each of the image processing devices includes a free space detection unit that detects a free space of a memory included in the image processing device and notifies the processing device determination unit of the free space.
The processing device determination means determines the transfer destination device based on the free space notified from each image processing device,
The free space detection means notifies the free space of the memory as a free space of the memory, which is obtained by subtracting a memory capacity used for processing according to a measurement type from the free space of the detected memory. . A magnetic resonance imaging apparatus including a multiple coil including a plurality of receiving coils and a control unit,
The control unit processes one or more signals received by the receiving coils and outputs data for each receiving coil, and a plurality of image processing devices for generating an image from the data for each receiving coil. And comprising
The one or more signal processing devices and the plurality of image processing devices are connected to each other so as to be able to transmit and receive data,
Each of the image processing devices includes image reconstruction means for reconstructing an image from data for each reception coil,
At least one of the image processing apparatuses is configured such that, for each measurement, for each data of each receiving coil, a transfer destination apparatus that is an image processing apparatus for reconstructing an image from the data is optimally distributed in load on each of the image processing apparatuses. Further comprising processing device determination means for notifying the signal processing device that has processed the data for each receiving coil,
The signal processing device outputs data for each reception coil toward the transfer destination device determined by the processing device determination means,
Each of the image processing devices includes a free space detection unit that detects a free space of a memory included in the image processing device and notifies the processing device determination unit of the free space.
The processing device determination means determines the transfer destination device based on the free space notified from each image processing device,
The magnetic resonance imaging apparatus characterized in that the processing device determination means determines the transfer destination device according to the ratio of the free capacity notified from the image processing devices. The magnetic resonance imaging apparatus according to any one of claims 1 to 4 ,
The image processing device further includes a processing state detection unit that detects a processing state in the image processing device of the image processing device and notifies the processing device determination unit of the detection result.
The magnetic resonance imaging apparatus characterized in that the processing device determination means determines the transfer destination device in consideration of the processing status notified from each of the image processing devices. The magnetic resonance imaging apparatus according to any one of claims 1 to 4,
The magnetic resonance imaging apparatus, wherein the one or more signal processing apparatuses and the one or more image processing apparatuses are connected to form a star topology via a hub. The magnetic resonance imaging apparatus according to any one of claims 1 to 4 ,
The magnetic resonance imaging apparatus characterized in that the processing device determination means determines the transfer destination device among image processing devices other than the image processing device in which the processing status is detected as being processed. The magnetic resonance imaging apparatus according to any one of claims 1 to 4 ,
The processing apparatus determining means further determines an image processing apparatus that performs post-processing on an image reconstructed by each image processing apparatus, and notifies the determination result to each image processing apparatus. . The magnetic resonance imaging apparatus according to claim 5 ,
The magnetic resonance imaging apparatus characterized in that the processing to be detected by the processing state detection means is at least one of image reconstruction processing and image synthesis processing.