JP5855553B2 - Optical trigger type serial-parallel conversion circuit - Google Patents

Description

  The present invention relates to an optical trigger type serial-parallel conversion circuit that converts a high-speed serial electric signal into a low-speed parallel electric signal.

  In recent years, with the explosive increase in data communication represented by the Internet, there has been an increasing demand for high speed and large capacity optical communication. Furthermore, future optical communication networks will need to be flexible enough to handle various network services and expandable to handle the types of services and the number of users.

  In response to the above problems, communication using optical packets can realize a network with high bandwidth utilization efficiency, flexibility, and expandability with fine data granularity. In order to realize such an optical packet switch network, an optical packet router (switch) capable of switching optical packets in high-speed burst mode is required.

  In routers, etc., the label recognition processing function to determine the output port by decoding the forwarding address information contained in the label of the optical packet, or the packet signal for an arbitrary time to avoid collision between optical packets A buffer memory processing function that can be delayed is necessary. Since these label recognition processing and buffer memory processing are executed after data is stored in a silicon-based CMOS-RAM (Random Access Memory), high-speed serial communication is possible up to the interface speed (about 1G is the limit) that these RAMs can receive. It is necessary to convert the signal into a low-speed parallel signal.

  In current optical communications, stream-type optical signals (not burst mode, but signals that flow continuously without interruption) are used, clock extraction is performed by CDR (Clock Data Recovery), and InP high-speed electronics A high-speed serial signal can be converted into a parallel signal by a DEMUX (Demultiplexer) circuit configured by a circuit or a GaAs high-speed electronic circuit.

However, in this method, since clock generation and serial-parallel conversion all depend on the electronic circuit, the conversion speed is limited by the operation speed of the electronic circuit, and the overall power consumption is considerably increased. Arise.
Furthermore, in conventional clock extraction using electronic circuits, it is necessary to apply feedback by PLL (Phase Locked Loop) and lock the oscillation frequency of VCO (Voltage Control Oscillator). It is extremely difficult to extract a clock instantly for a packet signal to be transmitted.

  As a method for solving these problems, an optical clock transistor array (OCTA) optoelectronic circuit has been developed to realize an electro-optical serial-parallel converter (see Non-Patent Document 1 below).

FIG. 4 is a schematic diagram showing a configuration of a conventional optical clock type transistor array (OCTA), that is, an optical trigger type serial-parallel conversion circuit 1.
In FIG. 4, 1-1, 1-2... 1-N are optical trigger transistor circuits, M ₁ , M ₂ ,... _MN are MSM-PDs (MSM photodiodes: Metal-Semiconductor- _{Metal photo Detector), m 1,} m 2, ··· m N charge and discharge MSM-PD circuit (MSM photodiode _{circuit), V M1, V M2 ···} V MN bias voltage for MSM-PD , R _M1 , R _M2 ... R _MN are input resistances, C _M1 , C _M2 ... C _MN are charging capacitors, Tr ₁ , Tr ₂ ... Tr _N are transistors, P ₁ , P _2.・ P _N is an optical pulse, V _b1 , V _b2 ... V _bN is a gate side bias voltage, R _b1 , R _b2 ... R _bN is a bias resistor connected in parallel, C _H1 , C _H2. C _HN the hold _{capacitor, B 1, B 2 ··· B} N is buffer _{Circuit, S ON1, S ON2 ··· S} ONN positive electrical pulses input to the gates, the S _S serial electric signal input of N _{bits, S P1, S P2 ··· S} PN output A parallel electric signal is shown.
In the following description, when a member with a suffix is generically referred to, a symbol without the suffix is used. For example M _1, M _2, when collectively · · · M _N uses M.

As shown in FIG. 4, in the conventional OCTA, that is, the conventional optical trigger serial / parallel conversion circuit 1, N (where N is a positive integer) optical trigger transistor circuits 1-1 to 1-N are one. Two transmission lines L are attached in parallel. Each of the optical trigger transistor circuits 1-1 to 1-N includes transistors Tr _{1 to} Tr _N , holding capacitors C _{H1 to} C _HN , buffer circuits B _{1 to} B _N , and transistors Tr _{1 to} Tr _N. It comprises charge / discharge type MSM-PD circuits m _{1 to} m _N attached to the gate terminal.

MSM-PD circuit m ₁ ~m _N charge and discharge type, the MSM-PD M ₁ ~M _N output side connected to the gate terminal of the transistor Tr ₁ to Tr _N, the input of the MSM-PD M ₁ ~M _N connected to the side input resistor R _M1 to R _MN and the charging capacitor _{C M1 ~C MN, MSM-PD} M 1 ~M N bias resistor R _b1 connected in parallel to the output side, that is, the gate terminal side of the to R _bN It is comprised by.

The gate terminals of the transistors Tr _{1 to} Tr _N are set to a normally-off state by applying negative bias voltages V _{b1 to} V _bN to the gate terminals of the transistors Tr _{1 to} Tr N and input to the respective optical trigger transistor circuits 1-1 to 1-N. The serial electric signal Ss is set so as not to flow into the holding capacitors C _{H1 to} C _HN .

Next, when the MSM-PD M ₁ is irradiated with the light pulse P ₁ , the positive electric pulse S _ON1 generated there rises until it exceeds the threshold of the gate voltage, and the transistor Tr ₁ is turned on. Therefore, during the period from when the electric pulse S _ON1 exceeds the threshold value of the gate voltage until it disappears (that is, while the transistor Tr ₁ is ON), the first bit of the input serial electric signal Ss is From L, the hold capacitor C _H1 is charged.

Therefore, the N MSM-PD M _{1 to} M _N are input by sequentially irradiating the optical pulses P _{1 to} P _N with a certain time difference τ (corresponding to the bit interval of the serial electrical signal S _S ). The k-th bit information (where k is an arbitrary positive integer between 1 and N) of the N-bit serial electric signal Ss is transferred to the holding capacitor C _{Hk of} the k-th phototrigger transistor circuit m _k . The sample will be held. Thereafter, the bit information held in the holding capacitors C _{H1 to} C _HN is output as parallel electric signals S _{P1 to} S _PN through the low-speed buffer circuits B _{1 to} B _N.

  Here, the reason why the charge / discharge type MSM-PD circuit m is used in the prior art shown in FIG. 4 will be described as follows.

In general, when MSM-PD M _{1 to MN} are operated, a direct current voltage is directly applied to one electrode (without using the input resistance R _M and the charging capacitor C _M ) to generate the light pulses P _{1 to} P _N. Irradiation generates electrical pulses. In this case, since the capacitance possessed by the MSM-PD M ₁ ~M _N itself is extremely small, although the rise of the electrical pulses steep, very slow tail (or 100 ps) for the hole mobility is very slow because it occurs It is difficult to close the transistors Tr _{1 to} Tr _N at high speed.

On the other hand, the charge and discharge of the MSM-PD circuit m ₁ ~m _N, and MSM-PD M ₁ ~M _N, between the application terminal of the bias voltage V _M1 ~V _MN, large input resistance R _M1 to R By inserting _MN and small charging capacitors C _{M1 to} C _MN , this problem is overcome as follows (see Non-Patent Document 2 below).

First, when the bias voltages V _{M1 to} V _MN are applied to the MSM-PD M _{1 to} M _N , the charging capacitors C _{M1 to} C _MN are slowly charged through the large input resistances R _{M1 to} R _MN. The
Next, when the light pulse P ₁ to P _N are irradiated to the MSM-PD M ₁ ~M _N, since the waveguide effect the resistance of the MSM-PD M ₁ ~M _N rapidly decreases, charging capacitor C _M1 -C _MN charges accumulated in is discharged at high speed through the MSM-PD M ₁ ~M _N, to flow to the bias resistor R _b1 to R _bN, positive electric pulse S _ON1 to S _ONN occurs To do.
That Focusing on charging capacitor C _M1 -C _MN, before the irradiation of the light pulse P ₁ to P _N are slow charging, high-rate discharge is performed immediately after the irradiation of the light pulse P ₁ to P _N.

At this time, by setting a sufficiently large value of the input resistor R _M, the current flowing from the bias voltage V _M while the electric pulses S _ON has occurred can be almost ignored. Therefore, generation of electric pulses S _ON is generated only by the charges that were accumulated mainly in the charging capacitor C _M. Therefore, since the response speed is determined by the CR time constant of “capacitor (C _M ) × bias resistance (R _b )”, an extremely high-speed electric pulse can be generated without being affected by slow holes. Become.

  However, the conventional optical trigger type serial-parallel conversion circuit 1 shown in FIG. 4 still has the following problems.

First, in order to cope with higher-speed input signals, it is necessary to electrical pulses S _ON to input to the transistor to turn ON the transistor faster (short pulses), the charging capacitor in order that It is necessary to set C _M and the bias resistance R _b small. Then, MSM-PD M ₁ the amplitude of the electrical pulses S _ON output from ~M _N is reduced, since the amount of charge that is sampled and held by the hold capacitor C _H is small, the parallel electric signal S _P1 ~ output _SP N becomes small.

Secondly, in the method of FIG. 4, when variations in the intensity of the irradiated light pulse P or circuit parameters (C _M , R _M , R _b, etc.) occur, the charge / discharge type MSM-PD circuit m outputs it. As a result, fluctuations occur in the amplitude and pulse width of the electrical pulse _SON , resulting in variations in the output signal for each channel.

Ryohei Urata, 4 others, “An Optically Clocked Transistor Array FOR High-Speed Asynchronous Label Swapping: 40 Gb / s AND BE L OJ J 26, NO. 6, March 15, 2008, p. 692-703 K. Takahata, 4 others, “3.3 ps electrical pulse generation from a discharge-Based metal-electronic photodetector”, Electronics LETTERS, VOL. 41, no. 1, January 6, 2005, p. 38,39

As described above, a serial-parallel converter is required as an interface in order to write a high-speed serial electric signal to a silicon-based CMOS memory and perform label recognition processing and buffer memory processing. However, if conventional InP high-speed electronic circuits or GaAs high-speed electronic circuits are used, the power consumption becomes extremely high and it is difficult to cope with asynchronous burst packets.
In order to solve these problems, an ultra-low power consumption optical trigger serial-parallel converter using an optical trigger transistor array has been researched and developed, but some of the problems described above remain. It was.

  From the above, the present invention outputs a larger parallel electric signal to a higher-speed input serial electric signal, and is not easily affected by variations in circuit parameters (manufacturing error) and fluctuations in optical pulse energy. An object of the present invention is to provide an optical trigger type serial-parallel conversion circuit that outputs a parallel electric signal having an amplitude.

The present invention for solving the above problems
A transmission line that propagates an N-bit serial electrical signal;
N photo-trigger type transistor circuits connected in parallel to the transmission line, taking in specific 1-bit electrical signals that constitute the N-bit serial electrical signal, and outputting them as parallel electrical signals;
With
The N photo-trigger transistor circuits are:
A transistor having a drain terminal connected to the transmission line;
A holding capacitor connected to the source terminal of the transistor;
A buffer circuit connected to a terminal on the transistor side among terminals of the holding capacitor;
An MSM-PD, and a positive bias voltage is input to the gate terminal of the transistor to make the initial state of the transistor normally on, while when the MSM-PD is irradiated with a light pulse, And an MSM-PD circuit that turns off the transistor by inputting a negative electric pulse below a threshold value of the transistor to the gate terminal.

The present invention also provides
The MSM-PD circuit is
The MSM-PD that outputs a negative electric pulse when a negative bias voltage is directly applied to the input side and a light pulse is irradiated;
The MSM-PD is connected in parallel to the output side of the MSM-PD and the gate terminal, and includes a bias resistor that inputs the positive bias voltage to the gate terminal.

The present invention also provides
The MSM-PD of the N optical trigger transistor circuits is irradiated with each of the N optical pulses,
The optical pulses irradiated to the MSM-PD are provided with a time difference corresponding to the bit interval of the serial electric signal, and the optical pulses irradiated to the MSM-PD are The phase is delayed with respect to the serial electric signal by a predetermined time slightly shorter than the bit interval.

The present invention also provides
The first bit of the serial electrical signal and the first bit of the optical pulse are always defined as 1.

Here, the prior art and the principle of the present invention will be described with reference to FIG. 5A shows the principle of the prior art, and FIG. 5B shows the principle of the present invention.
Here, the setting of the bias voltage, the signal state, and the difference in configuration are described first, and then the operation principle of both is described.

(1) the bias voltage V _M for the MSM-PD.
- In the past, as electrical pulses S _ON "positive" occurs, giving a bias voltage V _M of the "positive".
In the present invention, a “negative” bias voltage V so that a “negative” electrical pulse S _OFF is generated.
_M is given.

(2) Regarding the bias voltage V _b on the gate side.
Conventionally, a “negative” bias voltage V _b is applied to the gate terminal so that the transistor Tr is sufficiently “OFF” and “normally off”.
In the present invention, a “positive” bias voltage V _b is applied to the gate terminal so that the transistor Tr is sufficiently “ON” and “normally on”.

(3) Electric pulses S _ON and S _OFF .
Conventionally, the transistor Tr is turned “ON” when the value of the positive electric pulse S _{ON as} the ON signal “exceeds” the threshold value of the transistor Tr.
In the present invention, the transistor Tr is turned “OFF” when the value of the negative electric pulse S _OFF that is an OFF signal “below the threshold value of the transistor Tr”.

(4) The charge charged in the hold capacitor C _H.
· In the conventional serial electrical signals on the transmission line L is sampled, filled in gray in FIGS. 5 (a) "electric charge corresponding to the area A1" is stored in the hold capacitor C _H.
- In the present invention, since the transistor Tr is normally, the serial electrical signals on the transmission line L flows into the hold capacitor C _H, to the transistor Tr is turned OFF immediately before the signal bits is completed, FIG. 5 (b ) the painted in gray "charge corresponding to the area A2" is stored in the hold capacitor C _H.

(5) Difference in configuration.
Conventionally, an input resistor _RM and a charging capacitor _CM are provided on the input side of the MSM-PDM.
In the present invention, the input resistance R _M and the charging capacitor C _M are not provided on the input side of the MSM-PDM.

As described above, in the conventional method, a high-speed positive electric pulse is generated using a charge / discharge type MSM-PD circuit, and the transistor is turned on only for a short time by the electric pulse, so that one bit of the serial electric signal is generated. Sampling signal. At this time, a negative bias is applied to the bias voltage _Vb on the gate side so that the transistor Tr is sufficiently turned off, and an ON signal (positive electric power) output from the charge / discharge MSM-PD circuit is applied. the pulse), only the time domain exceeding the threshold voltage, the transistor Tr becomes oN, as shown in FIG. 5 (a), the amount of charge accumulated in the hold capacitor C _H is reduced.

On the other hand, in the present invention, a negative bias is directly applied to the input side of the MSM-PD so that a negative electrical pulse is generated from the MSM-PD circuit, so that the transistor Tr is normally on. A positive bias is applied to the output side of the MSM-PD, that is, the gate side.
At this time, the input resistor R _M and the charging capacitor C _M are not used so that the electrical output from the MSM-PD circuit has a sufficiently long tail.

In the present invention, the transistor Tr are the normally, when one bit signal of the electrical signal input to the transmission line is "1", the more charge is accumulated flows into the hold capacitor C _H. If the next bit signal is "0", the charge accumulated in the hold capacitor C _H will be be discharged through the transistor Tr again. However, when the accumulated charge reaches the maximum before this discharge (before the next bit signal is input), when the MSM-PD is irradiated with a light pulse, a negative electric pulse is generated from the MSM-PD circuit. occurs, to close the gate of the transistor Tr, the charge accumulated in the hold capacitor C _H will be be held in the hold capacitor C _H loses escape. At this time, since it has a negative electrical pulses long tails from MSM-PD circuit, a certain time the tail is present, the transistor Tr OFF, and the hold signal which is held in the hold capacitor C _H is sustained period of time, It is output from the buffer circuit B as a low-speed parallel electric signal.

In this way the present invention, a transistor of the normally-while tracking the serial electric signal input by the hold capacitor C _H, by irradiating a light pulse to the MSM-PD at a desired timing, the transistor The gate information is turned off and desired bit information is held for a certain time.

In the conventional technique, since sampling is performed with a short electric pulse, the amount of electric charge held in the holding capacitor via the transistor is small. Further, when the input serial electric signal becomes high speed, it is necessary to reduce the values of the charging capacitor and the bias resistor in order to shorten the electric pulse generated from the MSM-PD circuit. Becomes smaller, and the amount of charge held in the holding capacitor becomes smaller.
In addition, if the optical pulse energy and circuit parameters (such as the resistance value of the bias resistor and the threshold value of the transistor) irradiated to the MSM-PD vary from channel to channel, the amplitude of the electrical pulse varies, and the amplitude of the output parallel electrical signal Cause the results to vary from channel to channel.

On the other hand, according to the present invention, after the input serial electric signal is fully charged in the holding capacitor, the electric charge is held by the negative electric pulse, so that a large output parallel electric signal can be obtained. Is possible.
Furthermore, since there is no need to increase the tail of the MSM-PD, the bias resistance value can be set large (regardless of the speed of the input signal), so that a large OFF signal (with a smaller optical pulse energy) Negative electric pulse) can be obtained.
In addition, even if the amplitude of the electric pulse (OFF signal) fluctuates due to variations in circuit parameters or fluctuations in the light pulse energy, the amplitude fluctuation of the electric pulse (OFF signal) is once after the transistor is turned off. An output parallel electric signal having a constant amplitude can be obtained without affecting the output signal amplitude.

  As described above, the effect of the present invention realizes further increase in speed, reduction in power, and stabilization of output in the optical trigger type serial-parallel conversion circuit.

It is the schematic diagram which showed the structure of the optical trigger type | mold serial-parallel conversion circuit based on the Example of this invention. It is a signal waveform diagram which shows the negative electric pulse (OFF signal) in the Example of this invention. It is the schematic diagram which showed the structural example of the optical packet switch for demonstrating the utilization form of this invention. It is the schematic diagram which showed the structure of the conventional optical trigger type | mold serial-parallel conversion circuit. It is the schematic diagram which showed the operation principle of the conventional method and this invention.

  Hereinafter, the optical trigger type parallel-serial conversion circuit according to the present invention will be described in detail based on embodiments.

  FIG. 1 shows a configuration example for implementing a 1: N optical trigger type parallel-serial conversion circuit 10 according to an embodiment of the present invention.

The optical trigger type parallel-serial conversion circuit 10 is configured by connecting N optical trigger type transistor circuits 10-1 to 10 -N in parallel to the transmission line L. An N-bit serial electric signal S _S is propagated to the transmission line L, and this serial electric signal S _S is input to each of the optical trigger transistor circuits 10-1 to 10-N. The serial electric signal S _S is, for example, a label signal, and the first bit is always defined as “1”.
Light trigger type transistor circuits 10-1 to 10-N takes in particular 1 bit of the electrical signal different from each other to constitute a serial electrical signal S _S N-bit is output as a parallel electric signal S _P.

Each light trigger type transistor circuits 10-1 to 10-N, the transistor Tr ₁ and to Tr _N, and hold capacitor C _H1 -C _HN, a buffer circuit B ₁ ~B _N, MSM-PD circuit m _10-1 ~ _{M 10-N} . Although the detailed structure will be described later, the MSM-PD circuits m _{10-1 to} m _10-N are not charge / discharge types, unlike the conventional ones.

The drain terminals of the transistors Tr _{1 to} Tr _N are connected to the transmission line L. The holding capacitors C _{H1 to} C _HN are connected to the source terminals of the transistors Tr _{1 to} Tr _N. The buffer circuits B _{1 to} B _N are connected to a connection line that connects the source terminals of the transistors Tr _{1 to} Tr _N and the holding capacitors C _{H1 to} C _HN . In other words, the buffer circuits B _{1 to} B _N are electrically connected to terminals on the transistor Tr _{1 to} Tr _N side among the terminals of the holding capacitors C _{H1 to} C _HN .

The MSM-PD circuits m _{10-1 to} m _10-N are configured by MSM-PD M _{1 to MN} and bias resistors R _{b1 to} R _bN .
The output sides of the MSM-PD M _{1 to MN} are connected to the gate terminals of the transistors Tr _{1 to} Tr _N. Bias resistor R _b1 to R _bN is the gate terminal of the MSM-PD M ₁ ~M _N output side and transistors Tr ₁ to Tr _N, are connected in parallel.

Negative bias voltages V _{M1 to} V _MN are directly applied to the input sides of the MSM-PD M _{1 to} M _N.
Further, positive bias voltages V _b1 , V _b2 ... V _bN are input to the gate terminals of the transistors Tr _{1 to} Tr _N via the bias resistors R _{b1 to} R _bN . Thus, since the positive bias voltages V _b1 , V _b2 ... V _bN are input to the gate terminals, the transistors Tr _{1 to} Tr _N are set to normally-on.
The values of the positive bias voltages V _b1 , V _b2 ... V _bN are set to voltage values that can sufficiently turn on the transistors Tr _{1 to} Tr _N.

The MSM-PD M ₁ ~M _N, the light pulse P ₁ to P _N are adapted to be sequentially illuminated. That is, the light pulse P ₁ is irradiated to the MSM-PD M _1, the optical pulse P ₂ is radiated to the MSM-PD M _2, the light pulse P _k is irradiated to the _{MSM-PD M k, MSM-} PD M _N is irradiated with a light pulse P _N.

A time difference corresponding to the bit interval of the serial electrical signal S _S is sequentially set between the individual light pulses P _{1 to} P _N. That is, the _first bit of the optical pulse P ₂ is delayed from the _first bit of the optical pulse P ₁ by a time corresponding to the bit interval, and the first bit of the optical pulse P ₃ is set to the bit interval with respect to the first bit of the optical pulse P _2. The _first bit of the optical pulse P _N is delayed by a time corresponding to the bit interval with respect to the _first bit of the optical pulse P _N−1 .
The _first bit of the optical pulses P _{1 to} P _N is always defined as “1”.

Moreover, the optical pulses P _{1 to} P _N are out of phase with the serial electrical signal S _S. The shift amount is slightly shorter predetermined time than the bit interval of the serial electric signal S _S, the above shift amount to the phase of the phase of the optical pulse P ₁ to P _N a serial electrical signal S _S ( Time).
More specifically, the amount of shift (time) of the delayed phase of the optical pulses P _{1 to} P _N with respect to the serial electrical signal S _S is determined from the time when the 1-bit bit signal of the serial electrical signal S _S is input to the transistor Tr power storage charge 1-bit signal is charged in the hold capacitor C _H through the transistor Tr is the time interval up to the point of maximum (before the next bit signal is input).

MSM-PD M ₁ ~M _N, when the light pulse P ₁ to P _N is not irradiated, is large and the resistance value, the optical pulse P ₁ to P _N are irradiated by waveguide effect, the The resistance value has a characteristic of rapidly decreasing.

When the first bit of the N-bit serial electric signal (label signal) S _S is input to the transmission line L, the charge passes through the transistor Tr ₁ of the _first phototrigger transistor circuit 10-1 and is held by the hold capacitor C _H1. Is charged.

When charging reaches the maximum (immediately before switching to the second bit), when the optical pulse P ₁ (optical label signal: the first bit is always defined by “1”) is irradiated to the MSM-PD M ₁ , FIG. The negative electric pulse S _OFF1 due to the first bit of the optical label as shown in FIG. 6 is output from the MSM-PD M ₁ . Electric pulses S _OFF1 that is, the gate voltage is output, since below the threshold of the transistor Tr _1, the transistor Tr ₁ is turned OFF, the charge accumulated in the hold capacitor C _H1 becomes to be held.

Since the response signal (electric pulse S _OFF1 ) of MSM-PD M ₁ has a long tail, the potential decreases stepwise each time the subsequent bit of the optical pulse (optical label signal) P ₁ is irradiated. it is possible to hold the transistor Tr ₁ in the OFF state also continues for some time after irradiation of the last bit labels. Therefore, the signal (charge) held in the holding capacitor C _H1 is output to the outside as a low-speed parallel electric signal SP ₁ through the buffer circuit B ₁ .

Next, when the second bit of the serial electric signal (label signal) S _S is input to the transmission line L, similarly to the second optical trigger type transistor circuit 10-2, the optical pulse P ₂ is irradiated Accordingly, the second bit is taken out as a parallel electric signal S _P2.

Thereafter, the k-th bit of the serial electric signal (label signal) S _{S can be} sequentially extracted as the parallel electric signal S _Pk from the k-th optical trigger transistor circuit 10-k.

Finally, the parallel electric signals S _{P1 to} S _PN are taken out from the respective optical trigger type transistor circuits 10-1 to 10-N.
In this way, the high-speed serial electric signal SS can be converted into the low-speed parallel electric signals S _{P1 to} S _PN .

  FIG. 3 shows a configuration example of an optical packet switch as a usage example for explaining how to use the present invention.

  The input optical packet signal includes a payload in which data is stored and an N-bit optical label in which transfer information is stored. A part of the input optical packet signal is tapped and sent to the label processor 100.

  In the label processor 100, the payload part is first deleted by the label separator 110, and only the optical label is sent to the PD (photodiode) 120 and the optical branch delay circuit 130. The N-bit label signal (serial electric signal) converted into an electric signal by the PD 120 is input to the transmission line L of the serial-parallel conversion circuit 10 according to the present invention as described above.

The other optical label (optical pulse) sent to the optical branch delay circuit 130 is branched into N pieces, giving a time difference τ corresponding to the bit interval of the input optical label, and N optical labels (optical pulses). Is given the above-mentioned delay phase shift amount (time) with respect to the serial electric signal. In this way, optical labels (optical pulses) that are given a time difference corresponding to the bit interval and are given a phase shift amount with respect to the serial electrical signal are successively N MSM-PD M ₁ to M _N is irradiated. As described above, the N-bit label signal (serial electric signal) output from the PD (photodiode) 120 is converted into N low-speed parallel electric signals S _{P1 to} S _PN by the serial-parallel conversion circuit 10 of the present invention. And sent to the label recognition circuit 140 formed of a CMOS electronic circuit.

  In the label recognition circuit 140, the input label information (transfer destination information) is collated with an address table held therein to determine an output port and a control signal for the optical switch 150 is generated.

  Thus, the optical trigger type serial-parallel conversion circuit 10 of the present invention is used as a low-power interface device for processing burst mode high-speed label signals with a CMOS circuit in the label processor 100 in the optical packet router. Can do.

  For example, as described above, the present invention is an interface device (high-speed label device) for enabling high-speed label information to be recognized by a CMOS electronic circuit in an optical label processor used in an optical router indispensable for realizing an optical packet switch network. It can be used as a serial-parallel converter for an asynchronous burst serial optical signal.

1, 10 Optical trigger type serial-parallel conversion circuit 1-1 to 1-N, 10-1 to 10-N Optical trigger type transistor circuit m _{1 to} m _N , m _{10-1 to} m _10-N MSM-PD circuit (MSM photodiode circuit),
M ₁ , M ₂ ,... M _N MSM-PD (MSM photodiode)
Tr _{1 to} Tr _N transistors R _{b1 to} R _bN Bias resistors C _{H1 to} C _HN Hold capacitors B _{1 to} B _N Buffer circuits

Claims (4)

A transmission line that propagates an N-bit serial electrical signal;
N photo-trigger type transistor circuits connected in parallel to the transmission line, taking in specific 1-bit electrical signals that constitute the N-bit serial electrical signal, and outputting them as parallel electrical signals;
With
The photo-trigger transistor circuit is
A transistor having a drain terminal connected to the transmission line;
A holding capacitor connected to the source terminal of the transistor;
A buffer circuit connected to a terminal on the transistor side among terminals of the holding capacitor;
An MSM-PD, and a positive bias voltage is input to the gate terminal of the transistor to make the initial state of the transistor normally on, while when the MSM-PD is irradiated with a light pulse, An MSM-PD circuit that inputs a negative electrical pulse below a transistor threshold to the gate terminal to turn the transistor off;
An optical trigger type parallel-serial conversion circuit comprising: In claim 1,
The MSM-PD circuit is
The MSM-PD that outputs a negative electric pulse when a negative bias voltage is directly applied to the input side and a light pulse is irradiated;
A bias resistor connected in parallel to the output side of the MSM-PD and the gate terminal, and for inputting the positive bias voltage to the gate terminal;
An optical trigger type parallel-serial conversion circuit comprising: In claim 1 or claim 2,
The MSM-PD of the N optical trigger transistor circuits is irradiated with each of the N optical pulses,
The optical pulses irradiated to the MSM-PD are provided with a time difference corresponding to the bit interval of the serial electric signal, and the optical pulses irradiated to the MSM-PD are An optical trigger type parallel-serial conversion circuit characterized in that the phase is delayed with respect to the serial electric signal by a predetermined time slightly shorter than the bit interval of. In any one of Claims 1 thru | or 3,
The optical trigger type parallel-serial conversion circuit, wherein the first bit of the serial electrical signal and the first bit of the optical pulse are always defined as 1.

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