JP5865087B2 - Signal generating apparatus, information processing apparatus, and signal adjustment method - Google Patents

Description

  The present invention relates to a signal generation apparatus, an information processing apparatus, and a signal adjustment method capable of adjusting an output analog signal in a signal generation apparatus that outputs an analog signal from a current output type digital-analog converter. .

  In signal generators that generate and output analog signals from digital video data, current output type digital-to-analog converters (DACs) are widely used.

  FIG. 14 shows a signal generator 118 as an example of a conventional signal generating apparatus using a current output type DAC, and a receiving apparatus 120 connected to the signal generator 118. In general, the signal generator 118 receives the input video data, generates a necessary signal pattern (hereinafter referred to as DAC data), and a digital DAC received from the signal pattern generation circuit 130. It is composed of a current output type DAC 132 that converts data into an analog signal.

  The DAC 132 is provided with a reference voltage input terminal 152 and an output voltage adjustment terminal 154. A reference voltage Vref is supplied to the reference voltage input terminal 152, and an adjustment output resistor Rfs is connected to the output voltage adjustment terminal 154. Further, the DAC 132 is provided with a DAC output terminal 150 for outputting an analog signal converted by the DAC 132 to the outside. The DAC output terminal 150 is additionally provided with a transmission end (signal generation of the transmission line 158) in order to take out the analog signal converted by the DAC 132 outside the signal generator 118 (for example, the receiving device 120 such as a display device). Load resistor R1 at the end of the transmitter 118), the transmission line 158, and the load resistor R2 at the receiving end (end of the transmission line 158 on the receiving device 120 side). The load resistance R1 is a load resistance (internal load resistance) on the signal generator 118 side, while the load resistance R2 is a load resistance (external load resistance) on the receiving device 120. The DAC 132 can extract the output voltage Vout by the receiving device 120 connected to the signal generator 118 by supplying an analog current corresponding to the DAC data to each load resistor connected to the DAC output terminal 150.

  In a general usage example, for example, when the characteristic impedance Zo of the transmission line 158 is 75 [Ω], load resistors R1 and R2 having both 75 [Ω] are used. Accordingly, the load resistance R0 viewed from the DAC 132 is 37.5 [Ω], which is a parallel resistance value (combined resistance value) of 75 [Ω] and 75 [Ω]. If the signal amplitude V at the receiving end on the receiving device 120 side is 1.3 [V] at the maximum, the maximum value of the output current Idac of the DAC 132 is 1.3 [V] /37.5 [Ω] = 35 [mA].

  As a technique related to the DAC, for example, Patent Document 1 discloses a technique for controlling a display controller by determining a monitor type based on a load resistance of a connected monitor in a display control apparatus having a DAC. ing. Further, Patent Document 2 discloses a technique related to adjustment of an output voltage value caused by variation in component characteristics of components such as a DAC and an amplifier provided in an acoustic measuring instrument, which is performed when the acoustic measuring instrument is manufactured. Yes.

Japanese Patent Laid-Open No. 5-73016 JP 2002-267695 A

  Incidentally, the output voltage Vout of the signal generator configured as described above is a value obtained by multiplying the output current Idac of the DAC 132 by the load resistance R0, and depends on R0.

  Here, depending on the receiving device 120 connected to the receiving end by the user, the design value of the load resistance R2 (that is, the ideal value of the load resistance R2 (75Ω in the above example)) and the user actually connected An error may occur between the value of the external load resistance. Usually, the standard of the signal generator 118 and the receiver 120 connected to the signal generator 118 is unified, and the external load resistance of the receiver 120 is expected to be approximately equal to the ideal load resistance R2. Is done. If the signal generator 118 and the receiving device 120 are products of the same manufacturer, both are manufactured to meet the standard in the same way, so that errors are unlikely to occur. However, the signal generator 118 and the receiving device 120 may be connected from different manufacturers. The method of meeting the standards does not necessarily match between manufacturers. For example, some manufacturers use a load resistor R2 that can satisfy the standards with sufficient accuracy for the receiving device 120. Some manufacturers use a load resistor R2 that meets the standards for accuracy. Due to such variations, there has been a problem that the load resistance R0 as viewed from the DAC 132 fluctuates and the output voltage Vout from the signal generator deviates from the intended value. Here, the reference voltage Vref and the adjustment output resistance Rfs described above define a reference current that serves as a reference for the output current Idac of the DAC 132. Conventionally, these values are the values of the ideal load resistance R0 during manufacturing. Since the setting was fixed based on the value, the above problem could not be dealt with.

  In the above-mentioned Patent Document 1, although the DAC is set based on the connected load, the output of the own apparatus cannot be adjusted according to the error due to the load fluctuation. Further, in the above-mentioned Patent Document 2, the adjustment is simply performed according to the characteristic variation of the own device at the manufacturing stage, and no consideration is given to the fluctuation of the output voltage due to the error of the load resistance connected at the stage of use. .

  The present invention has been proposed in order to solve the above-described problem. In a signal generator that outputs a signal from a current output type DAC, the value of a load resistance connected to the output terminal of the DAC, the design value, An object of the present invention is to provide a signal generation device, an information processing device, and a signal adjustment method capable of suppressing fluctuations in the output voltage of a DAC due to the error even if an error occurs between the two.

In order to achieve the above object, a signal generator according to the present invention includes a signal generator for generating a digital signal based on input video data or a predetermined control signal and outputting the digital signal from an output terminal, and an input terminal Is connected to the output end of the signal generating means, and has a digital / analog converting means for converting a digital signal inputted from the input end into an analog current and outputting the analog current, and is connected to the output end of the digital / analog converting means. Is a signal conversion means to which an internal load resistance is connected in advance and an external load resistance can be connected; an output voltage output from the output terminal of the digital-analog conversion means; and an upper limit value and a lower limit value of a predetermined output voltage When the output voltage is not less than the lower limit value and not more than the upper limit value, the external load resistor is connected to the output terminal of the digital-analog conversion means. A detecting means for outputting a detection signal indicating that it is, to a first predetermined time period of the operation period of the signal converting means, said signal generating means to input said control signal to said signal generating means When the control signal is received and the detection signal is received in the first period, a digital resistor based on the control signal is digitally connected with a reference resistor having a predetermined resistance value connected to the output terminal of the digital-analog converter. The first reference voltage set as the output voltage output from the output terminal of the digital-analog conversion means when a signal is generated, and the external load resistor connected to the output terminal of the digital-analog conversion means When a digital signal is generated based on a control signal, the output voltage output from the output terminal of the digital-analog conversion means is compared, and the difference is small. Starts the adjustment operation for adjusting the signal conversion means in a direction in which, immediately before the signal and in the second period in which the control signal is not input to the generating means, the second period of the operation period of the signal converting means Adjusting means for controlling the signal conversion means so that the adjustment state adjusted in the first period is maintained.

  The information processing apparatus according to the present invention includes the signal generation device, an imaging unit that captures a subject and acquires video data, a storage unit that stores the video data captured by the imaging unit, and the storage Input means for inputting video data stored in the means to the signal generating means of the signal generating device.

In addition, the signal adjustment method of the present invention includes a signal generating unit that generates a digital signal based on input video data or a predetermined control signal and outputs the digital signal from an output end, and the signal generating unit is connected to the input end. An output terminal is connected, and has a digital-analog conversion means for converting a digital signal input from the input terminal into an analog current and outputting the analog current, and an internal load resistor is provided at the output terminal of the digital-analog conversion means. A signal adjustment method performed by a signal converter that is connected in advance and can be connected to an external load resistor, the output voltage output from the output terminal of the digital-analog converter, and a predetermined upper limit value of the output voltage, and When each of the lower limit values is compared and the output voltage is not less than the lower limit value and not more than the upper limit value, the external load is connected to the output end of the digital-analog conversion means. And outputs a detection signal indicating that the anti is connected, in advance in the first period determined, the signal generating means to input said control signal to said signal generating means in the operation period of the signal converting means When the detection signal is received during the first period, a digital signal is generated based on the control signal in a state where a reference resistor having a predetermined resistance value is connected to the output terminal of the digital-analog conversion means. The first reference voltage set as the output voltage output from the output terminal of the digital-analog conversion means and the control signal in a state where an external load resistor is connected to the output terminal of the digital-analog conversion means. Based on the output voltage output from the output terminal of the digital-to-analog conversion means when a digital signal is generated based on the Start the adjustment operation for adjusting the signal conversion means, in a second period in which the control signal to said signal generating means is not input in the operation period of the signal converting means, the duration of the second just before the first The signal conversion means is controlled so that the adjustment state adjusted in the period is maintained.

  As described above, according to the present invention, in the signal generator that outputs a signal from the current output type DAC, there is an error between the design value and the value of the load resistance actually connected to the output terminal of the DAC. Even if it occurs, there is an effect that the fluctuation of the output voltage of the DAC due to the error can be suppressed.

It is a figure which shows the structural example of the information processing apparatus which concerns on embodiment. It is a block diagram which shows the detailed structure of the signal generator which concerns on embodiment, and the electrical structure of the connection site | part with respect to this signal generator of the receiver connected to this signal generator. It is a figure which shows an example of a structure of a general DAC of a current output type. It is a figure which shows an example of a structure of the output voltage adjustment circuit which concerns on embodiment. It is a timing chart explaining error correction concerning a 1st embodiment. It is a timing chart explaining error correction concerning a 2nd embodiment. It is a figure which shows the other example of a structure of an output voltage adjustment circuit. It is a figure which shows the other example of a structure of an output voltage adjustment circuit. It is a figure which shows the other example of a structure of an output voltage adjustment circuit. 10 is an example of a timing chart when error correction is performed by the output voltage adjustment circuit shown in FIG. 9. It is a figure which shows the other example of a structure of an output voltage adjustment circuit. It is a figure which shows the other example of a signal generator. It is a figure which shows the structural example of the output voltage adjustment circuit in FIG. It is a figure which shows the structure of the conventional signal generator.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  [First Embodiment]

  An example of the information processing apparatus 10 is shown in FIG. An information processing apparatus according to the present invention is an apparatus that generates and outputs an analog signal from digital video data to a monitor such as a television, a projector, or the like (hereinafter, these apparatuses are collectively referred to as a receiving apparatus 20). For example, a video camera or a DVD player can be used, but in the present embodiment, a video camera is taken as an example of the information processing apparatus 10, and video data obtained by imaging video data with the video camera. An example will be described.

  As shown in FIG. 1, the information processing apparatus 10 includes an image sensor 11, a control unit 12, an analog-to-digital converter (ADC) 13, an encoder circuit 14, a memory 15, a decoder circuit 16, and A signal generator 18 is provided.

  The control unit 12 includes a CPU (Central Processing Unit), a RAM (Random Access Memory), and a ROM (Read Only Memory), and is configured by a general computer configured to be connected to each other via a bus. ing. The control unit 12 controls the information processing apparatus 10 as a whole when the CPU executes a program stored in a storage unit such as a ROM. The processing performed by the control unit 12 includes processing for outputting an error correction circuit operation signal described later to the signal generator 18.

  The imaging device 11 is made of, for example, a charge coupled device (CCD), a complementary metal oxide semiconductor (CMOS), or the like, and images a subject. An analog video signal obtained by imaging is converted into digital data (hereinafter referred to as video data) by the ADC 13 and input to the encoder circuit 14. The encoder circuit 14 performs a predetermined encoding process (for example, MPEG compression) on the input video data and stores it in the memory 15. The memory 15 is configured by a nonvolatile storage medium such as a flash memory. Note that the memory 15 may be configured by a removable storage medium such as a USB memory. The memory 15 may be storage means for storing video data acquired from another removable storage medium or video data downloaded from a network (not shown).

  The decoder circuit 16 performs decoding according to the encoding format (for example, MPEG) of the video data stored in the memory 15 and inputs it to the signal generator 18.

  The signal generator 18 converts the decoded video data input from the decoder circuit 16 into an analog signal and outputs the analog signal to the receiving device 20 connected to the signal generator 18.

  FIG. 2 is a configuration diagram showing a configuration of the signal generator 18 and an electrical configuration of a connection portion of the receiving device 20 connected to the signal generator 18 with respect to the signal generator 18. The signal generator 18 of the present embodiment includes a signal pattern generation circuit 30, a current output type digital-to-analog converter (DAC) 32, an error correction circuit 34, and a connection detection circuit 36. Yes.

  The signal pattern generation circuit 30 generates a signal pattern (hereinafter referred to as DAC data) necessary for processing in the DAC 32 based on video data input from the outside (in this embodiment, the decoder circuit 16). The DAC 32 includes a plurality of current cells (details will be described later), and the signal pattern generation circuit 30 generates digital DAC data for turning on / off a switch provided in the current cell in accordance with serially input video data. It is generated for each current cell and output in parallel. Note that a predetermined control signal may be input to the signal pattern generation circuit 30 from a control circuit 38 to be described later. In this case, predetermined DAC data is generated according to the control signal and input to the DAC 32.

  A DAC output terminal 50 is connected to the DAC 32. The DAC output terminal 50 additionally includes a load resistor R1, a transmission line 58, and a reception line (end of the transmission line 58 on the signal generator 18 side). A load resistor R2 at the end (the end of the transmission line 58 on the receiving device 20 side) is connected. The load resistor R1 is a load resistor (hereinafter referred to as an internal load resistor) provided on the signal generator 18 side, and is configured in a state of being connected to the DAC output terminal 50 in advance. On the other hand, the load resistance R2 is a load resistance (hereinafter referred to as an external load resistance) of the receiving device 20 connected to the receiving end. Since the user can connect any receiving device 20 to the information processing device 10, the value of the load resistance R2 may vary depending on the connected receiving device 20. In addition, the connection between the receiving device 20 and the information processing device 10 may be released by the user, and the load resistor R2 may not be connected to the DAC output terminal 50.

  The DAC 32 converts the DAC data input from the signal pattern generation circuit 30 into an analog current, and supplies the analog current to the load resistor R 0 connected to the DAC output terminal 50. More specifically, when an external load resistor is connected to the DAC output terminal 50 together with an internal load resistor, an analog current is supplied to the load resistor R1 (internal load resistor) and the load resistor R2 (external load resistor), and the DAC output is output. When an external load resistor is not connected to the terminal 50, an analog current is supplied to the load resistor R1 (internal load resistor). Note that when the receiving device 20 is not connected to the signal generator 18, an analog current may not flow from the DAC 32 to the load resistor R1. When an external load resistance is connected, the load resistance R0 viewed from the DAC 32 is a combined resistance of the internal load resistance and the external load resistance. When no external load resistance is connected, the load resistance R0 viewed from the DAC 32 is obtained. Is the internal load resistance.

  In a general usage example, for example, when the characteristic impedance Zo of the transmission line 58 is 75 [Ω], load resistors R1 and R2 having both 75 [Ω] are used. As a result, the load resistance R0 viewed from the DAC 32 is 37.5 [Ω], which is a parallel resistance value (combined resistance value) of 75 [Ω] and 75 [Ω]. In this case, if the signal amplitude V at the receiving end is 1.3 [V] at the maximum, the maximum value of the output current Idac of the DAC 132 is 1.3 [V] /37.5 [Ω] = 35 [mA]. In this way, the value of the load resistance R2 is designed to be the same value as the load resistance R1, but this value is a design value at the manufacturing stage, a so-called ideal value, as the load resistance R2 actually connected by the user. There may be an error between the external load resistance and the design value. In this case, an error also occurs between the design value and the load resistance R0 viewed from the DAC 32 when the external load resistance is connected.

  Further, the DAC 32 is provided with a reference voltage input terminal 52 and an output voltage adjustment terminal 54. A reference voltage Vref is supplied to the reference voltage input terminal 52, and an adjustment output resistor Rfs is connected to the output voltage adjustment terminal 54.

  FIG. 3 shows an example of the configuration of a general current output type DAC 32.

  The DAC 32 shown in the figure includes a main current source unit 22 that generates a reference current, and a current cell unit 26 that generates a current corresponding to input DAC data.

  The main current source unit 22 includes an operational amplifier 60 and an NMOS transistor 62. The + input terminal of the operational amplifier 60 is connected to the reference voltage input terminal 52 to which the reference voltage Vref is supplied, the − input terminal of the operational amplifier 60 is connected to the output voltage adjustment terminal 54, and the output signal of the operational amplifier 60 is an NMOS transistor. 62 is input to the gate. An adjustment output resistor Rfs is connected between the output voltage adjustment terminal 54 and the ground.

  The output signal of the operational amplifier 60 is controlled so that the reference voltage Vref and the voltage level of the output voltage adjustment terminal 54 coincide. As a result, the reference current Iref corresponding to the voltage level of the output signal of the operational amplifier 60 is supplied to the adjustment output resistor Rfs via the NMOS transistor 62, and the voltage level (Vfs) of the output voltage adjustment terminal 54 matches the reference voltage Vref. It is adjusted to the direction to do. The reference current Iref at this time is expressed by reference current Iref = Vref / Rfs.

  The drain of the PMOS transistor 64 is connected to the drain of the NMOS transistor 62. As a result, the reference current Iref is supplied from the main current source unit 22 to the PMOS transistor 64.

  The current cell unit 26 includes a plurality of current cells 24a to 24n. Although the number of current cells is not particularly limited, for example, in a case where 10 bits of video data can be processed, 1024 current cells may be provided. Each of the current cells 24a to 24n includes a PMOS transistor 66 and a switch 68 connected in series, and each of them is connected in parallel. The PMOS transistor 66 of each of the current cells 24a to 24n constitutes a current mirror circuit using the PMOS transistor 64 as an input transistor. The reference current Iref generated by the main current source unit 22 flows in the current path of each current cell. Each switch 68 is connected to the DAC output terminal 50. Each switch 68 is turned on / off according to the input DAC data, and the currents supplied from all the current cells in which the switch 68 is turned on are added and supplied to the DAC output terminal 50. As described above, the load resistance R0 is connected to the DAC output terminal 50, and the output voltage Vout of the DAC output terminal 50 is a value obtained by multiplying the current Idac supplied from the current cell unit 26 by the load resistance R0. expressed.

  However, as described above, since any receiving device 20 can be connected to the receiving end by the user, the value of the load resistance R2 is not always the same as the design value. Therefore, depending on the receiving device 20 connected to the receiving end, the load resistance R0 viewed from the DAC 32 may not be the same as the design value, and an error may occur, resulting in variation (variation) in the output voltage Vout. Therefore, in this embodiment, an error correction circuit 34 is provided in the signal generator 18 so as to suppress variations in the output voltage Vout. Note that the design value of the load resistor R0 refers to a combined resistance value when the resistance values of the load resistor R1 and the load resistor R2 are design values (and the same value).

  The error correction circuit 34 corrects an error in the output voltage Vout of the DAC 32 caused by an error in the load resistance (hereinafter referred to as error correction or adjustment of the output voltage Vout). The error correction circuit 34 includes a control circuit 38 and an output voltage adjustment circuit 40. The control circuit 38 outputs an operation signal to the output voltage adjustment circuit 40 in response to the input of the error correction circuit operation signal from the control unit 12 to operate the output voltage adjustment circuit 40, and the signal pattern generation circuit 30 A control signal is output to generate predetermined DAC data.

  The output voltage adjustment circuit 40 is connected to the output terminal of the DAC 32 and receives the output voltage Vout corresponding to the predetermined DAC data. The output voltage adjustment circuit 40 compares the output voltage out with a reference voltage Vr1 described later to adjust the reference voltage Vref. The reference voltage Vr1 corresponds to the first reference voltage of the present invention, and the reference voltage Vref corresponds to the second reference voltage. In this embodiment, the predetermined DAC data is DAC data for maximizing the output voltage Vout of the DAC 32. The DAC data for maximizing the output voltage Vout of the DAC 32 is DAC data for turning on all the switches 68 of the plurality of current cells. Hereinafter, this DAC data is referred to as maximum DAC data. The adjustment with the maximum value of the output voltage Vout is preferable because the adjustment is performed with the voltage value having the largest amplitude and the error of the adjustment result can be reduced.

  A connection detection circuit 36 is also connected to the output terminal of the DAC 32. The connection detection circuit 36 says that the receiving device 20 (external load resistor) is connected to the receiving end (note that the receiving end is connected to the DAC output terminal 50, and thus “connected to the DAC output terminal 50”). In this embodiment, when the maximum DAC data is generated and output to the DAC 32, the output voltage Vout of the DAC 32 is equal to or lower than a predetermined reference voltage E1. A predetermined signal indicating that some normal external load resistance (receiving device 20) is connected is output. Hereinafter, the detection operation performed by the connection detection circuit 36 may be simply referred to as load detection.

  The connection detection circuit 36 can be configured to include a comparator. For example, the output terminal of the DAC 32 is connected to the + input terminal of the comparator, and the reference voltage E1 is input to the − input terminal of the comparator. The reference voltage E1 is, for example, a value slightly larger than the output voltage Vout when the maximum DAC data is input to the DAC 32 when a resistor having a predetermined resistance value (reference resistor) is connected as the load resistor R2. be able to. Here, it is assumed that the resistance value of the reference resistor is the same value (75Ω in the above example) as the design value of the load resistor R1, which is an internal load resistor. If the output voltage Vout is smaller than the reference voltage E1, the output of the comparator becomes L level, indicating that some external load resistance is connected. When the output voltage Vout exceeds the reference voltage E1, the output of the comparator changes from L level to H level. Thereby, it can be detected that the connection of the external load resistor is released.

  The detection result of the connection detection circuit 36 is output to the control circuit 38. The control circuit 38 inputs an operation signal to the output voltage adjustment circuit 40 in accordance with the detection result of the connection detection circuit 36 together with the error correction circuit operation signal. As will be described later, the detection result of the connection detection circuit 36 may be output to the control unit 12. In this case, the control unit 12 refers to the detection result and outputs an error correction circuit operation signal to the control circuit 38 of the error correction circuit 34 at a predetermined timing. As described above, the control circuit 38 outputs an operation signal to the output voltage adjustment circuit 40 in accordance with the error correction circuit operation signal.

  An example of the circuit configuration of the output voltage adjustment circuit 40 is shown in FIG. As shown in FIG. 4, the output voltage adjustment circuit 40 includes a sample hold circuit 70 and an error amplifier 72. The output terminal of the DAC 32 is connected to the input terminal of the sample hold circuit 70, and the output voltage Vout is input. The output terminal of the sample and hold circuit 70 is connected to the negative input terminal of the error amplifier 72. The sample hold circuit 70 is also provided with an input terminal to which an operation signal is input from the control circuit 38. When the operation signal is input from the control circuit 38, the sample hold circuit 70 outputs the output voltage Vout input from the DAC 32 to the error amplifier 72. Further, after the input of the operation signal is stopped, the sample hold circuit 70 holds (holds) the output voltage Vout input immediately before the input of the operation signal is stopped. The held input signal (output voltage Vout) is output to the negative input terminal of the error amplifier 72. A predetermined reference voltage Vr1 is input to the + input terminal of the error amplifier 72.

  The error amplifier 72 compares the reference voltage Vr1 and the output voltage Vout, amplifies and adjusts the difference so that the difference becomes small, and inputs the amplified difference to the reference voltage input terminal 52 of the DAC 32 as an adjustment circuit output voltage. This adjustment circuit output voltage is used as the reference voltage Vref in the DAC 32. The reference voltage Vr1 is set as the output voltage Vout when the maximum DAC data is generated by the signal pattern generation circuit 30 and input to the DAC 32 in a state where the reference resistance is connected to the DAC output terminal 50 as the load resistor R2. Voltage. A reference voltage adjusted by the error amplifier 72 so that the difference between the output voltage Vout output when the maximum DAC data is input to the DAC 32 in a state where some external load resistance is connected and the reference voltage Vr1 is reduced. Vref (adjustment circuit output voltage) is supplied to the reference voltage input terminal 52.

  In the DAC 32 for current output shown in FIG. 3, assuming that the maximum value of the output voltage Vout is Vomax and the maximum value of the output current Idac is Imax, Vomax is expressed by the following equation.

  Vomax = Imax × R0 (1)

  Here, it can be expressed by Imax = K × Iref (K is a constant determined by a circuit), and the relational expression of Vfs = Rfs × Iref is established in the main current source unit 22. Further, as described above, since Vfs is controlled to be Vref, when these relational expressions are applied to the above expression (1), the following expression (2) is derived.

  Vomax = K × Vref × (Ro / Rfs) (2)

  As shown in Equation (2), the maximum output voltage Vomax is proportional to Vref and R0, and inversely proportional to Rfs. In this embodiment, by adjusting Vref, variations in the output voltage Vout due to an error in the load resistance R0 are suppressed.

  Here, the error correction operation by the error correction circuit 34 will be described in detail with reference to the timing chart of FIG. The timing chart of FIG. 5 shows a timing chart when an external load resistor is connected.

  In response to an instruction from the control unit 12, the energization of the signal generator 18 is started, and the signal generator 18 is shifted from the non-operating state to the operating state. At this stage, video data is not input from the decoder circuit 16, and the signal pattern generation circuit 30 generates DAC data for setting the output voltage Vout of the DAC 32 to 0 and inputs the DAC data to the DAC 32. Further, the output voltage adjusting circuit 40 is maintained in a non-operating state until an operation signal described later is input from the control circuit 38.

  Next, the control unit 12 asserts an error correction circuit operation signal to the control circuit 38 of the error correction circuit 34 (sets to H level). In response to this, the control circuit 38 outputs a control signal to the signal pattern generation circuit 30 so that the maximum DAC data with the maximum output voltage Vout is generated. An operation signal is input to the sample and hold circuit 70 together with this control signal. Note that the input of the maximum DAC data to the DAC 32 is continued while the error correction circuit operation signal is at the H level.

  On the other hand, the connection detection circuit 36 performs load detection as described above, and outputs a signal indicating whether or not an external load resistor is connected to the control circuit 38. When a signal indicating that an external load resistor is connected is input from the connection detection circuit 36, the control circuit 38 outputs an operation signal to the output voltage adjustment circuit 40 to output the output voltage adjustment circuit 40. The operation is performed, the output voltage Vout input to the output voltage adjustment circuit 40 is compared with the reference voltage Vr1, and error correction is performed. On the other hand, when a signal indicating that the external load resistance is not connected is input from the connection detection circuit 36, there is no need to adjust according to the external load resistance. Is terminated without outputting.

  In the error amplifier 72 of the output voltage adjustment circuit 40, error correction is performed as follows. When the external load resistance as the load resistance R2 is smaller than the design value, the output voltage Vout of the DAC 32 is lower than the reference voltage Vr1, and therefore, the error circuit output voltage is set between the output voltage Vout and the reference voltage Vr1. Adjustment is made so that the output voltage Vout of the DAC 32 is increased by adjusting the direction in which the difference is reduced (in this case, in the direction in which the voltage is higher than the voltage before adjustment) (the line when the adjustment circuit output of FIG. See also.)

  On the other hand, when the external load resistance has a resistance value larger than the design value, the output voltage Vout of the DAC 32 exceeds the reference voltage Vr1, so that the difference between the error circuit output voltage and the output voltage Vout and the reference voltage Vr1 becomes small. The output voltage Vout of the DAC 32 is adjusted to be lowered by adjusting the direction (here, in a direction lower than the voltage before adjustment) (see also the line at the time of high resistance connection of the output of the adjustment circuit in FIG. 5). .

  Thereafter, when the error correction circuit operation signal is negated (set to L level) by the control unit 12, the input of the maximum DAC data to the DAC 32 is stopped by the control signal from the control circuit 38. In addition, a signal for stopping the operation is input from the control circuit 38 to the sample hold circuit 70 (end of the adjustment period). Thus, after the error correction circuit operation signal is negated, the sample hold circuit 70 holds the output voltage Vout in the adjustment operation immediately before the error correction circuit operation signal is negated, and the held output voltage Vout is It continues to be input to the error amplifier 72. The error amplifier 72 is maintained in the operating state, and the reference voltage Vref corresponding to the output voltage Vout held by the sample hold circuit 70 is continuously output.

  Thereafter, the video data decoded from the decoder circuit 16 is input to the signal pattern generation circuit 30 according to the control signal of the control unit 12. The signal pattern generation circuit 30 supplies the DAC data to the DAC 32 according to the input data, so that the signal generator 18 operates so as to continue to output the output voltage Vout with suppressed variation.

  As described above, according to the present embodiment, by providing the output voltage adjusting circuit 40 and the control circuit 38, the reference voltage Vref is equal to the output voltage Vout and the reference voltage Vr1 regardless of the value of the external load resistance. Since the difference is adjusted in a decreasing direction and the adjusted reference voltage Vref is supplied to the reference voltage input terminal 52 of the DAC 32, variations in the output voltage Vout can be suppressed. Thereby, more accurate signal transmission becomes possible.

  In this embodiment, the connection of the external load resistor is detected or error correction is performed based on the value of the output voltage Vout of the DAC 32 when the maximum DAC data is generated so that the output voltage Vout is maximized. However, this is only an example, and the present invention is not limited to this. It generates predetermined DAC data other than the maximum DAC data, and detects the connection of the external load resistor according to this. The error correction may be performed.

  In the above embodiment, load detection is performed after the error correction circuit operation signal is asserted. However, the present invention is not limited to this. For example, the output terminal of the connection detection circuit 36 is connected to the control unit 12 instead of the control circuit 38, and a signal for load detection is asserted from the control unit 12 to the control circuit 38 before the error correction circuit operation signal is asserted. As described above, predetermined DAC data (maximum DAC data in the above embodiment) may be generated by the signal pattern generation circuit 30 and load detection may be performed by the connection detection circuit 36.

  In this case, the control unit 12 receives the load detection result from the connection detection circuit 36 and asserts an error correction circuit operation signal to the control circuit 38 when it is determined that the external load resistor is connected. When receiving the error correction circuit operation signal, the control circuit 38 outputs again predetermined DAC data (maximum DAC data in the above embodiment) to the signal pattern generation circuit 30 and outputs the operation signal to the output voltage adjustment circuit. Forty error amplifiers 72 and sample hold circuit 70 are input.

  That is, it may be configured such that the error detection circuit operation signal is asserted when the load is detected first and the control unit 12 determines that the external load resistor is connected.

  Further, when the connection detection circuit 36 inputs predetermined DAC data (maximum DAC data in the present embodiment) to the DAC 32, the output voltage Vout of the DAC 32 is within a predetermined output voltage range. In such a case, it may be configured to output a predetermined signal indicating that some normal load (receiving device 20) is connected.

  For example, a window comparator composed of two comparators can be included. An upper limit value VH of a predetermined output voltage range is input as a reference voltage to the negative input terminal of one comparator (A1), and a positive input terminal is connected to the output terminal of the DAC 32. Further, the lower limit value VL of the output voltage range is input as a reference voltage to the + input terminal of the other comparator (A2), and the − input terminal is connected to the output terminal of the DAC 32. As a result, when the output voltage Vout obtained from the output terminal is within the range of VL to VH, the outputs of the two comparators are H level, and the output voltage Vout obtained from the output terminal is less than VL. In this case, the comparator A1 becomes L level, and when it exceeds VH, the output of the comparator A2 becomes L level. Here, when the outputs of the two comparators are at the H level, it can be determined that the external load resistor is connected. When the output of the comparator A1 is L level, it can be determined that the DAC output terminal 50 is short-circuited. When the output of the comparator A2 is L level, it can be determined that the external load resistor is not connected. As described above, the connection detection circuit 36 may output a detection signal indicating which of the three states of the state where the external load resistor is connected, the state where the external load resistor is not connected, and the short circuit state. You may comprise so that it can do.

  In this way, the output voltage Vout is compared with the upper limit value VH and the lower limit value VL, thereby protecting the connection of an external load resistor having an unintended resistance value from being prevented from circuit operation. Can do.

  In this embodiment, an example in which load detection is performed and error correction is performed before video data is input has been described. However, when it is detected as a result of load detection that an external load resistor is not connected. The load detection may be performed again at predetermined time intervals, and the error correction may be performed when a state in which the external load resistance is connected is detected from a state in which the external load resistance is not connected.

  [Second Embodiment]

  In the first embodiment, an example will be described in which an external load resistance is detected and error correction (adjustment operation) is performed by the error correction circuit 34 before video data is input after the signal generator 18 is in an operating state. However, in this embodiment, an example in which error correction is performed at an arbitrary timing during input of video data will be described. Note that the configuration of the information processing apparatus 10 and the configuration of the signal generator 18 are the same as those in the first embodiment, and thus description thereof is omitted.

  During operation of the signal generator 18, normal video data is input to the signal pattern generation circuit 30 to start displaying an image, and then forcibly generating some predetermined DAC data to perform error correction. When error correction is performed during a period in which video is displayed on the receiving device 20 (display period), a video based on DAC data that is not related to the video data is displayed on the video screen (even if the time is extremely short). It will be.

  Therefore, in the present embodiment, as shown in FIG. 6, control is performed so that error correction is performed by the error correction circuit 34 during a period in which no video is displayed (non-display period). As shown in the figure, in a non-display period of one scanning period, a synchronization signal period in which a synchronization signal is output, and a color detection reference signal output period in which a reference signal (color burst) for performing color detection is output. Exists. Therefore, it is more preferable to perform error correction in a period excluding a signal period necessary for such display control in the non-display period.

  For example, the signal pattern generation circuit 30 is configured to input a synchronization signal to the control circuit 38 from the signal pattern generation circuit 30 to the control circuit 38 every time a non-display period after the end of the display period arrives. 12, the control unit 12 outputs an error correction circuit operation signal at predetermined time intervals, and the control circuit 38 receives a synchronization signal from the signal pattern generation circuit 30 after the error correction circuit operation signal is input. When input, an operation signal can be input to the error correction circuit 34 to perform error correction in the same manner as in the first embodiment.

  Alternatively, when the control unit 12 monitors the video data input to the signal pattern generation circuit 30 and detects that the non-display period after the end of the display period has arrived, the error correction circuit operation signal is input to the control circuit 38. You may make it do. In this case, it is not necessary to output the error correction circuit operation signal for each detection. For example, the error correction circuit operation signal may be output at a predetermined interval.

  In the present embodiment, as in the first embodiment, error correction is performed in a state where a normal external load resistor (receiving device 20) is connected by the connection detection circuit 36, but in a normal use state. Since the video data can be expected to be distributed from the minimum value to the maximum value, the connection detection circuit 36 is always operated during the period of outputting the input video data, and the connection detection circuit 36 is supplied with the output voltage Vout of the DAC 32. To monitor. Then, during a period in which a detection signal indicating that the external load resistor is not connected is continuously output beyond the predetermined time from the connection detection circuit 36, it is determined that the external load resistor is disconnected, and the control unit 12 Even if an error correction circuit operation signal is input from the control circuit 38, the control circuit 38 does not output an operation signal or a control signal and does not perform error correction. In addition, when the output terminal of the connection detection circuit 36 is connected to the control unit 12, for example, an error correction circuit operation signal is periodically input to the control circuit 38 only during a period in which the external load resistor is connected. The error correction circuit operation signal can be configured not to be input to the control circuit 38 during a period when the external load resistor is not connected.

  In a state where it is detected that the external load resistor is connected, the control circuit 38 is configured to generate the maximum DAC data when the error correction circuit operation signal is input. A control signal is input to the control signal and an operation signal is input to both the sample hold circuit 70 and the error amplifier 72. Since the subsequent error correction method by the error correction circuit 34 is performed in the same manner as in the first embodiment, description thereof is omitted here. With such a configuration, error correction can be performed efficiently during a necessary period.

  In addition, instead of constantly monitoring the output voltage Vout and detecting the load, in the present embodiment, predetermined DAC data (for example, maximum DAC data) is generated in the signal pattern generation circuit 30 in the non-display period and the load is detected. May be performed. When the error correction circuit operation signal is input in the state where the connection of the external load resistor is detected, the control circuit 38 outputs the operation signal to the output voltage adjustment circuit 40 and generates the maximum DAC data again. Output a control signal. When the output terminal of the connection detection circuit 36 is connected to the control unit 12, an error correction circuit operation signal is output to the control circuit 38 when connection of an external load resistor is detected as described above. You may make it do.

  Further, the error correction may be performed when it is detected that the external load resistance is connected after it is detected that the external load resistance is not connected.

  Furthermore, when load detection is performed by inputting predetermined DAC data to the DAC 32, the value of the output voltage Vout for each load detection is monitored, and it is detected that an external load resistor is connected and output. When it is determined that the voltage Vout has changed, an error correction circuit operation signal may be input from the control unit 12 to the control circuit 38 to perform the error correction. In other words, the error correction may be performed when it is recognized that the external load resistance has changed, and the error correction may not be performed when the load is the same.

  As described above, according to the present embodiment, it is possible to adjust (error correction) the output voltage Vout of the DAC 32 at an arbitrary timing. As a result, the error correction time interval can be shortened as compared with the case where error correction is performed only immediately after the signal generator 18 enters the operating state, and therefore, it is possible to cope with load fluctuations over time. Thus, the output voltage can be further stabilized.

  This is because, for example, an error may occur between the external load resistance and the reference resistance due to secular change or sudden abnormality (failure, etc.) during use of the receiving apparatus 20. Is required to be continuously adjusted even when the apparatus is in operation (for example, while displaying video data video on a television monitor or the like). Thus, as described in the present embodiment, such a need can be met by configuring such that error correction can be performed while video data output is continued.

  [Other embodiments]

  In the first and second embodiments, the example in which the sample and hold circuit 70 is provided on the input side of the error amplifier 72 has been described. However, the present invention is not limited to this. For example, the sample hold circuit 70 is not necessarily provided on the input side of the error amplifier 72. For example, as shown in FIG. 7, the sample hold circuit 70 may be installed on the output side of the error amplifier 72, that is, between the error amplifier 72 and the reference voltage input terminal 52. In this configuration, during the adjustment period, the error amplifier 72 outputs the adjustment circuit output voltage (Vref) corresponding to the difference between the output voltage Vout and the reference voltage Vr1, and the sample hold circuit 70 is supplied from the error amplifier 72. The input adjustment circuit output voltage is output. After the adjustment period, the sample hold circuit 70 holds the value of the adjustment circuit output voltage adjusted in the adjustment period. Since the held voltage value continues to be output to the reference voltage input terminal 52 after being held by the sample hold circuit 70, it is not necessary to operate the error amplifier 72. Therefore, in this case, when the error correction circuit operation signal is negated, the control circuit 38 can control the error amplifier 72 to be in a non-operation state.

  In the case of such a configuration, in the first embodiment, the operation signal is controlled to be input to both the sample hold circuit 70 and the error amplifier 72 when the external load resistance is detected. The circuit 38 or the control unit 12 is configured, and the control circuit 38 and the control unit 12 may be configured so that a stop signal for stopping the adjustment operation is input to the sample hold circuit 70 and the error amplifier 72 after the adjustment period ends. . In the second embodiment, the operation signal may be input and the stop signal may be input as described above.

  Further, as shown in FIG. 8, the output voltage adjustment circuit 40 may be configured by a switch element 74 and an integration circuit 76. The switch element 74 is turned on when an operation signal is input from the control circuit 38. As a result, the output voltage Vout is input to the negative input terminal of the integrating circuit 76. The reference voltage Vr1 is input to the + input terminal of the integrating circuit 76.

  While the error correction circuit operation signal is at the H level, the switch element 74 is kept on. When the error correction circuit operation signal is negated, the control circuit 38 inputs a non-operation signal to the switch element 74 and turns off. State. As a result, charging of the capacitor provided in the integration circuit 76 proceeds while the switch element 74 is in the ON state, and saturates to the value of the adjustment circuit output voltage corresponding to the difference between the output voltage Vout and the reference voltage Vr1. When the switch element 74 is turned off, the adjustment circuit output voltage held by the capacitor is continuously input to the reference voltage input terminal 52 as the reference voltage Vref.

  In the configuration of FIG. 8, a resistance element may be provided between the negative input terminal of the integration circuit 76 and the switch element 74. Thereby, the current flowing through the capacitor of the integrating circuit 76 can be adjusted, and this configuration is effective when it is desired to limit the current flowing through the capacitor.

  As shown in FIGS. 4, 7, and 8, both the output voltage Vout and the reference voltage Vr1 are analog signals, and in the case of a configuration in which the comparison result is also processed and output as an analog signal, the analog signal It is not necessary to provide an ADC that converts the digital signal into a digital signal and a DAC that converts the digital signal into an analog signal, and can be realized with a relatively simple circuit configuration as compared with the case where a DAC or an ADC is provided. For this reason, it becomes an advantageous configuration for further downsizing and cost reduction of the chip.

  Further, as shown in FIG. 9, the output voltage adjustment circuit 40 may be configured by a comparator 80, a counter 82, and a DAC 84.

  When the control circuit 38 inputs operation signals to the comparator 80, the counter 82, and the DAC 84, the operation of each component is started.

  The output voltage Vout of the DAC 32 is input to the + input terminal of the comparator 80, and the reference voltage Vr1 is input to the − input terminal. The comparator 80 compares the output voltage Vout with the reference voltage Vr1. When the output voltage Vout is higher than the reference voltage Vr1, the output of the comparator 80 is H level, and when the output voltage Vout is lower than the reference voltage Vr1, the output of the comparator 80 is L level. .

  The counter 82 counts the output of the comparator 80 in synchronization with a separately input clock, and outputs the count data to the DAC 84 in parallel. The DAC 84 converts the input count data into analog to generate an adjustment circuit output voltage, and inputs this to the reference voltage input terminal 52 as the reference voltage Vref.

  FIG. 10 shows an example of a timing chart of this circuit.

  When the output voltage Vout is lower than the reference voltage Vr1, the output comp of the comparator 80 is at L level. The counter 82 counts up in synchronization with the clock while the output of the comparator 80 is at the L level. In accordance with the count output Count of the counter 82, the adjustment circuit output voltage of the DAC 84 also increases. When the output voltage Vout exceeds the reference voltage Vr1, the output of the comparator 80 becomes H level and the adjustment operation ends. When the output of the comparator 80 changes from the L level to the H level, the counter 82 holds the count data Count immediately before the change (that is, immediately before the end of the adjustment operation), and thereafter outputs the held count data Count to the DAC 84. Keep doing.

  Although the illustration when the output voltage Vout is higher than the reference voltage Vr1 is omitted, in this case, the operation is the reverse of the operation when the output voltage Vout is lower than the reference voltage Vr1. That is, the output comp of the comparator 80 becomes H level, and the counter 82 counts down in synchronization with the clock while the output of the comparator 80 is at H level. In accordance with the count result (count data) Count of the counter 82, the output voltage of the adjustment circuit of the DAC 84 also decreases. When the output voltage Vout falls below the reference voltage Vr1, the output of the comparator 80 becomes L level and the adjustment operation ends. . When the output of the comparator 80 changes from the H level to the L level, the counter 82 holds the count data Count immediately before the change (that is, immediately before the end of the adjustment operation), and thereafter outputs the held count data Count to the DAC 84. Keep doing.

  Since the DAC 84 converts the count data output from the counter 82 into an analog signal and outputs the analog signal, the DAC 84 continues to output a constant voltage value (adjusted Vref) after the adjustment operation ends. According to this configuration, the reference voltage Vref is digitally (fixedly) held and output as compared with the configurations illustrated in FIGS. 4, 7, and 8 in which the adjustment circuit output voltage is sampled and held in an analog manner. Therefore, the accuracy of error correction is improved with high reproducibility and can be used stably.

  Further, as shown in FIG. 11, the output voltage adjustment circuit 40 may be configured by an ADC 86, a latch circuit 87, and a DAC 88. The ADC 86, the latch circuit 87, and the DAC 88 each start operating when an operation signal is input from the control circuit 38. Here, it is assumed that the voltage range that can be input to the ADC 86 matches the voltage range that is output from the DAC 88.

  The output voltage Vout of the DAC 32 is input to the input terminal of the ADC 86. Note that a value of the reference voltage Vr1 is set in advance in the ADC 86. When the output voltage Vout is lower than the reference voltage Vr1, the ADC 86 is stepwise like the count output Count of FIG. 10 so that the value of the adjustment circuit output voltage gradually increases until the output voltage Vout exceeds the reference voltage Vr1. Generate and output an increasing digital signal. The latch circuit 87 holds the output of the ADC 86 and outputs it to the DAC 88. The DAC 88 converts the digital signal output from the latch circuit 87 into an analog signal and outputs the voltage as the reference voltage Vref (adjustment circuit output voltage). In accordance with the output of the ADC 86, the adjustment circuit output voltage of the DAC 88 also increases, and the adjustment operation ends when the output voltage Vout exceeds the reference voltage Vr1. On the other hand, when the output voltage Vout is higher than the reference voltage Vr1, the ADC 86 generates and outputs a digital signal that gradually decreases the value of the adjustment circuit output voltage until the output voltage Vout falls below the reference voltage Vr1. In response to the output of the ADC 86, the output voltage of the adjustment circuit of the DAC 88 also decreases, and the adjustment operation ends when the output voltage Vout falls below the reference voltage Vr1.

  After completion of the adjustment operation, the operation of the ADC 86 is stopped, and the latch circuit 87 holds (latches) the digital signal output from the ADC 86 immediately before the end of the adjustment operation, and continues to output the held digital signal to the DAC 88. The DAC 88 converts the digital signal output from the latch circuit 87 into an analog signal and continues to output it as the reference voltage Vref. Also with this configuration, similarly to the configuration of FIG. 9, the reference voltage Vref can be digitally held and output, the accuracy of error correction can be improved with good reproducibility, and can be used stably.

  In the configuration of FIG. 11, an error amplifier may be provided before the ADC 86. The error amplifier is configured such that the output voltage Vout is input to the + input terminal and the reference voltage Vr1 is input to the − input terminal, and the difference is amplified and output to the ADC 86. Thereby, for example, when the voltage range that can be input to the ADC 86 and the voltage range that is output from the DAC 88 are different, this can be matched.

  Further, an operation stabilizing circuit such as a delay circuit or a filter circuit may be provided between the ADC 86 and the DAC 88. For example, depending on the sensitivity of the ADC 86 and the DAC 88, the control may not be converged and the amplitude may be repeated. Therefore, by providing an operation determination circuit such as a delay circuit or a filter circuit, the control can be stabilized. In this case, the latch circuit 87 is provided before or after the operation stabilization circuit. Further, a circuit having the function of the operation stabilization circuit and the latch circuit 87 may be provided between the ADC 86 and the DAC 88.

  In addition to the combination of a combination circuit such as a gate and a sequential circuit including an F / F (flip-flop), the circuit block of the operation stabilization circuit includes a circuit including a microcontroller (MCU). Of course.

  In each of the above-described embodiments and other embodiments, the example in which the error is corrected by adjusting the reference voltage Vref input to the reference voltage input terminal 52 has been described. However, the present invention is not limited to this. For example, the error correction may be performed by adjusting the DAC data generated by the signal pattern generation circuit 30.

  FIG. 12 shows a configuration example when adjusting the DAC data generated by the signal pattern generation circuit 30. 12, parts that are the same as or equivalent to those in FIG. 2 are given the same reference numerals, and descriptions thereof are omitted.

  In FIG. 12, the signal generator 18 includes a signal pattern generation circuit 30, a current output type DAC 32, an error correction circuit 44, and a connection detection circuit 36.

  The error correction circuit 44 according to the present embodiment corrects the DAC data generated by the signal pattern generation circuit 30, thereby correcting the error of the output voltage Vout of the DAC 32 caused by the load resistance error. The error correction circuit 44 includes a control circuit 38 and an output voltage adjustment circuit 42. The control circuit 38 outputs an operation signal to the output voltage adjustment circuit 42 in response to the input of the error correction circuit operation signal from the control unit 12 to operate the output voltage adjustment circuit 42, and causes the signal pattern generation circuit 30 to operate. On the other hand, a control signal is output to generate predetermined DAC data.

  The output voltage adjustment circuit 42 is connected to the output terminal of the DAC 32, and receives the output voltage Vout according to the predetermined DAC data. The output voltage adjustment circuit 42 outputs a coefficient for adjusting the DAC data to the signal pattern generation circuit 30 in accordance with the output voltage out. Also in the present embodiment, the predetermined DAC data is the maximum DAC data that maximizes the output voltage Vout of the DAC 32.

  Here, an example of the circuit configuration of the output voltage adjusting circuit 42 is shown in FIG. As shown in FIG. 13, the output voltage adjustment circuit 42 includes an ADC 90 and a logic circuit 92. The ADC 90 and the logic circuit 92 each start to operate when an operation signal is input from the control circuit 38.

  The output voltage Vout of the DAC 32 is input to the input terminal of the ADC 90. Note that a value of the reference voltage Vr1 is set in advance in the ADC 90. The ADC 90 converts the ratio of the output voltage Vout to the reference voltage Vr1 into a digital signal and outputs it. The logic circuit 92 calculates the reciprocal number of the digital signal input from the ADC 90 and outputs a digital signal corresponding to the reciprocal value to the signal pattern generation circuit 30. The signal pattern generation circuit 30 generates DAC data obtained by multiplying the original DAC data generated from the video data by the reciprocal (hereinafter referred to as a coefficient) indicated by the digital signal input from the logic circuit 92, and outputs the DAC data to the DAC 32. When the error correction circuit operation signal is negated, the adjustment operation of the output voltage adjustment circuit 44 is stopped, and the logic circuit 92 holds the coefficient obtained immediately before the adjustment operation is stopped and continues to output it to the signal pattern generation circuit 30. The signal pattern generation circuit 30 generates DAC data corresponding to the video data using the coefficient given from the logic circuit 92.

  Of course, the circuit block of the logic circuit 92 includes a combination of a combination circuit such as a gate and a sequential circuit including an F / F, and a circuit including a microcontroller (MCU).

  With this configuration, for example, when the output voltage Vout is 10% higher than the reference voltage Vr1, the signal is generated so that the DAC data of the signal pattern generation circuit 30 is multiplied by the reciprocal of 1.1 (1 / 1.1, approximately 0.91). A coefficient is given to the pattern generation circuit 30 and feedback is applied. Specifically, for example, when the analog video data indicates a value of 100, the signal pattern generation circuit 30 has a value “91” obtained by multiplying 100 by the coefficient 0.91 input from the logic circuit 92. A digital signal (DAC data) indicating a value is generated. As described above, the output voltage adjusting circuit 42 shown in FIG. 13 has a configuration in which the reciprocal is calculated and supplied to the signal pattern generating circuit 30 as a coefficient of DAC data. Also with this configuration, as in the configuration of FIG. 9, coefficients can be digitally held and output, error correction accuracy can be improved with high reproducibility, and can be used stably.

  In the configuration shown in FIG. 13 as well, an error amplifier may be provided in the preceding stage of ADC 90, as described in the configuration in FIG.

  Furthermore, in addition to the above components, as shown in the above equation (2), the maximum value Vomax of the output voltage Vout of the DAC 32 is a function of R0, Vref, Rfs, and K. In addition to correcting the error (instead of correcting Vref), the error can be corrected by adjusting the adjustment output resistance Rfs and the load resistance R0 (however, the internal load resistance can be adjusted). Similarly, it is also possible to change the constant K determined by the circuit.

  Specifically, for example, although not shown, a resistance circuit in which a plurality of resistance elements each having a switch connected in series is connected in parallel is configured as an internal load resistance (load resistance R1) or an adjustment output resistance Rfs. The switches are configured to switch according to the difference between the output voltage Vout and the reference voltage Vr1. Thereby, the value of the internal load resistance or the adjustment output resistance Rfs can be adjusted. Even when the internal load resistance or the adjustment output resistance Rfs is changed, the output of the output voltage adjustment circuit exemplified above can be used. For example, in FIG. 9 and FIG. 11, a digital adjustment circuit output voltage is output from the output voltage adjustment circuit 40. The digital value is converted into an input signal for switching on / off of the switch of the resistor circuit and given to each switch. be able to. For this reason, a conversion circuit is required between the adjustment circuit output voltage and the resistance circuit, but this also causes fluctuations in the output voltage Vout due to the error of the load resistance R2 as in the case of adjusting the Vref and DAC data. Can be suppressed.

  Normally, the value of K is determined according to the amount of current flowing through the current cell 24. In order to adjust the amount of current, an additional resistor circuit is provided between each current cell of the DAC 32 and the DAC output terminal 50. In the same manner as described above, the resistance value of the resistor circuit may be changed, and the value of K may be changed according to the output of the output voltage adjustment circuit to perform error correction.

  Although various variations have been described above, the output voltage Vout of the DAC 32 when the maximum DAC data is generated (here, the maximum DAC data is used. However, as described above, the maximum DAC data may not be used) is specified. It is essential that the output voltage Vout of the DAC 32 is corrected in comparison with the voltage of the above. The correction method and the configuration of the correction circuit may be various, and the above description Of course, the circuit is not limited to the above.

  In each of the above-described embodiments, the information processing apparatus 10 is a video camera. However, the present invention is not limited to this. For example, no image sensor or encoding circuit is provided, and video data input from the outside is provided. It may be an information processing device that operates as a storage medium for storing. In each of the above embodiments, the information processing apparatus 10 encodes video data obtained by photographing with the image sensor 11 and stores the encoded video data in the memory 15. The video data stored in the memory 15 is decoded and signaled. Although the example configured to input to the generator 18 has been described, the present invention is not limited to this, and video data obtained by photographing with the image sensor 11 is stored in the memory 15 without being encoded and stored in the memory. The video data may be input to the signal generator 18 without being decoded.

DESCRIPTION OF SYMBOLS 10 Information processing apparatus 11 Image pick-up element 12 Processor 14 Encoder circuit 15 Memory 16 Decoder circuit 18 Signal generator 20 Reception apparatus 30 Signal pattern generation circuit 32 DAC
34, 44 Error correction circuit 36 Connection detection circuit 38 Control circuit 40, 42 Output voltage adjustment circuit 50 DAC output terminal 52 Reference voltage input terminal 54 Output voltage adjustment terminal

Claims (12)

Based on the input video data or a predetermined control signal, a signal generating means for generating a digital signal and outputting it from the output end, and an output end of the signal generating means is connected to the input end, from the input end It has a digital-analog conversion means that converts the input digital signal into an analog current and outputs it from the output end. An internal load resistor is connected in advance to the output end of the digital-analog conversion means and an external load resistance can be connected. Signal conversion means,
The output voltage output from the output terminal of the digital-analog conversion means is compared with each of the predetermined upper limit value and lower limit value of the output voltage, and the output voltage is not less than the lower limit value and not more than the upper limit value. Detection means for outputting a detection signal indicating that the external load resistor is connected to the output terminal of the digital-analog conversion means,
Control means for controlling the signal generation means by inputting the control signal to the signal generation means during a predetermined first period of the operation period of the signal conversion means;
When the detection signal is received in the first period, a digital signal is generated based on the control signal in a state in which a reference resistor having a predetermined resistance value is connected to the output terminal of the digital-analog conversion unit. A first reference voltage set as an output voltage output from the output terminal of the digital-analog conversion means, and a digital signal based on the control signal in a state where an external load resistor is connected to the output terminal of the digital-analog conversion means. When the signal is generated, the output voltage output from the output terminal of the digital-analog conversion means is compared, and an adjustment operation for adjusting the signal conversion means in a direction in which the difference decreases is started, and the signal conversion In the second period in which the control signal is not input to the signal generating means in the operation period of the means, the first immediately before the second period And adjusting means for controlling the signal conversion means as adjusted adjusted state is maintained between,
A signal generator comprising: The signal generator according to claim 1, wherein the first period is provided in a non-display period excluding a display period in which a video is displayed based on the video data. The detection means compares the output voltage output from the output terminal of the digital-analog conversion means with each of a predetermined upper limit value and lower limit value of the output voltage, and the output voltage is less than the lower limit value. In the case or when exceeding the upper limit value, a non-detection signal indicating that the external load resistance is not connected to the output terminal of the digital-analog conversion means is output,
The adjusting means does not start the adjusting operation even when the non-detection signal is received in the first period;
The signal generator according to claim 1 or 2. The digital-analog conversion means includes a switch element that is turned on and off by a digital signal generated by the signal generation means and a current cell portion in which a plurality of current cells connected in series are connected in parallel, and a predetermined resistance. A current source unit configured to generate a reference current by supplying a second reference voltage to the resistor and to input the plurality of transistors;
When the adjustment unit receives the detection signal in the first period, the adjustment unit is configured to reduce the difference based on a comparison result between the first reference voltage and the output voltage of the digital / analog conversion unit. The adjustment operation which adjusts a voltage is performed, and in the second period, the second reference voltage adjusted in the first period is held and supplied to the current source unit. The signal generator according to Item. The adjusting means includes
When the detection signal is received in the first period, the first reference voltage is compared with the output voltage of the digital-to-analog converter, and if the output voltage is greater than the first reference voltage, the first reference voltage is A comparator that outputs a second level signal when the output voltage is smaller than the first reference voltage;
When the detection signal is received in the first period, the signal output from the comparator is counted according to a predetermined clock signal to output count data as the count result, and in the second period, A counter that holds and outputs count data immediately before the end of the first period;
A digital-to-analog converter that converts the count data output from the counter into an analog signal in the first period and the second period and supplies the analog signal as the second reference voltage;
The signal generator of Claim 4 comprised including these. The adjusting means includes
When the detection signal is received in the first period, the output voltage of the digital-analog conversion means is input and the input output voltage is output, and in the second period, the output of the first period A holding circuit that holds the output voltage of the digital-analog conversion means that is input immediately before the end and outputs the held output voltage;
In the first period and the second period, the output voltage output from the holding circuit and the first reference voltage are compared and the difference is amplified, and the amplified voltage is used as the second reference voltage. An error amplifier for supplying to the current source unit;
The signal generator of Claim 4 comprised including these. The adjusting means includes
When receiving the detection signal in the first period, an error amplifier that compares the first reference voltage with the output voltage of the digital-analog conversion means, amplifies the difference, and outputs the error amplifier;
When the detection signal is received in the first period, the voltage output from the error amplifier is input, the input voltage is supplied to the current source unit as the second reference voltage, and the second period A holding circuit that holds the voltage input from the error amplifier immediately before the end of the first period and supplies the held voltage to the current source unit as the second reference voltage;
The signal generator of Claim 4 comprised including these. The adjusting means includes
A switch element that is turned on when the detection signal is received in the first period and turned off in other periods ;
The output terminal of the digital / analog conversion means is connected to the output terminal of the digital / analog conversion means through the switch element, and the switch element is turned on and the output voltage of the digital / analog conversion means is input. 1 is compared with a reference voltage and a voltage corresponding to the difference is integrated and held. When the switch element is switched from on to off and the input of the output voltage of the digital-analog converter is stopped, the integration is performed. An integrating circuit for supplying the held voltage to the current source unit as the second reference voltage;
The signal generator of Claim 4 comprised including these. The adjusting means includes
When the detection signal is received in the first period, the first reference voltage is compared with the output voltage of the digital-analog conversion means, and the voltage changes in a direction in which the output voltage approaches the first reference voltage. An analog-digital converter that converts an analog waveform into a digital signal and outputs it;
In the first period, the digital signal output from the analog-digital converter is input and the input digital signal is output. In the second period, immediately before the end of the first period. A holding circuit that holds and outputs the input digital signal; and
A digital-to-analog converter that converts a digital signal output from the analog-to-digital converter into an analog voltage and supplies the analog signal to the current source unit in the first period and the second period; The signal generator of Claim 4 comprised including these. The signal generating means adjusts the value of the digital signal to be generated based on the video data or the control signal, using the coefficient given by the adjusting means,
When the adjustment means receives the detection signal in the first period, the adjustment means outputs the output voltage of the digital-analog conversion means based on the comparison result between the first reference voltage and the output voltage of the digital-analog conversion means. An adjustment operation for adjusting the coefficient in a direction in which a difference from one reference voltage becomes smaller is started, and the signal after adjustment by the adjustment operation in the first period is held in the second period. It supplied to the generating means,
The signal generator of any one of Claims 1-3. A signal generator according to any one of claims 1 to 10,
Imaging means for capturing a subject and acquiring video data;
Storage means for storing video data imaged by the imaging means;
Input means for inputting the video data stored in the storage means to the signal generating means of the signal generating device;
An information processing apparatus comprising: Based on the input video data or a predetermined control signal, a signal generating means for generating a digital signal and outputting it from the output end, and an output end of the signal generating means is connected to the input end, from the input end It has a digital-analog conversion means that converts the input digital signal into an analog current and outputs it from the output end. An internal load resistor is connected in advance to the output end of the digital-analog conversion means and an external load resistance can be connected. A signal adjustment method performed by a simple signal conversion device,
The output voltage output from the output terminal of the digital-analog conversion means is compared with each of the predetermined upper limit value and lower limit value of the output voltage, and the output voltage is not less than the lower limit value and not more than the upper limit value. A detection signal indicating that the external load resistor is connected to the output terminal of the digital-analog conversion means,
In a first predetermined period of the operation period of the signal converting means, the control signal is input to the signal generating means to control the signal generating means,
When the detection signal is received in the first period, a digital signal is generated based on the control signal in a state in which a reference resistor having a predetermined resistance value is connected to the output terminal of the digital-analog conversion unit. A first reference voltage set as an output voltage output from the output terminal of the digital-analog conversion means, and a digital signal based on the control signal in a state where an external load resistor is connected to the output terminal of the digital-analog conversion means. Compare the output voltage output from the output terminal of the digital-analog conversion means when a signal is generated, and start an adjustment operation to adjust the signal conversion means in a direction in which the difference is reduced ,
In the second period in which the control signal is not input to the signal generation unit in the operation period of the signal conversion unit, the adjustment state adjusted in the first period immediately before the second period is maintained. Controlling the signal conversion means;
Signal adjustment method.