JP5867906B2 - Intentionally contaminated wafer heat treatment method - Google Patents

Description

  The present invention relates to a gettering technique which is a method for removing harmful impurities from a highly integrated device, and more particularly to a method for intentionally contaminating a silicon wafer with an impurity element in order to evaluate the gettering capability.

  As the density of devices such as semiconductor integrated circuits is increased and the integration is increased, stabilization of device operation has been desired. In particular, improvement of characteristic values such as leakage current and oxide film breakdown voltage is an important issue.

  However, in the manufacturing process of semiconductor integrated circuits, the possibility of contamination with impurities such as undesired heavy metals such as Cu, Fe, and Ni cannot be denied. It is widely known that these heavy metal impurities significantly degrade the above-described leakage current and oxide breakdown voltage characteristics in a solid solution or precipitated state in a silicon single crystal.

  Gettering technology, which is a method for removing these heavy metal impurities, is widely known in the world. Each of these methods has different characteristics, and there are elements that can be removed and their applicable range. Therefore, depending on the type of device to be manufactured and its manufacturing method, a wafer with the optimum gettering technology can be obtained. Need to use.

  However, even if the target device and its manufacturing process are determined, it is not clear which wafer has the optimal gettering layer, and the gettering capability is evaluated in advance by some method, and the wafer to be used is determined. It is necessary to select. As an evaluation method, an element that is likely to be contaminated (hazardous impurities) is intentionally contaminated and appropriately diffused inside the wafer, and then the appropriate evaluation method is simple but direct knowledge can be obtained. Has been widely practiced since.

  As an invention related to impurity contamination in a wafer, Patent Document 1 discloses a method for measuring the amount of metal contamination on a wafer. The invention of Patent Document 1 is an invention relating to a method for measuring the amount of metal contamination of a wafer to be measured by a hot plate method, in order to prevent contamination of the wafer to be measured by metal contained in the hot plate itself. In addition, another wafer is interposed between the measurement target wafer and the hot plate.

JP 2003-130822 A

  By the way, in order to intentionally contaminate a silicon wafer with an impurity element, it is necessary to perform a heat treatment step for diffusing the impurity element into the silicon wafer. Special care must be taken when diffusing impurity elements in the heat treatment process. For example, a furnace that has once intentionally contaminated and diffused Fe is already contaminated with Fe, and if another clean wafer is introduced, it is automatically contaminated with Fe. It becomes an inappropriate furnace for diffusion and introduction.

  In order to avoid this, after the heat treatment of the intentionally contaminated wafer, the cleanliness of the furnace may be restored by some method. For example, if heat treatment is performed at 1200 ° C. for a long time in a state where nothing is put in the furnace, the contaminating elements will eventually sublimate and be discharged out of the system, and the cleanliness will be restored. There is also a method of replacing all contaminated members in the furnace with clean new members. However, both methods are time consuming and economically disadvantageous.

  There are other methods. For example, if the target element is three types of Fe, Ni, and Cu, it is a method of preparing three separate furnaces. If it is desired to change the concentration of contamination, furnaces may be prepared for each concentration. With this method, although the target element is contaminated, it is not necessary to be contaminated with unintended elements. However, this method also requires many furnaces, so the equipment to be prepared must be large.

  The present invention has been made in view of the above problems, and provides a heat treatment method in which only a target impurity element is introduced into a silicon wafer, non-target elements are not mixed into the silicon wafer, and the furnace is not contaminated as much as possible. This is the issue.

In order to solve the above-mentioned problems, the present invention is a method for performing a heat treatment for diffusing the intentionally contaminating element adhered to the silicon wafer surface into the contamination target wafer, which is the silicon wafer,
The front and back surfaces of the wafer to be contaminated are respectively dummy wafers that are different silicon wafers, and a gap is formed between them, and then the heat treatment is performed.

  According to the present invention, the heat treatment is performed in a state where the front and back surfaces of the contamination target wafer are sandwiched between the dummy wafers. At this time, since a gap is formed between the contamination target wafer and the dummy wafer (because the contamination target wafer and the dummy wafer are not in direct contact), an unintended element was temporarily mixed into the dummy wafer from the furnace. However, it is possible to suppress the entry of elements other than the intended object into the contamination target wafer. That is, only the target impurity element can be introduced into the contamination target wafer. Further, since the gap is formed between the contamination target wafer and the dummy wafer, it is possible to prevent the intentional contamination element attached to the surface of the contamination target wafer from being transferred to the dummy wafer. That is, contamination from the contamination target wafer to the furnace can be suppressed via the dummy wafer.

  Further, it is preferable that an oxide film is formed on one side or both sides of the dummy wafer. Since the diffusion of the contaminating elements in the dummy wafer is suppressed by the oxide film, the contamination from the furnace to the contamination target wafer and the contamination from the contamination target wafer to the furnace can be further suppressed.

  Moreover, it is preferable to form a gap by sandwiching a small piece made of a silicon wafer between the contamination target wafer and the dummy wafer. According to this, since the small piece is made of a silicon wafer that is cleaner than metal or the like, impurities can be prevented from being mixed into the contamination target wafer from the small piece.

  Further, the gap between the contamination target wafer and the dummy wafer is preferably 500 μm or more. If the distance between the contamination target wafer and the dummy wafer is too narrow, there is a possibility that the contamination element will diffuse from the contamination target wafer to the dummy wafer or from the dummy wafer to the contamination target wafer. By setting the gap to be 500 μm or more, the diffusion can be effectively prevented.

It is the figure which showed embodiment of heat processing in the example which the contamination target wafer 1 and the dummy wafer 21 contacted directly. It is the figure which showed heat processing embodiment in the example which pinched | interposed the wafer 1 to be contaminated with the dummy wafer 24 with the oxide film 22 between. It is the figure which showed embodiment of the heat processing of this invention. 1 is a plan view of a contamination target wafer 1. FIG. It is the flowchart which showed the process of the heat processing method of this invention.

  Embodiments of a method for heat treating a intentionally contaminated wafer according to the present invention will be described below with reference to the drawings. First, considerations up to the idea of the present invention will be described. Conventionally, when a silicon wafer is intentionally contaminated with a target element, the element is applied to the surface by some method, and the silicon wafer is put into an electric furnace and diffused in order to diffuse it into the silicon wafer. However, in this method, if the electric furnace is already contaminated with another element, the wafer is contaminated by that element, and it is difficult to introduce only the target element into the wafer. Further, if the electric furnace is clean, the furnace is contaminated with intentional contaminant elements, and the heat treatment target wafer is contaminated at the next use.

  In order to prevent this, a method of sandwiching both surfaces of the contamination target wafer with another silicon wafer (dummy wafer) is conceivable. An embodiment of the heat treatment by this method is shown in FIG. That is, in this method, as shown in FIG. 1A, after applying heavy metal impurities 3 (illustrated by white circles) such as Fe on the surface of the contamination target wafer 1, the front and back surfaces of the contamination target wafer 1 are respectively dummy wafers. 21. Thereafter, as shown in FIG. 1B, the contamination target wafer 1 is heat-treated while being sandwiched between the dummy wafers 21 to diffuse the heavy metal impurities 3 into the contamination target wafer 1.

  Prior art related to the method of FIG. 1 includes the above-mentioned Patent Document 1, but the method of Patent Document 1 is intended for use of a hot plate and is a large electric furnace capable of heat-treating a normal silicon wafer. Is outside the expected range. In addition, even when the method of this document is applied to an electric furnace, if there is sufficient diffusion time so that either the target element of intentional contamination or the non-targeted contamination element received from the furnace penetrates the dummy wafer, It is not possible to prevent both furnace contamination and furnace contamination. In FIG. 1B, a state in which contaminating atoms 4 (illustrated by black circles, hereinafter referred to as exogenous contaminating atoms) from the outside (electric furnace) penetrate through the dummy wafer 21 and enter the contamination target wafer 1 is illustrated. Show. Further, FIG. 1B shows a state in which a part of the heavy metal impurity 3 which is an intentional contamination target element has diffused to the dummy wafer 21 side. That is, quantitative intentional contamination of the contamination target wafer 1 by the heavy metal impurity 3 is inhibited.

  Therefore, a method of forming an oxide film on the dummy wafer and sandwiching both surfaces of the contamination target wafer between the dummy wafers as in FIG. 1 can be considered. An embodiment of heat treatment by this method is shown in FIG. That is, in this method, as shown in FIG. 2A, an oxide film 22 is formed on both surfaces of a silicon wafer 21, and a dummy wafer 24 (dummy wafer with oxide film) composed of the silicon wafer 21 and the oxide film 22 is formed. ) To sandwich the wafer 1 to be contaminated. When heat treatment is performed in this state, the movement of the heavy metal impurities 3 and the extrinsic contaminant atoms 4 can be suppressed by the oxide film 22, as shown in FIG. Therefore, compared with the method of FIG. 1, the contamination of the furnace by heavy metal impurities 3 (contamination from the contamination target wafer 1 to the furnace) and the contamination of the contamination target wafer 1 by the extrinsic contamination atoms 4 (from the furnace to the contamination target wafer 1). Contamination).

  However, the method of FIG. 2 is also insufficient as a method that does not lower the cleanliness of the furnace while performing quantitative deliberate contamination. This is because in the case of assuming contamination from the furnace, an element having a diffusion coefficient high enough to penetrate through the oxide film 22, such as Cu, is so thick that it cannot be practically used to suppress the movement of Cu. Is required. Further, from the viewpoint of carrying out quantitative deliberate contamination, the heavy metal impurities 3 on the contamination target wafer 1 adhere and diffuse also on the oxide film 22 side of the dummy wafer 24 that is in contact, and the amount cannot be ignored. Therefore, it is clear that the target contamination concentration will be diluted.

  From the above, as long as the dummy wafer is in contact with the wafer to be contaminated, it cannot be a method that satisfies both the quantitative intentional contamination and the furnace contamination prevention.

  Through the above consideration, the present invention has been conceived. Specifically, when a wafer to be contaminated is sandwiched between dummy wafers, a method of performing a heat treatment by forming a slight gap between the dummy wafer and the wafer to be contaminated. I came up with an idea. FIG. 3 shows an embodiment of the heat treatment according to the present invention. FIG. 3A shows a state in which the contamination target wafer 1 is being sandwiched between the dummy wafers 24, and FIG. The state which is heat-processing the wafer 1 to be contaminated pinched | interposed is shown.

  As shown in FIG. 3A, in the present invention, the silicon wafer 1 having the surface 11 coated with the heavy metal impurity 3 is used as a contamination target wafer, and the front surface 11 and the back surface 12 of the contamination target wafer 1 are respectively dummy wafers 24. Insert with. At this time, a spacer 5 (small piece) is provided between the contamination target wafer 1 and the dummy wafer 24, and a gap 6 is formed between the contamination target wafer 1 and the dummy wafer 24. That is, the contamination target wafer 1 and the dummy wafer 24 are not brought into direct contact. The dummy wafer 24 is a wafer in which the oxide film 22 is formed on both surfaces of the silicon wafer 21. In addition, you may employ | adopt the dummy wafer in which the oxide film was formed only in the single side | surface of a silicon wafer. The size of the dummy wafer 24 is the same size as the contamination target wafer 1 or slightly larger than the contamination target wafer 1.

Any spacer 5 can be used according to its purpose such as size and material, but for the purpose of quantitative contamination by using it for heat treatment, it can easily be contaminated as well as heat resistance at the temperature during heat treatment. A member that contaminates the wafer 1 is not appropriate. Accordingly, silicon wafer fragments are suitable for the spacer 5. Thereby, it is possible to prevent the spacer 5 from being deformed during the heat treatment and to prevent the contamination from the spacer 5 to the contamination target wafer 1. Further, from the viewpoint of suppressing contamination from the dummy wafer 24 to the contamination target wafer 1 and contamination from the contamination target wafer 1 to the dummy wafer 24 via the spacer 5, the size of the spacer 5 (area of the spacer 5 in plan view). Is preferably smaller. The size of the spacer 5 is, for example, about several mm ² to several tens mm ² .

  Further, if the contamination target wafer 1 and the dummy wafer 24 are not in direct contact, it is preferable that the thickness of the spacer 5 (gap 6) is small. However, since the small piece made from the silicon wafer is used as the spacer 5, there is a limit to reducing the thickness of the spacer 5. In view of this, the thickness of the spacer 5 is preferably 500 μm or more. The value of 500 μm is a value (thickness equivalent to one silicon wafer) set based on the thickness of the spacer 5 (the thickness of a 6-inch silicon wafer 675 μm) used in the following examples. By setting the thickness of the spacer 5 to 500 μm or more, a spacer having a desired thickness can be easily made from a silicon wafer. That is, the thickness of the spacer 5 can be easily adjusted. On the other hand, if the thickness of the spacer 5 (gap 6) is too large, the effect of providing the dummy wafer 24 is diminished, and extrinsic contamination directly from the atmospheric gas in the electric furnace (without the dummy wafer 24). The atoms 4 are mixed into the contamination target wafer 1. Further, heavy metal impurities 3 applied to the surface 11 are diffused into the electric furnace. Therefore, the thickness of the spacer 5 is preferably within 10 mm. In addition, the value of 10 mm is a value set on the assumption of the thickness of the sample for lifetime measurement cut out from the ingot.

  The number of spacers 5 may be any number, but from the viewpoint of suppressing the introduction of impurities (heavy metal impurities 3 and extrinsic contaminant atoms 4) and transfer through the spacers 5, the number of spacers 5 is preferably small. However, if the number of the spacers 5 is too small, the dummy wafer 24 becomes unstable. Therefore, the number of spacers 5 is preferably 3 on one side (6 on both sides). FIG. 4 shows a plan view of the contamination target wafer 1 in a state where the spacer 5 is installed. In FIG. 4, the surface 11 side of the contamination target wafer 1 is shown. As shown in FIG. 4, the three spacers 5 are disposed at a position where the vicinity of the outer periphery of the contamination target wafer 1 is divided into three equal parts in the circumferential direction (the position may not be strictly divided into three equal parts). Contact between the target wafer 1 and the dummy wafer 24 (contact through the spacer 5) can be minimized, and the dummy wafer 24 can be stabilized.

  According to the present invention, the contamination target wafer 1 and the dummy wafer 24 are only in contact with each other through the spacer 5, and the contact with the atmospheric gas can be adjusted by the thickness of the spacer 5, so that the contamination from the atmospheric gas, that is, the furnace Heat treatment can be carried out with almost no contamination from. That is, as shown in FIG. 3B, most of the extrinsic contaminating atoms 4 are blocked by the dummy wafer 24 with the oxide film 22, and mixing of the exogenous polluting atoms 4 into the contamination target wafer 1 can be suppressed. Further, the heavy metal impurities 3 applied to the surface 11 do not contaminate the furnace tube via the furnace atmosphere. Therefore, it is possible to perform a heat treatment that satisfies both the desired quantitative intentional contamination and the contamination prevention for the furnace.

  Next, the steps of the heat treatment method of the present invention will be described. FIG. 5 is a flowchart showing the steps of the heat treatment method of the present invention. 5 will be described with reference to FIG. 4. First, a silicon wafer 1 (contamination target wafer) to be contaminated is prepared (S11). Specifically, a gettering capability (internal gettering or external gettering) is provided, and a silicon wafer for evaluating the gettering capability is prepared as the contamination target wafer 1.

  Next, heavy metal impurities 3 such as Fe, Cu, and Ni are applied to the surface 11 of the contamination target wafer 1 prepared in S11 (S12). Next, two dummy wafers 24 having oxide films 22 formed on both sides or one side of the silicon wafer 21 are prepared (S13). Further, a necessary number of small pieces 5 (spacers) made from a silicon wafer are prepared (S13). For example, when three spacers 5 on one side are used, a total of six spacers are prepared.

  Next, the contamination target wafer 1, the spacer 5, and the dummy wafer 24 are set as shown in FIG. 3 (S14). That is, the front and back surfaces of the contamination target wafer 1 are sandwiched between the two dummy wafers 24. At this time, the spacer 5 is provided between the contamination target wafer 1 and the dummy wafer 24. The spacer 5 is not attached to the contamination target wafer 1 or the dummy wafer 24 with an adhesive or the like, and nothing is attached to the contact surface between the contamination target wafer 1 or the dummy wafer 24 and the spacer 5. This prevents impurities contained in the adhesive or the like from entering the contamination target wafer 1.

  Next, the contamination target wafer 1, the spacer 5, and the dummy wafer 24 are put into an electric furnace in the setting state of S14, and the contamination target wafer 1 is heat-treated in the electric furnace (S15). The setting of S14 may be performed in an electric furnace. Thereby, as shown in FIG. 3B, the heavy metal impurities 3 applied to the surface 11 are diffused into the contamination target wafer 1.

  Through the above steps, the intentionally contaminated wafer 10 (see FIG. 3B) intentionally contaminated with the heavy metal impurities 3 can be obtained. Thereafter, the gettering ability of the intentionally contaminated wafer 10 (original contamination target wafer 1) is evaluated based on the heavy metal impurity 3 in the intentionally contaminated wafer 10.

  As described above, according to the present embodiment, it is possible to suppress both diffusion of heavy metal impurities applied to the surface of the contamination target wafer to the furnace and contamination from the furnace to the contamination target wafer. Intentional contamination can be carried out in the same furnace.

In order to confirm the effect of the present invention, the following experiment was conducted.
(Comparative Example 1)
By a CZ method, a Si crystal rod having a diameter of 6 inches, an initial oxygen concentration of 14 ppma (JEIDA), and an orientation <100> was pulled at a normal pulling rate (1.2 mm / min). This crystal rod was processed into a substrate wafer (contamination target wafer) having a thickness of 675 μm, and was directly subjected to heat treatment at 1000 ° C. for 1 hour in an electric furnace that was confirmed to be contaminated with Fe. Thereafter, when the Fe concentration on the surface of the substrate wafer was measured by a total reflection fluorescent X-ray method, 5.4 × 10 ¹¹ cm ⁻² Fe was detected. This indicates that a large amount of Fe was contaminated from the furnace by heat treatment in the furnace contaminated with Fe. Note that “JEIDA” is an abbreviation for “Jaonese Electronic Industry Development Association” and indicates that the oxygen concentration was measured based on a calibration curve defined by JEIDA.

(Comparative Example 2)
By a CZ method, a Si crystal rod having a diameter of 6 inches, an initial oxygen concentration of 14 ppma (JEIDA), and an orientation <100> was pulled at a normal pulling rate (1.2 mm / min). By processing this crystal rod, one substrate was used as a substrate wafer (contamination target wafer), and two wafers were formed on both sides with 200 nm oxide films as dummy wafers. . The thickness of the substrate wafer and the dummy wafer is 675 μm. The three wafers were directly stacked and heat-treated at 1000 ° C. for 1 hour in an electric furnace that was confirmed to be contaminated with Fe. Thereafter, when the Fe concentration on the surface of the substrate wafer was measured by a total reflection fluorescent X-ray method, 7.0 × 10 ¹⁰ cm ⁻² Fe was detected. This shows that although the substrate wafer is not completely exposed to the furnace as in Comparative Example 1, the contamination concentration is lower than that in Comparative Example 1, but it still receives Fe contamination. This is because the dummy wafer was first contaminated, Fe atoms passed through and diffused through the dummy wafer, and it was thought that the substrate in direct contact was eventually contaminated with Fe, which completely prevented contamination from the furnace. I can't say that.

Example 1
By a CZ method, a Si crystal rod having a diameter of 6 inches, an initial oxygen concentration of 14 ppma (JEIDA), and an orientation <100> was pulled at a normal pulling rate (1.2 mm / min). By processing this crystal rod, one substrate was used as a substrate wafer (contamination target wafer), and two wafers were formed on both sides with 200 nm oxide films as dummy wafers. . The thickness of the substrate wafer and the dummy wafer is 675 μm. When the three wafers were stacked, three pieces of a 4 × 4 mm ² silicon wafer having a thickness of 675 μm were placed between the substrate wafer and the dummy wafer at a location close to the outer periphery of the wafer, and this was used as a spacer. Naturally, since a spacer is necessary between two dummy wafers arranged on both sides of the substrate wafer, a total of six spacers are used. Thus, using the spacer, the three wafers stacked so that the dummy wafer and the substrate wafer are not in direct contact with each other in an electric furnace that has been confirmed to be contaminated with Fe at 1000 ° C. for 1 hour. Heat treatment was applied. Since this experiment is an experiment for confirming Fe contamination from the contamination furnace, no intentional contamination element is applied to the surface of the substrate wafer.

Thereafter, when the Fe concentration on the surface of the substrate wafer was measured by a total reflection fluorescent X-ray method, 1.7 × 10 ¹⁰ cm ⁻² Fe was detected. This is because the dummy wafer and the substrate wafer are not completely in contact with each other as in Comparative Example 2, so that the contamination received from the furnace by the dummy wafer was not transmitted to the substrate wafer. This shows that even though the gap was in contact with the furnace atmosphere, it was not contaminated by that atmosphere. From this, it has been found that the present invention is a heat treatment method that satisfies both the purposeful quantitative intentional contamination and the prevention of contamination to the furnace.

(Example 2)
By a CZ method, a Si crystal rod having a diameter of 6 inches, an initial oxygen concentration of 14 ppma (JEIDA), and an orientation <100> was pulled at a normal pulling rate (1.2 mm / min). This crystal rod was processed so that one was a substrate wafer (contamination target wafer), and a dummy wafer was formed by forming 200 nm oxide films on both surfaces of another two wafers. Of these three wafers, 1 × 10 ¹³ cm ⁻² of Fe was applied to the surface of the substrate wafer, and the wafers were stacked so as to be sandwiched between two dummy wafers. At this time, three pieces of a 4 × 4 mm ² silicon wafer having a thickness of 675 μm were placed in the gap between the substrate wafer and the dummy wafer at a location close to the outer periphery of the wafer, and this was used as a spacer. Naturally, since a spacer is necessary between two dummy wafers arranged on both sides of the substrate wafer, a total of six spacers are used. Thus, using the spacer, the three wafers stacked so that the dummy wafer and the substrate wafer are not in direct contact with each other in an electric furnace that has been confirmed to be contaminated with Fe at 1000 ° C. for 1 hour. Heat treatment (hereinafter referred to as heat treatment 1) was performed.

Following this heat treatment 1, this time, a clean wafer whose surface is not contaminated with Fe is put into the furnace alone, heat treated at 1000 ° C. for 1 hour, and then the surface of the substrate wafer by total reflection fluorescent X-ray method. As a result, the Fe concentration of 5.4 × 10 ¹¹ cm ⁻² was detected. As shown in Comparative Example 1, this indicates that there was no change in the contamination concentration before the contaminated wafer was charged, and the furnace was not contaminated by the heat treatment 1 using the above-described dummy wafer.

On the other hand, when the contaminated wafer was put into the furnace without using this method of sandwiching with a dummy wafer as in Comparative Example 1, and then the clean wafer was heat treated and the subsequent surface Fe concentration was measured. , About 1.0 × 10 ¹² cm ⁻² was detected, and the contamination concentration was higher than before the contaminated wafer was introduced (5.4 × 10 ¹¹ cm ⁻² ). Without it, it was shown that the furnace was reliably contaminated with Fe.

  The present invention is not limited to the above embodiment. The above embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

DESCRIPTION OF SYMBOLS 1 Contamination target wafer 24 Dummy wafer 22 Oxide film 3 Heavy metal impurity 4 Exogenous contamination atom 5 Spacer 6 Crevice 10 Intentionally contaminated wafer

Claims (4)

A method of performing a heat treatment for diffusing the intentionally contaminating element attached to the silicon wafer surface into the contamination target wafer, which is the silicon wafer,
An intentionally contaminated wafer heat treatment method, wherein the heat treatment is performed after the front and back surfaces of the contamination target wafer are sandwiched between dummy wafers, which are different silicon wafers, with a gap formed therebetween.   2. The method for heat treating a intentionally contaminated wafer according to claim 1, wherein an oxide film is formed on one side or both sides of the dummy wafer.   3. The intentionally contaminated wafer heat treatment method according to claim 1, wherein the gap is formed by sandwiching a small piece made of a silicon wafer between the contamination target wafer and the dummy wafer. The method for heat treatment of intentionally contaminated wafers according to any one of claims 1 to 3, wherein the gap is 500 µm or more.

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