JP5874471B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  Embodiments described below relate to a semiconductor device and a manufacturing method thereof.

  A dynamic threshold MOS transistor (hereinafter referred to as a Dt-MOS transistor) has a gate electrode short-circuited to a semiconductor layer or a well region in which a channel region is formed, and an input signal is a semiconductor layer in which the gate electrode and the channel region are formed. In addition, by simultaneously applying to the well region, a low off-state current and a large on-state current can be realized with a low threshold, and the MOS transistor is suitable for low power consumption operation with a low power supply voltage. A semiconductor layer or well region in which a channel region is formed may be referred to as a body.

  FIG. 1 is a diagram for explaining the principle of a general Dt-MOS transistor, and FIG. 2 is a graph showing operating characteristics of the Dt-MOS transistor 10 of FIG.

  Referring to FIG. 1, in this example, a Dt-MOS transistor 10 is an n-channel MOS transistor on a silicon substrate 11 on which a p-type well 11P including an n-type doped source region 11S and a drain region 11D is formed. On the silicon substrate 11, a gate electrode 13 made of, for example, n-type polysilicon is formed on a channel region 11C between the source region 11S and the drain region 11D via a gate insulating film 12. Is formed.

  In the Dt-MOS transistor 10 of FIG. 1, the gate electrode 13 is further electrically connected to the p-type well 11P, that is, the body, and the signal voltage applied to the gate electrode 13 is also applied to the body 11P. Is done. As a result, the signal voltage acts to lower the threshold voltage of the Dt-MOS transistor 10, and the operating characteristic of the Dt-MOS transistor 10 is that of the MOS transistor having a low threshold voltage as the signal voltage increases. Asymptotically. For this reason, the Dt-MOS transistor 10 is switched on with a low signal voltage.

  On the other hand, when the signal voltage is 0V or a low voltage in the vicinity thereof, the potential of the body 11P is 0V or in the vicinity thereof, and the operating characteristic of the Dt-MOS transistor 10 is that of a MOS transistor having a high threshold voltage. Asymptotically. That is, the threshold voltage of the Dt-MOS transistor 10 is the same as that of a normal n-channel MOS transistor having a high threshold voltage. As a result, the Dt-MOS transistor 10 has a low off-current or leakage as shown in FIG. The switch-off operation characterized by current is shown.

  The above description holds true for the p-channel MOS transistor in which the p-type and n-type are inverted.

JP 2002-134627 A

Sharp Technical Report No. 79, April 2001

  Conventionally, in such a Dt-MOS, since the source region and the drain region are in contact with the body, there arises a problem that the parasitic capacitance of the body increases. Therefore, in Patent Document 1, an increase in parasitic capacitance of the body is suppressed by providing a shallow trench type element isolation region under the gate electrode.

  However, since the body current path is narrowed by the shallow trench isolation region, the resistance of the body increases. In addition, if the shallow trench isolation region is made shallower in order to reduce the body resistance, the portion where the source region / drain region and the body come into contact increases, and the effect of reducing the parasitic capacitance of the body is reduced. End up.

  According to one aspect, a semiconductor device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate, an element region defined by the element isolation region in the semiconductor substrate, and the semiconductor substrate, An insulating film region that is formed continuously with the element isolation region and divides the element region into an active region and a tap region, and is formed continuously with the element isolation region in the insulating film region, and the lower end of the element isolation region Than the first insulating film region portion having a lower end at a shallow position from the surface of the semiconductor substrate, and the insulating film region is formed continuously with the element isolation region, the lower than the lower end of the element isolation region, the A second insulating film region portion having a lower end at a shallow position from the surface of the semiconductor substrate; and the insulating film region between the first insulating film region portion and the second insulating film region portion. A third insulating film region portion formed and having a lower end at a position shallower from the surface of the semiconductor substrate than the lower end of the first insulating film region portion and the lower end of the second insulating film region portion; And a gate electrode formed on the insulating film region and electrically connected to the tap region, and first and second gate electrodes formed on the first and second gate side walls facing the gate electrode, respectively. A sidewall insulating film, a body formed on the semiconductor substrate, continuously extending from the active region along the gate electrode to the tap region under the insulating film region, and having a first conductivity type, and in the active region And a diffusion region formed with the gate electrode interposed therebetween and having a second conductivity type opposite to the first conductivity type.

  According to another aspect, a method of manufacturing a semiconductor device includes a step of introducing a first impurity element having a first conductivity type into a semiconductor substrate to a first depth, and forming an element isolation region on the semiconductor substrate. Forming an element region surrounded by the element isolation region, and removing a part of the semiconductor substrate in the element region to form an insulating film region opening in contact with the element isolation region And forming an insulating film region by forming a first insulating film in the opening of the insulating film region, the active region surrounded by the element isolation region and the insulating film region, and the element isolation A step of being divided into a tap region which is surrounded by the region and the insulating film region and is continuous with the active region under the insulating film region, and extends from the active region to the insulating film region on the semiconductor substrate Gate electrode Forming the first and second sidewall insulating films on the opposite side wall surfaces of the gate electrode, the gate electrode and the first and second layers, respectively. Using the sidewall insulating film as a mask, a part of the first insulating film in the insulating film region is removed until the semiconductor substrate under the insulating film region is exposed. Forming the first and second recesses, and exposing the semiconductor substrate exposed at least in the first and second recesses using the gate electrode and the first and second sidewall insulating films as a mask. A step of removing, a step of forming a second insulating film in the first and second recesses, and a second impurity element of a second conductivity type different from the first conductivity type in the active region. And introduce a diffusion region with the gate electrode in between. And a step of forming, a step of electrically connecting the gate electrode to the tap region.

  According to the embodiment, as a result of ensuring a sufficient thickness in the body of the Dt-MOS transistor, the resistance value is reduced and the operation speed of the Dt-MOS transistor is improved. Further, a short circuit between the body and the source / drain regions is avoided, and the yield of the semiconductor device can be improved.

It is a figure explaining the basic composition of a Dt-MOS transistor. It is a figure which shows the typical operating characteristic of a Dt-MOS transistor. 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. FIG. 3B is a cross-sectional view taken along line BB ′ in FIG. 3A. It is sectional drawing along line CC 'in FIG. 3A. FIG. 3B is a cross-sectional view taken along line DD ′ in FIG. 3A. It is sectional drawing along line EE 'in FIG. 3A. It is sectional drawing along line FF 'in FIG. 3A. It is a top view which shows the state which removed the structure of the silicon substrate in the top view of FIG. 3A. FIG. 3B is a plan view showing a state where a part of the insulating film is further removed in the plan view of FIG. FIG. 6 is a diagram (part 1) for explaining the method of manufacturing a semiconductor device according to the first embodiment; FIG. 8 is a diagram (part 2) for explaining the method of manufacturing a semiconductor device according to the first embodiment; FIG. 6 is a view (No. 3) for explaining the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a view (No. 4) for describing the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a view (No. 5) for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a view (No. 6) for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 7 is a view (No. 7) for explaining the method for manufacturing the semiconductor device according to the first embodiment; FIG. 8 is a view (No. 8) for explaining the method for manufacturing the semiconductor device according to the first embodiment; FIG. 9 is a diagram (No. 9) for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 10 is a diagram (No. 10) for explaining the method of manufacturing the semiconductor device according to the first embodiment; FIG. 11 is a view (No. 11) for explaining the method for manufacturing the semiconductor device according to the first embodiment; It is FIG. (12) explaining the manufacturing method of the semiconductor device by 1st Embodiment. It is FIG. (13) explaining the manufacturing method of the semiconductor device by 1st Embodiment. It is FIG. (14) explaining the manufacturing method of the semiconductor device by 1st Embodiment. FIG. 18 is a view (No. 15) for explaining the method of manufacturing the semiconductor device according to the first embodiment; It is a top view which shows the silicon substrate in the middle of a manufacturing process. It is sectional drawing along line BB 'in FIG. 5A. It is sectional drawing along line CC 'in FIG. 5A. It is a top view which shows the silicon substrate in the middle of a manufacturing process. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 1st Embodiment. FIG. 7B is a cross-sectional view taken along line BB ′ in FIG. 7A. It is sectional drawing along line CC 'in FIG. 7A. FIG. 7B is a cross-sectional view taken along line DD ′ in FIG. 7A. FIG. 7B is a cross-sectional view taken along line EE ′ in FIG. 7A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 1st Embodiment. It is sectional drawing along line BB 'in FIG. 8A. It is sectional drawing along line CC 'in FIG. 8A. It is sectional drawing along line DD 'in FIG. 8A. It is sectional drawing along line EE 'in FIG. 8A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 1st Embodiment. FIG. 9B is a cross-sectional view taken along line BB ′ in FIG. 9A. FIG. 9B is a cross-sectional view taken along line CC ′ in FIG. 9A. FIG. 9B is a cross-sectional view taken along line DD ′ in FIG. 9A. FIG. 9B is a cross-sectional view taken along line EE ′ in FIG. 9A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 1st Embodiment. FIG. 10B is a cross-sectional view taken along line BB ′ in FIG. 10A. FIG. 10B is a cross-sectional view taken along line CC ′ in FIG. 10A. FIG. 10B is a cross-sectional view taken along line DD ′ in FIG. 10A. FIG. 10B is a cross-sectional view taken along line EE ′ in FIG. 10A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 1st Embodiment. FIG. 11B is a cross-sectional view taken along line BB ′ in FIG. 11A. FIG. 11B is a cross-sectional view taken along line CC ′ in FIG. 11A. FIG. 11B is a cross-sectional view taken along line DD ′ in FIG. 11A. FIG. 11B is a cross-sectional view taken along line EE ′ in FIG. 11A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 1st Embodiment. It is sectional drawing along line BB 'in FIG. 12A. It is sectional drawing along line CC 'in FIG. 12A. FIG. 12B is a sectional view taken along line DD ′ in FIG. 12A. It is sectional drawing along line EE 'in FIG. 12A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 1st Embodiment. It is sectional drawing along line BB 'in FIG. 12A. It is sectional drawing along line CC 'in FIG. 12A. FIG. 12B is a sectional view taken along line DD ′ in FIG. 12A. It is sectional drawing along line EE 'in FIG. 12A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 1st Embodiment. FIG. 14B is a cross-sectional view taken along line BB ′ in FIG. 14A. FIG. 14B is a cross-sectional view taken along line CC ′ in FIG. 14A. FIG. 14B is a cross-sectional view taken along line DD ′ in FIG. 14A. FIG. 14B is a cross-sectional view taken along line EE ′ in FIG. 14A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 1st Embodiment. FIG. 15B is a cross-sectional view taken along line BB ′ in FIG. 15A. FIG. 15B is a cross-sectional view taken along line CC ′ in FIG. 15A. FIG. 15B is a cross-sectional view taken along line DD ′ in FIG. 15A. It is sectional drawing along line EE 'in FIG. 15A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 1st Embodiment. It is sectional drawing along line BB 'in FIG. 16A. It is sectional drawing along line CC 'in FIG. 16A. FIG. 16B is a cross-sectional view taken along line DD ′ in FIG. 16A. FIG. 16B is a cross-sectional view taken along line EE ′ in FIG. 16A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 1st Embodiment. FIG. 17B is a cross-sectional view taken along line BB ′ in FIG. 17A. It is sectional drawing along line CC 'in FIG. 17A. FIG. 17B is a cross-sectional view taken along line DD ′ in FIG. 17A. FIG. 17B is a cross-sectional view taken along line EE ′ in FIG. 17A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 1st Embodiment. FIG. 18B is a cross-sectional view taken along line BB ′ in FIG. 18A. FIG. 18B is a cross-sectional view taken along line CC ′ in FIG. 18A. It is sectional drawing along line DD 'in FIG. 18A. It is sectional drawing along line EE 'in FIG. 18A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 1st Embodiment. FIG. 19B is a cross-sectional view taken along line BB ′ in FIG. 19A. FIG. 19B is a cross-sectional view taken along line CC ′ in FIG. 19A. FIG. 19B is a cross-sectional view taken along line DD ′ in FIG. 19A. FIG. 19B is a cross-sectional view taken along line EE ′ in FIG. 19A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 1st Embodiment. It is sectional drawing along line BB 'in FIG. 20A. It is sectional drawing along line CC 'in FIG. 20A. FIG. 20B is a cross-sectional view taken along line DD ′ in FIG. 20A. FIG. 20B is a cross-sectional view taken along line EE ′ in FIG. 20A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 1st Embodiment. FIG. 21B is a cross-sectional view taken along line BB ′ in FIG. 21A. It is sectional drawing along line CC 'in FIG. 21A. FIG. 21B is a cross-sectional view taken along line DD ′ in FIG. 21A. FIG. 21B is a cross-sectional view taken along line EE ′ in FIG. 21A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 1st Embodiment. It is sectional drawing along line BB 'in FIG. 22A. It is sectional drawing along line CC 'in FIG. 22A. It is sectional drawing along line DD 'in FIG. 22A. It is sectional drawing along line EE 'in FIG. 22A. It is a top view which shows the structure of the semiconductor device by the modification of 1st Embodiment. It is sectional drawing along line BB 'in FIG. 23A. It is sectional drawing along line CC 'in FIG. 23A. FIG. 23B is a cross-sectional view taken along line DD ′ in FIG. 23A. FIG. 23B is a cross-sectional view taken along line EE ′ in FIG. 23A. It is a top view which shows the structure of the semiconductor device by the other modification of 1st Embodiment. FIG. 24B is a cross-sectional view taken along line BB ′ in FIG. 24A. It is sectional drawing along line CC 'in FIG. 24A. It is sectional drawing along line DD 'in FIG. 24A. It is sectional drawing along line EE 'in FIG. 24A. It is sectional drawing along line FF 'in FIG. 24A. It is a top view which shows the structure of the semiconductor device by the other modification of 1st Embodiment. FIG. 25B is a cross-sectional view taken along line BB ′ in FIG. 25A. It is a top view which shows the structure of the semiconductor device by 2nd Embodiment. FIG. 26B is a cross-sectional view taken along line BB ′ in FIG. 26A. FIG. 26B is a cross-sectional view taken along line CC ′ in FIG. 26A. FIG. 26B is a cross-sectional view taken along line DD ′ in FIG. 26A. FIG. 26B is a cross-sectional view taken along line EE ′ in FIG. 26A. It is a top view which shows the structure of the semiconductor device by 3rd Embodiment. FIG. 27B is a cross-sectional view taken along line BB ′ in FIG. 27A. FIG. 27B is a cross-sectional view taken along line CC ′ in FIG. 27A. FIG. 27B is a cross-sectional view taken along line DD ′ in FIG. 27A. FIG. 27B is a cross-sectional view taken along line EE ′ in FIG. 27A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 3rd Embodiment. FIG. 28B is a cross-sectional view taken along line BB ′ in FIG. 28A. FIG. 28B is a cross-sectional view taken along line CC ′ in FIG. 28A. FIG. 28B is a cross-sectional view taken along line DD ′ in FIG. 28A. FIG. 28B is a cross-sectional view taken along line EE ′ in FIG. 28A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 3rd Embodiment. FIG. 29B is a cross-sectional view taken along line BB ′ in FIG. 29A. It is sectional drawing along line CC 'in FIG. 29A. It is sectional drawing along line DD 'in FIG. 29A. It is sectional drawing along line EE 'in FIG. 29A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 3rd Embodiment. FIG. 30B is a cross-sectional view taken along line BB ′ in FIG. 30A. It is sectional drawing along line CC 'in FIG. 30A. FIG. 30B is a cross-sectional view taken along line DD ′ in FIG. 30A. FIG. 30B is a cross-sectional view taken along line EE ′ in FIG. 30A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 3rd Embodiment. FIG. 31B is a cross-sectional view taken along line BB ′ in FIG. 31A. FIG. 31B is a cross-sectional view taken along line CC ′ in FIG. 31A. FIG. 31B is a cross-sectional view taken along line DD ′ in FIG. 31A. FIG. 31B is a cross-sectional view taken along line EE ′ in FIG. 31A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 3rd Embodiment. It is sectional drawing along line BB 'in FIG. 32A. It is sectional drawing along line CC 'in FIG. 32A. FIG. 32B is a cross-sectional view taken along line DD ′ in FIG. 32A. It is sectional drawing along line EE 'in FIG. 32A. It is a top view for demonstrating one process of the manufacturing method of the semiconductor device by 3rd Embodiment. FIG. 33B is a cross-sectional view taken along line BB ′ in FIG. 33A. FIG. 33B is a cross-sectional view taken along line CC ′ in FIG. 33A. FIG. 33B is a cross-sectional view taken along line DD ′ in FIG. 33A. It is sectional drawing along line EE 'in FIG. 33A.

(First embodiment)
3A is a plan view showing the configuration of the semiconductor device 20 according to the first embodiment, and FIGS. 3B to 3F are lines BB ′, CC ′, DD ′, and E in FIG. 3A, respectively. It is sectional drawing along -E 'and FF'.

Referring to FIGS. 3A to 3F, the semiconductor device 20 includes Dt-MOS transistors Tr _A and Tr _{B. The} Dt-MOS transistors Tr _A and Tr _B are formed with an n-type well 21NW, and the n-type well In the p-type silicon substrate 21 in which the p-type well 21PW is formed on the well 21NW, as shown by a thick line in FIGS. 3G and 3H, in the element region 210 surrounded by the STI-type element isolation region 21I. Is formed. As will be described in detail later, FIG. 3G is a plan view showing a state in which the gate electrode, the gate insulating film, and the sidewalls on the silicon substrate 21 and the surface of the silicon substrate 21 are removed in the plan view of FIG. is there. FIG. 3H is a plan view showing a state in which the p-type well 21PW is exposed by removing a part of the insulating film and a part of the substrate in the plan view of FIG. 3G.

The device region 210 in the present embodiment, wherein the surface of the silicon substrate 21 is formed continuously from the element isolation region 21I, the insulating film region portion (21IT _A) indicated by a broken line in FIG. 3G _A ~ (21IT _A ) insulating film region 21IT _a and the insulating film region portion comprising a _C (21IT _B) by the insulating film region 21IT _B containing _a ~ (21IT _{B) C,} the active region 21A and the first and second tap region _21T a. It is divided into a 21T _B.

Plan view of FIG. 3A and the reference to the sectional view of FIG. 3B, the polysilicon gate electrode 23G _A of on the silicon substrate 21 is first Dt-MOS transistor Tr _A from the active region 21A to the tap region 21T _A polysilicon but the insulating film region 21IT _a of the insulating film region portion (21IT _a) exceeds the _a extends, Similarly the active from the area 21A to the tap region 21T _B second Dt-MOS transistor Tr _B the gate electrode 23G _B extends beyond the insulating layer region portion (21IT _{B) a} of the insulating film region 21IT _B. In the illustrated example the polysilicon gate electrode _23G A, but 23G _B are parallel to the drawing, this embodiment is intended to cover the case where the gate electrode _23G A, is 23G _B not parallel. The polysilicon gate electrode 23G _A carries a silicide layer _{23G As,} also the polysilicon gate electrode 23G _B carries a silicide layer _{23G Bs.}

Also the polysilicon gate electrode 23G _A, the has a sidewall insulating film 24a made of silicon nitride film from the polysilicon gate electrode 23G _B farther side wall surface, also on the side wall surface of the mold close to the gate electrode 23b Similarly, a side wall insulating film 24b made of a silicon nitride film is provided. However the sidewall insulation films 24a, 24b is continuous at both ends of the polysilicon gate electrode 23G _A. Similarly the gate electrode 23G _B, the has a sidewall insulating film 24c made of silicon nitride film on the gate electrode 23G _A near side of the side wall surface, also likewise silicon on the side wall surface of the furthest mold from the gate electrode 23a A sidewall insulating film 24d made of a nitride film is provided. However the sidewall insulation film 24c, 24d is continuous at both ends of the gate electrode 23G _B.

The polysilicon gate electrode 23G _A As can be seen from the cross-sectional view of FIG. 3B are in the active region 21A is formed through a gate insulating film 22 _A on the silicon substrate 21, also of the insulating film region 21IT _A in the insulating film region portion over (21IT _{a) a} and the tap region 21T _a, it is formed through a similar insulating film _{22 Ai} which is continuous from the gate insulating film 22 _a. Although not shown, is the same polysilicon gate electrode 23G _B.

The tap region 21T _A insulating film region portion constituting the device isolation region 21I and the insulating film region 21IT _A as shown in the sectional view of FIG. 3B and 3F plan view and in FIG. 3A and FIG. 3G (21IT _{A) A} ~ (21IT _A ) _{C is} defined, and an n + -type contact region 21T _A P or 21T _B P is formed on the surface to reduce contact resistance, and is covered with the silicide layer 21T _As . Also the polysilicon gate electrode 23G _A in the tap region 21T _A, the shared contact plug _23T A Sc, via the silicide layer _{23G As} on the silicide layer _{21T As} and the gate electrode 23G _A, are electrically connected Yes. Further the tap region 21T _A As can be seen from Figure 3B is constituted by a part of the p-type well 21PW continuous with the active region through the bottom of the insulating film region portion (21IT _{A) A.} For this reason, such a transistor Tr _A exhibits a dynamic threshold operation as described above with reference to FIG.

Similarly the tap region 21T _B is also covered with a silicide layer _{21T Bs} as shown in the sectional view of FIG. 3B and 3F plan view and in FIGS. 3A and 3G, the polysilicon gate electrode 23G _B is the tap region the shared contact plug _23T B Sc to 21T _B, via the silicide layer _{23G Bs} on the silicide layer _{21T Bs} and the gate electrode 23G _B, are electrically connected. The illustration is omitted, also the tap region 21T _B is constituted by a part of the p-type well 21PW continuous with the active region 21A through the bottom of the insulating film region portion (21IT _{B) A.} For this reason, the transistor Tr _B also exhibits the dynamic threshold operation as described above with reference to FIG.

Still referring to plan views and FIGS. 3C and 3D of the sectional view of FIG. 3A, the in active region 21A in the silicon substrate 21, the gate electrode 23G _A transistor Tr _A in the left drawing the first of the n + type source region 21S _a is also on the right side in the drawing n + -type drain region 21D _a is formed, also in the drain region 21D _a is the second transistor Tr _B in the left side in the drawing of the gate electrode 23G _B n + It is formed also serves as a source region 21S _B. Further, the on the right side of the polysilicon gate electrode 23G _B, n + -type drain region 21D _B of the second transistor Tr _B are formed.

The plan view and the surface of the source region 21S _A As can be seen from the cross-sectional view of FIG. 3C of Figure 3A and the silicide layer _{21S As} is formed, the silicide layer _{21S As} is formed on the surface of the drain region 21D _A ing. Further, the on the surface of the source region 21S _B and silicide layer _{21S Bs} is formed on the surface of the drain region 21D _B is silicide layer _{21D Bs} is formed. Here, the silicide layer 21D _As and the silicide layer 21S _Bs continuously form a single silicide layer. The silicide layer _{21S As,} silicide layer _{21D As,} therefore silicide layer _{21S Bs,} and the silicide layer _21D on _Bs, contact plugs _{V A, V B, V C} are respectively formed.

For further reference to the cross-sectional view of FIG. 3C and 3D, the directly below the source region 21S _A transistor Tr _A is formed buried insulating region 21IS _A extending from the isolation region 21I is also the Immediately below the drain region 21D _A of the transistor Tr _A , an embedded insulating region 21ID _A that extends from the element isolation region 21I is formed. Also immediately below the source region 21S _B of the transistor Tr _B are buried insulating region 21IS _B extending from the isolation region 21I is formed. Here buried insulating region 21ID _A forms a single buried insulating region is continuous with the buried insulation region 21IS _B. Further, immediately below the drain region 21D _B of the transistor Tr _B , a buried insulating region 21ID _B extending similarly from the element isolation region 21I is formed.

By forming the buried insulating region immediately below the source region or the drain region in this way, the parasitic capacitance is reduced in each of the above-described source or drain regions in the Dt-MOS transistors Tr _A and Tr _B according to the present embodiment, The operation speed is improved.

For further reference to the cross-sectional view of FIG. 3D, between the buried insulating region 21IS _A and 21ID _A in the present embodiment, the portion of the silicon substrate 21, the gate insulating film 22 _A, the gate electrode 23G _A and sidewall insulating films 24a, mesa region 21M _a supporting and 24b are formed, the mesa region 21M during _a side wall insulating film 24a, n-type source extension region 21a and a drain extension region 21b directly below the 24b are formed, respectively You can see that. _A p-type channel region CH _A is formed between the source extension region 21a and the drain extension region 21b.

Between Similarly the buried insulating region 21IS _B and 21ID _B, the portion of the silicon substrate 21, the gate insulating film 22 _B, the gate electrode 23G _B and the sidewall insulating film 24c, the mesa region to support the 24d 21M _B is formed, during the mesa region 21M _B the sidewall insulation film 24c, n-type source extension region 21c and a drain extension region 21d immediately below the 24d are formed respectively. Also between the source extension region 21c and the drain extension region 21d is, p-type channel region CH _B is formed.

Therefore, according to the present embodiment, by applying an appropriate gate voltage to the polysilicon gate electrodes 23G _A and 23G _B , the conduction of the channel region CH _A or CH _B is controlled in the same manner as a normal MOS transistor. Is possible. However, in this embodiment, the polysilicon gate electrode 23G _A As also described above is connected to the tap region 21T _A, the tap region 21T _A passes below the insulating film region 21IT _A channel region Since it is conducting to CH _A , the transistor TrA exhibits the dynamic threshold operation as described in FIG. Similarly, in this embodiment, the As also described earlier polysilicon gate electrode 23G _B is connected to the tap region 21T _B, the tap region 21T _B passes below the insulating film region 21IT _B channel since the conducting to the region CH _B, the transistor TrA denotes a dynamic threshold operation as described in FIG.

The buried insulating region 21IS _A and 21ID _A silicon epitaxial layer p- type on 21ep _1, 21ep ₂ is formed by combining the respective sidewall surface of the mesa structure 21M _A is further the mesa structure 21M _A and, the n + type source region 21S _a in the silicon epitaxial layer 21Ep _1, also above n + -type drain region 21D _a in the silicon epitaxial layer 21Ep _2, are formed, respectively.

Formed in the same manner as the mesa structure 21M _B the buried insulating region 21IS _B and 21ID _B on the p- -type silicon epitaxial layer 21ep _3, 21ep ₄ is attached to each side wall surface of the mesa structure 21M _A are, the n + -type source region 21S _B is in the silicon epitaxial layer 21Ep _3, the drain region 21D _B of the n + type in the silicon epitaxial layer 21Ep _4, are formed. Wherein said the silicon epitaxial layer 21Ep ₂ and 21Ep ₃ to form a single silicon epitaxial layer continuous.

During the mesa structure _{M A,} deeper bottom than the upper end of the pn junction plane pn _A indicated by a broken line by the lower of the n-type well 21NW and an upper p-type well 21PW said buried insulating film 21IS _A and 21ID _A are formed at a shallow position also, also in said mesa structure M _B similarly, the pn junction surface pn _B indicated by a broken line by the lower of the n-type well 21NW and an upper p-type well 21PW buried insulating film It is formed in a shallower position than deeper bottom than the upper end of the 21IS _B and 21ID _B. By forming the pn junction surfaces pn _A and pn _B in this way, interference between the operation of the transistor Tr _{A and} the operation of Tr _B can be avoided.

Although overlapping with the above description, in the semiconductor device 20 of the present embodiment, as can be seen from the cross-sectional views of FIGS. 3C and 3E and the plan view of FIG. 3G, the tap regions 21T _A and 21T from the active region 21A. to _B, the gate electrode _23G a, under the 23G _B, wherein the n-type well 21NW and the p-type well 21PW, constitutes a part of a silicon substrate 21, respectively the mesa structure 21M _a and the mesa structure 21M _B It should be noted that the extending portions 21Ex _A and 21Ex _B are included. The extended portion 21ex _A is the mesa structure 21M central portion corresponding to the _A (21Ex _{A) A} and the peripheral portion of both sides (21Ex _{A) B,} is more configuration and (21Ex _{A) C,} wherein the central portion Figure 3H It is composed of p-type well 21PW of the silicon substrate 21 as shown in, and passed under the thin shallow insulating film region (21IT _{a) a} continuous from said device isolation region 21I reaches the tap region 21T _a and, constituting the body of the Dt-MOS transistor Tr _a. Similarly the extended portion 21ex _B is the central part corresponding to the mesa structure 21M _B (21Ex _{B) A} and the peripheral portion of both sides (21ex _{B) B,} is more configuration and (21ex _{B) C,} said central portion ( 21Ex _B ) _A is composed of a p-type well 21PW of the silicon substrate 21 as shown in FIG. 3H, and passes under the thin and shallow insulating film region portion (21IT _B ) _A continuous from the element isolation region 21I. reaches the tap region 21T _B Te, constituting the body of the Dt-MOS transistor Tr _B. However, FIG. 3H is a plan view in which the shallow insulating film region portions (21IT _A ) _A and (21IT _B ) _A are removed from the plan view of FIG. 3G.

As described above, in the Dt-MOS transistor Tr _A , the channel region CH _A is used as a body, and under the shallow insulating region portion (21IT _A ) _A via the central portion (21Ex _A ) _A of the extending portion 21Ex _A. through it, drawn to the tap region 21T _a formed outside the active region 21A. Similarly, in the Dt-MOS transistor Tr _B , its channel region CH _B serves as the body and passes under the shallow insulating region portion (21IT _B ) _A through the central portion (21Ex _B ) _A of the extending portion 21Ex _B. Te, drawn up the tap region 21T _B formed outside the active region 21A. In this case, according to the present embodiment, the thickness of the shallow insulating region portion (21IT _A ) _A can be reduced, and the p-type well constituting the central portion (21Ex _B ) _A of the extension portion 21Ex _B A height sufficient for 21 PW can be secured. As a result, it becomes possible to reduce the body resistance of the Dt-MOS transistor Tr _A. For example 230nm~270nm the depth of the pn junction plane 21pnA in the cross section of FIG. 3E, the shallow insulation film region portion (21IT _B) when the 45nm~55nm a thickness of _A, p-type in said mesa structure 21M _A As a body constituted by the well 21PW, a height of 185 nm to 225 nm can be secured. The same applies to the Dt-MOS transistor Tr _B.

Note the width of the mesa structure 21M _A is from the outer end of the sidewall insulation film 24a in Figure 3D of the cross-section outer end of the sidewall insulating film 24b, or to the outer end of the sidewall insulating films 24d from the outer end of the sidewall insulation film 24c When the gate length of the transistor TrA or TrB is 60 nm, for example, it is about 120 nm. In the cross section of FIG. 3E, when the manufacturing method described later is applied, this width is slightly smaller than this width. Value. However, the above dimensions are merely examples, and the present embodiment is not limited to such specific dimensions.

On the other hand, the peripheral portions (21Ex _A ) _B and (21Ex _A ) _C of the extended portion 21Ex _A are the shallow insulation, as can be seen from the cross-sectional views of FIGS. 3C and 3E and the plan views of FIGS. 3G and 3H. area portion (21IT _{a) a} both sides of the deep thick insulating film region portion (21IT _{a) B,} are formed of a n-type well 21NW extending below the (21IT _{a) C.} Therefore, as can be seen from the cross-sectional view of FIG. 3E, the central portion (21Ex _A ) _A of the extension portion 21Ex _A defined by the insulating film region portions (21IT _A ) _B and (21IT _A ) _C is _A mesa structure including a pn junction surface 21pnA and continuing to the mesa structure 21MA is formed between an upper part made of the type well 21PW and a lower part made of the n-type well 21NW. The peripheral portions (21Ex _A ) _B and (21Ex _A ) _C of the extension portion 21Ex _A are electrically isolated from the adjacent Dt-MOS transistor TrB by the element isolation region 21I.

Similarly, the peripheral portions (21Ex _B ) _B and (21Ex _B ) _C of the extending portion 21Ex _B are the shallow insulating films as can be seen from the cross-sectional views of FIGS. 3C and 3E and the plan views of FIGS. 3G and 3H. The region portion (21IT _B ) is formed of an n-type well 21NW extending under the deep and thick insulating film region portions (21IT _B ) _B and (21IT _B ) _C on both sides of _A. Therefore, as can be seen from the sectional view of FIG. 3E, the central portion (21Ex _B ) _A of the extension portion 21Ex _A defined by the insulating film region portions (21IT _B ) _B and (21IT _B ) _C is consists type well 21PW to form a mesa structure that is continuous with the mesa structure 21M _B includes a pn junction surface 21pnA between the lower formed of top and n-type well 21NW constituting the body. The peripheral portions (21Ex _B ) _B and (21Ex _B ) _C of the extending portion 21Ex _B are electrically isolated from the adjacent Dt-MOS transistor TrA by the element isolation region 21I.

Further, the deep thick insulating film region portion (21IT _A) as shown in the sectional view of FIG. 3C _B is the drain region 21D _A of the transistor Tr _A, i.e. the buried insulating film immediately under the source region 21S _B of the transistor Tr _B 21ID _a, thus buried insulating film 21IS is continuous in _B, the result, the drain region 21D _a, therefore the source region 21S _B never directly contact with the p-type well 21PW constituting the tap region 21TA. The same applies to the source region 21S _A and the drain region 21D _B.

According to the present embodiment, as shown in the sectional views of FIGS. 3B, 3C, and 3E, the insulating film region portions (21IT _A ) _B and (21IT _A ) _C , or the insulating film region portions (21IT _B ) _B and (21IT _B ) _{C up} to the depth of the source region or drain region, for example, the source region 21S _B , and thus the lower end of the drain region 21D _A , in the illustrated example, to the depth of the n-type well 21NW On the other hand, the insulating film region portion (21IT _A ) _A or (21IT _B ) _A is shallow, and the tap regions 21T _A and 21T _B are formed from the source region or the drain region of each transistor at the pn junction. The p-type structure constituting the body (21Ex _A ) _A or (21Ex _B ) _A is separated by an insulating film. It is possible to secure a sufficient height with respect to the cell 21PW, and it is possible to improve the operation speed of the Dt-MOS transistors Tr _A and Tr _B. According to the present embodiment, the insulating film region portion (21IT _A ) _A is shallower than the insulating film region portions (21IT _A ) _B and (21IT _A ) _C , and the resistance of the body can be reduced. Become.

As described above, in the present embodiment, the insulating film region portions (21IT _A ) _B and (21IT _A ) _C , or the insulating film region portions (21IT _B ) _B and (21IT _B ) _C are replaced with the n-type. It is not always necessary to form the well 21NW deeply. In particular, by forming the source region or the drain region, for example, the source region 21S _B , and therefore the depth exceeding the lower end of the drain region 21D _A , for example, exceeding the lower end of the silicon epitaxial layers 21ep _{1 to} 21ep ₃ , The film region portion (21IT _A ) _B is continuous with the buried insulating region 21ID _A in the active region 21A, that is, 21IS _B. As a result, the drain region 21D _A in the active region 21A, that is, the source region 21S _B is the device isolation region 21I, the buried insulating region 21ID _A and the enclosed by the insulating film region portion (21IT _{A) B,} is completely and reliably separated from the tap region 21TA. The same applies to the other of the source region 21S _A and the drain region 21D _B.

According to such a configuration, for example, positional deviation in the drain region 21D A in the cross section of FIG. _3C, therefore the source region 21S _B is formed by ion implantation occurs and until a portion of the tap region 21T _A, n + -type even when the impurity element as the ion implantation, the drain region 21D _a, therefore the source region 21S _B, are separated by a deep insulator region portion (21IT _{a) B} from the tap region 21T _a Therefore, the source region and the drain region are not short-circuited with the tap region, and the production yield of the Dt-MOS transistor can be improved.

Hereinafter, a method for manufacturing the semiconductor device 20 of the present embodiment will be described with reference to FIGS. 4A to 4M, FIGS. 5A to 5C, FIGS. 6 and 7A to 27E. Although only the Dt-MOS transistor Tr _A will be described with reference to FIGS. 4A to 4M, the same process is applied to the manufacture of the Dt-MOS transistor Tr _B.

Referring to FIG. 4A, in this embodiment, first, for example, a p ⁻ -type doped silicon substrate 21 is prepared, and if necessary, a p-type impurity element such as B (boron) is ion-implanted to form a p ⁻ -type well 21PW. Form.

Next, as shown in FIG. 4B, after the surface of the silicon substrate 21 is oxidized to form a thermal oxide film 21ox, a silicon nitride film 21N is deposited, and in the step of FIG. 4C, the silicon nitride film 21N and the thermal oxide film are further deposited. patterning the 21Ox, an opening 21IM and 21IT _a M for forming the element formation region of the isolation region 21I and the insulating film region 21IT _a are respectively formed to expose the surface of the silicon substrate 21.

Further protected by a resist pattern _{R 1} the opening 21IT _A M in the step of FIG. 4D, the said silicon substrate 21 in the step of FIG. 4E resist pattern _{R 1,} dry the silicon nitride film 21N and the thermal oxide film 21ox the mask Etching is performed to form an element isolation trench 21It corresponding to the element isolation region 21I.

To expose the surface of the silicon substrate 21 in addition the resist the opening pattern R1 is removed 21IT A _M in the step of FIG. 4F, further the silicon nitride film 21N and thermal oxidation of the silicon substrate 21 in the step of FIG. 4G dry-etching the film 21ox a mask to form a recess 21Pt example in 20nm~100nm depth d in the opening 21IT _a M. Further, along with this dry etching, the depth of the element isolation trench 21It reaches a predetermined depth of, for example, 250 nm to 400 nm.

  Further, in the step of FIG. 4H, a silicon oxide film 21Ox is formed on the silicon substrate 21 by, for example, high density plasma CVD so as to fill the element isolation trench 21It and the recess 21Pt. In the step of FIG. Using the nitride film 21N as a stopper, the silicon oxide film 21Ox on the silicon substrate is removed by a chemical mechanical polishing (CMP) method and dry etching.

In addition Figure 4J step, the silicon nitride film 21N and the thermal oxide film 21Ox is removed and the surface of the silicon substrate 21, the active region 21A and the tap region 21T _A, further illustrated is not, but the tap region 21T _B Expose to correspond to. As a result, an STI-type element isolation structure 21I is formed so as to fill the element isolation trench 21It so as to define the element region 210, and further fills the recess 21Pt in the element region 210. region 21IT _a is formed with a thickness corresponding to the depth d.

  Further, in the step of FIG. 4K, an n-type impurity element such as P (phosphorus) or arsenic (As) is ion-implanted into the silicon substrate 21 to a depth near the lower end of the element isolation region 21I. An n-type well 21NW is formed under the 21PW so that the upper end of the n-type well 21NW is shallower than the lower end of the element isolation region 21I, for example, a depth of 250 nm to 350 nm. In the illustrated example, the lower end of the n-type well 21NW coincides with the lower end of the element isolation region 21I. However, the lower end of the n-type well 21NW is not limited to such a specific depth, and is deeper. It doesn't matter.

  FIG. 5A shows a plan view of the silicon substrate 21 corresponding to the step of FIG. 4K.

Referring to FIG. 5A, the element isolation region 21I defines an element region 210 indicated by a thick line. In the element region 210, in addition to the insulating film region 21IT _A described in FIG. insulating film region 21IT _B is formed, as a result, the surface of the device region 210 by the insulating film region 21IT _a and 21IT _B, active regions 21A and the tap region _21T a, that is divided into 21T _B Recognize. In addition, from the active region 21A to the tap regions 21T _A and 21T _B , a part of the silicon substrate 21 corresponds to the plan views of FIGS. 3G and 3H described above, extending portions 21Ex _A and 21Ex _B As you can see, it extends.

5B is a cross-sectional view of the active region 21A along the line AA ′ in FIG. 5A, and FIG. 5C is a cross-sectional view of the extending portions 21Ex _A and 21Ex _B along the line BB ′ in FIG. 5A. .

5B, the active region 21A is defined by an element isolation region 21I. The active region 21A has an n-type well 21NW at a lower portion and a p-type well 21PW at an upper portion. It can be seen that pn junctions corresponding to the pn junctions 21 pn _A and 21 pn _B are formed at slightly shallower positions.

5C, the extension portions 21Ex _A and 21Ex _B are defined by the element region 21I, and have a thickness d of, for example, 20 nm to 100 nm in the BB ′ cross section. insulating film region 21IT _a, extend respectively below the 21IT _B, the p-type well 21PW has a height h of 150nm~230nm measured from the junction surface between the n-type well 21NW thereunder .

  Next, in the process of FIG. 4L, a polysilicon film 23 is formed with a film thickness of, for example, 150 nm to 200 nm on the silicon substrate 21 via a thermal oxide film or plasma oxide film 22i of, for example, 1 nm to 2 nm. 4M, a silicon nitride film 23n having a thickness of 1 nm to 2 nm is deposited on the polysilicon film 23 via a thermal oxide film or a plasma oxide film 23i having a thickness of 1 nm to 2 nm. 4L and 4M are cross-sectional views along line AA ′ in FIG. 5A.

Further patterning the polysilicon film 23 in the step of FIG. 4N, the polysilicon gate electrode 23G _A, the 23G _B, formed in a state in which each carrying the silicon nitride film 23n and the thermal oxide film or a plasma oxide film 23i . Thus formed polysilicon gate electrode _23G A, 23G _B is on the silicon substrate 21, as shown in the plan view of FIG. 6, the tap region 21T _A or tap region 21T from the active region 21A Up to _B , the insulating film regions 21IT _A and 21IT _B are respectively extended. Also, the activity in the regions 21A the thermal oxide film or a plasma oxide film 22i is a gate insulating film 22A immediately below the gate electrode 23G _A, also to form a gate insulating film 22B immediately below the gate electrode 23G _B. Although not shown, such gate electrode 23G with the formation of _A, the insulating film 22Ai by the thermal oxide film or a plasma oxide film 22i in the extended portion 23EX _A is formed. Although not shown, the even extending portion 23EX _B, under the gate electrode 23G _B, by the thermal oxide film or a plasma oxide film 22i, similar insulating film is formed.

  Further, in the step of FIG. 4O, the silicon oxide film 23O and the silicon nitride film 23N are sequentially formed on the structure of FIG.

  After the step of FIG. 4K, the method for fabricating the semiconductor device according to the present embodiment proceeds to the steps shown in FIGS. 7A to 7E. 7A is a plan view of the semiconductor device 20 in this process, and FIGS. 7B to 7E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. .

Referring to FIGS. 7A to 7E, in this step, the silicon nitride film 23N is etched back with the silicon oxide film 23O below as a stopper except for the tap regions 21T _A and 21T _B, and as a result, the gate wherein the electrode 23G _a silicon nitride film 23N sidewall insulating from film 23Na, 23Nb is, the formed through the silicon oxide film 23O, further the gate electrode 23G sidewall insulating films 23Nc from the silicon nitride film 23N is in _B, 23Nd Is formed through the silicon oxide film 23O. Here, the side wall insulating films 23Na to 23Nd are temporary gate side wall insulating films as will be described later.

  After the steps of FIGS. 7A to 7E, the method for fabricating the semiconductor device according to the present embodiment proceeds to the steps shown in FIGS. 8A to 8E. 8A is a plan view showing the semiconductor device 20 being fabricated, and FIGS. 8B to 8E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. It is.

In the step shown in FIG 8A~ Figure 8E, to the structure of the previous figures 7A~ Figure 7E, said polysilicon gate electrode 23G _A and 23G _B of the silicon nitride film 23n, and the sidewall insulating film 23Na~23Nd a stopper The silicon oxide film is dry etched to correspond to the recesses 21Pt having a depth d outside the sidewall insulating films 23Na and 23Nb and outside the sidewall insulating films 23Nc and 23Nb in the extending portions 21Ex _A and 21Ex _B. The recessed portion 21Pt _A and the similar recessed portion 21Pt _B are exposed. The p-type well 21PW is exposed on the bottom and side wall surfaces of the recesses 21Pt _A and 21Pt _B. Also in the active region 21A, with the exception of the portion where the gate electrode _23G A, the 23G _B and the sidewall insulating films 23Na~21Nd is formed, the p-type well 21PW is exposed. As shown in FIG. 8B or FIG. 8C and FIG. 8E, in this step, the silicon oxide film is etched to a depth d or more until the bottom of the recess 23PA is exposed. As shown in FIGS. 8C to 8E, the silicon oxide film is etched to the depth d or more.

  After the steps of FIGS. 8A to 8E, the method for fabricating the semiconductor device according to the present embodiment proceeds to the steps shown in FIGS. 9A to 9E. 9A is a plan view showing the semiconductor device 20 being fabricated, and FIGS. 9B to 9E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. is there.

Figure 9A~ in the step shown in Figure 9E, compared the structure of the previous figures 8A~ Figure 8E, the tap region _21T A, the silicon nitride film covering the 21T _B 23N and the polysilicon gate electrode _23G A, a silicon covering the 23G _B a nitride layer 23n and the sidewall insulating films 23Na~23Nd dry etching is performed with respect to the silicon substrate 21 as a mask, in cross-sectional view of FIG. 9D in the extended portion 21ex _a, sidewall insulation on the left of the polysilicon gate electrode 23G _a outer membrane 23Na, right right side wall insulating film 23Nb of the gate electrode 23G _a, the side wall on the right side of the outer left side by the sidewall insulation films 23Nc of the polysilicon gate electrode 23G _B, and the polysilicon gate electrode 23G _B on the outside of the insulating film 23Nd, the shallow recess 21 pt _a, deep tray from 21 pt _B Ji _{21TR A, 21TR B, 21TR C} , 21TR D are respectively formed, of which trench 21TR _B and the trench 21TR _C are adjacent to each other across the device isolation region 21I.

Further, the trench 21TR _A and 21TR _B form a mesa structure 23M _A between the mesa structure 23M _A is said p-type well 21PW, formed by laminating an insulating film region (21IT _{A) A} thereon, wherein the gate electrode 23G _a, the sidewall insulating film 23Na and 23Nb, and a silicon oxide film 23O in company interposed between and supports. It said trench 21TR _C and 21TR _D similarly form a mesa structure 23M _B between the mesa structure 23M _B is said p-type well 21PW, formed by laminating an insulating film region (21IT _{B) A} thereon, wherein the gate electrode 23G _B, the sidewall insulating films 23Nc and 23Nd, and the silicon oxide film interposed between 23O in company and supports.

Wherein in the etching for forming the trench 21TR _A ~21TR _D, in the active region 21A at the same time, the trench 21TR _E, 21TR _F and 21TR _G is, outwardly left side in the drawing of the sidewall insulating film 23Na of each of the gate electrodes 23G _A, the gate outside in the figure right sidewall insulating films 23Nb of electrodes 23G _a, and outside of the sidewall insulating films 23Nc in the left side in the drawing of the gate electrode 23G _B, the outer side of the gate electrode 23G in the figure sidewall insulating films 23Nd in the left _B Formed.

Said active region said mesa structure in 21A 21M _A extends between the trench 21TR _F and the trench 21TR _E, also mesa structure 21M _A extending between said trench 21TR _G and the trench 21TR _F.

As can be seen from FIG. 9C, the trench 21TR _B is continuous to the trench 21TR _F , but is formed deeper than the trench 21TR _F by the depth d of the recess 21Pt _A. The same applies to the other trenches 21TR _A , 21TR _C, and 21TR _D. The trench 21TR _A is continuous to the trench 21TR _E , the trench 21TR _B and the trench 21TR _C are continuously connected to the trench 21TR _F , and the trench 21TR _D is continuous to the trench 21TR _G.

In the illustrated example, as can be seen from FIG. 9C, the trench 21TR _B is formed so as to expose the n-type well 21NW in the extending portion 21ExA, and the other wells are the same, but in the present embodiment, it is not necessarily the case. The trench 21TR _B does not need to expose the n-type well 21NW, and the trench 21TR _B can be formed, for example, in the p-type well 21PW.

  After the steps of FIGS. 9A to 9E, the method for fabricating the semiconductor device according to the present embodiment proceeds to the steps shown in FIGS. 10A to 10E. Here, FIG. 10A is a plan view showing the semiconductor device 20 under fabrication, and FIGS. 10B to 10E are cross-sectional views taken along lines BB ′, CC ′, DD ′ and EE ′, respectively. is there.

Figure 10A~ in the step shown in FIG. 10E, to the structure of FIG 9A~ Figure 9E, the silicon nitride film 23N, the polysilicon gate electrode silicon nitride film on 23G _A 23n and the sidewall insulating film 23Na, 23Nb, and the polysilicon gate electrode silicon nitride film on 23G _B 23n and the sidewall insulating film 23 nC, while using 23Nd oxidation mask, thermal oxidation treatment or a plasma oxidation process, in the active region 21A is the trench _21T a _{~21T A} continuous silicon oxide film 21Oxd is formed to a thickness of 5 nm to 20 nm, for example, 10 nm, on the bottom surface and side wall surface of _D , and on the bottom surface and side wall surfaces of the trenches 21TE to 21TG in the extension portions 21Ex _A and 21Ex _B. To do. As a result, as shown in FIGS. 10D and 10E, the side wall surface of the mesa structure 21MA is continuously covered from the bottoms of the trenches 21E and 21F by the silicon oxide film 21Oxd having a thickness of 10 nm. The silicon oxide film 21Oxd is continuous with the silicon oxide film 23O covering the tap region 21Ta or 21Tb under the silicon nitride film 23N.

  After the steps of FIGS. 10A to 10E, the semiconductor device manufacturing method according to the present embodiment proceeds to the steps shown in FIGS. 11A to 11E. Here, FIG. 11A is a plan view showing the semiconductor device 20 under fabrication, and FIGS. 11B to 11E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. It is.

Figure 11A~ in the step shown in Figure 11E, of the structure of FIG 10A~ Figure 10E, the trench _{21TR A, 21TR B, 21TR C} , a resist pattern _{R 2} is formed on 21TR _D, each of the silicon oxide film 21Oxd Protect. In the cross-sectional views of FIGS. 11C and 11E, the resist pattern R2 is drawn so as to be formed to a height corresponding to the surface of the original substrate. However, the present embodiment is not limited to such a specific configuration. The resist pattern R2 can be formed at an arbitrary height as long as the silicon oxide film 21Oxd is protected in the trenches 21TR _A , 21TR _B , 21TR _C , and 21TR _D.

  After the steps of FIGS. 11A to 11E, the semiconductor device manufacturing method according to the present embodiment proceeds to the steps shown in FIGS. 12A to 12E. 12A is a plan view showing the semiconductor device 20 under fabrication, and FIGS. 12B to 12E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. is there.

In the step shown in FIG 12A~ Figure 12E, the resist pattern _{R 2} is removed, further trench 21TR _E in the active region 21A, said silicon oxide film 21Oxd from the bottom surface of 21TR _F and 21TR _G, selectively etched Then, the surface of the silicon substrate 21 is exposed. However, as shown in the cross-sectional view of FIG. 12D, the silicon oxide film 21Oxd is formed on the side wall surfaces of the trench trenches 21TR _E , 21TR _F, and 21TR _G , that is, on the side wall surfaces of the mesa structures 21MA and 21MB. Except for the lower end where the oxide film 21Oxd was formed, it remains.

For example, the selective etching described above is performed by isotropic etching and anisotropic etching that operates in a direction substantially perpendicular to the surface of the silicon substrate 21, and the isotropic etching reduces the film thickness by 3 nm. By reducing the film thickness by 7 nm by isotropic etching, the film thickness of the silicon oxide film 21Oxd covering the side walls of the mesa structures 21MA and 21MB in the active region 21A is reduced from the initial 10 nm to 7 nm. Meanwhile, the extended portion 21ex _A, in 21ex _B, the silicon oxide film 21Oxd because that were protected by the resist pattern _{R 2,} maintains the thickness of the original 10 nm. The isotropic etching can be performed by wet etching using HF.

  As the silicon oxide film 21Oxd is etched, in this step, as shown in FIGS. 12B to 12D, the height of the element isolation region 21I that defines the active region 21A corresponds to the thickness of the silicon oxide film 21Oxd. Only has decreased.

  After the steps of FIGS. 12A to 12E, the method for manufacturing the semiconductor device according to the present embodiment proceeds to the steps shown in FIGS. 13A to 13E. Here, FIG. 13A is a plan view showing the semiconductor device 20 being fabricated, and FIGS. 13B to 13E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. is there.

In the step shown in FIG 13A~ Figure 13E, in the silicon substrate 21 is the active region 21A, the silicon nitride film 23N, the gate electrode _23G A, a silicon nitride film on 23G _B 23n and the sidewall insulating films 23Na～23Nd, Further, the silicon oxide film 21Oxd covering the bottom surfaces of the trenches 21TR _{A to} 21TR _D is used as a mask to perform etching by anisotropic etching acting substantially perpendicular to the surface of the silicon substrate 21, and as a result, as shown in FIG. The trenches 21TR _{E to} 21TR _G are dug until the n-type well 21NW is exposed.

As a result, as can be seen from FIG. 13D, the mesa structure _21M A, so the bottom of 21M _B include pn junction plane 21Pn _A and 21Pn _B of the p-type well 21PW and n-type well 21NW.

13A to 13E, the silicon oxide film 21Oxd is slightly formed in the active region 21A and the extended portions 21Ex _A and 21Ex _B by wet etching using HF in a post-processing step after the etching of the silicon substrate. undergo etching, so that the thickness of the silicon oxide film 21Oxd formed on the sidewall surface of the mesa structure _21M a, 21M _B in the active region 21A shown in Figure 13D, for example, reduced from the previous 7nm to about 5 nm. On the other hand, the thickness of the silicon oxide film 21Oxd formed on the sidewall surface of the mesa structure _21M A, 21M _B in the extending portion 21ex _A, 21ex _B shown in FIG. 13E is reduced from the previous 10nm for example, 8 nm.

  After the steps of FIGS. 13A to 13E, the method of manufacturing the semiconductor device according to the present embodiment proceeds to the steps shown in FIGS. 14A to 14E. 14A is a plan view showing the semiconductor device 20 being fabricated, and FIGS. 14B to 14E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. is there.

In the active region 21A in the step shown in FIG 14A~ Figure 14E, the silicon nitride film 23N, the gate electrode _23G A, a silicon nitride film on 23G _B 23n and the sidewall insulating films 23Na～23Nd, further said trench 21TR _A ~ the silicon oxide film 21Oxd covering the bottom surface of the 21TR _D in a mask to perform epitaxial growth of the SiGe mixed crystal layer on the silicon substrate 21, corresponding to said trench 21TR _E ~21TR _G as shown in the sectional view of FIG. 14D SiGe mixed crystal layer 21SG _E, 21SG _F, the 21SG _G, from the n-type well 21NW, beyond the mesa structure 21M _a and 21M pn junction plane 21Pn _a and 21Pn _B in _B, buried in FIG. 3C and 3D on the write insulating film 21IS _a ~21ID _B Epitaxially grown to a predetermined height corresponding to further the SiGe mixed crystal layer 21SG _E, 21SG _F, a silicon cap layer 21ep ₁ ~21ep ₃ on 21SG _G, is respectively grown epitaxially. At that time, the silicon cap layer 21ep ₁ ~21 example _{p 3} acts to suppress the surface asperity caused by the abnormal growth of the SiGe mixed crystal layer 21Si _E ~21Si in _G. In the mesa structure 21M _A and 21M _B, since the side wall surface is covered with the silicon oxide film 21Oxd, never the SiGe mixed crystal layer 21Si _E ~21Si _G is the growth crawls up the side wall.

  The epitaxial growth of such a SiGe layer is, for example, under a pressure of 1330 to 13300 Pa (10 to 100 Torr), preferably under a pressure of 5320 Pa (40 Torr), at a substrate temperature of 650 to 750 ° C., preferably at a substrate temperature of 700 ° C. The hydrogen gas partial pressure is set to 4000 Pa to 6000 Pa, preferably 5300 Pa, the dichlorosilane partial pressure is set to 20 Pa to 30 Pa, preferably 26 Pa, the monogermane partial pressure is set to 10 Pa to 15 Pa, preferably 12 Pa, and chlorinated. The hydrogen partial pressure is set to 10 Pa to 15 Pa, preferably 12 Pa, and the growth can be performed at a growth rate of 45 nm / min.

As the SiGe mixed crystal layers 21SG _{E to} 21SG _G , for example, those containing about 20% of Ge by atomic fraction are used, but the composition of Ge should be increased as long as it can be epitaxially grown on the silicon substrate 21. Can do. For example SiGe mixed crystal containing approximately 40% by atomic fraction to Ge, it is also possible to use as the SiGe mixed crystal layer 21SG _E ~21SG _G. As the SiGe mixed crystal layer 21SG _E ~21SG _G, it is also possible to use SiGeC mixed crystal layer further comprises a C.

The growth of the silicon epitaxial layer 21ep ₁ ~21ep _3, the pressure under 1330~13300Pa (10~100Torr), preferably under a pressure of 5320Pa (40Torr), a substrate temperature of 650 to 750 ° C., the substrate preferably 700 ° C. At temperature, the hydrogen gas partial pressure is set to 4000 Pa to 6000 Pa, preferably 5300 Pa, the dichlorosilane partial pressure is set to 15 Pa to 25 Pa, preferably 21 Pa, and the hydrogen chloride partial pressure is set to 3 Pa to 10 Pa, preferably 5 Pa. However, it can be performed at a growth rate of 0.7 nm / min.

In the illustrated example, the upper ends of the silicon cap layers 21ep _{1 to} 21ep ₃ are drawn so as to correspond to the upper ends of the element isolation structures 21I. However, this is not essential, and the silicon cap layers 21ep _{1 to} 21ep ₃ may be above or below the upper end of the element isolation structure 21I.

In the cross section of FIG. 14E, since the bottom and side walls of the trenches 21TR _{A to} 21TR _D are covered with the silicon oxide film 21Oxd, the growth of the SiGe mixed crystal layer or the silicon epitaxial layer does not occur.

14A to 14E, prior to the epitaxial growth of the SiGe mixed crystal layer, wet etching using HF is performed as a pretreatment step on the structure of FIGS. 13A to 13E. , the mesa structure _21M a is in the active region 21A shown in FIG. 14D, the thickness of the silicon oxide film 21Oxd on the side wall surface of 21M _B, has decreased from the initial 5nm to about 3 nm.

  After the steps of FIGS. 14A to 14E, the method of manufacturing the semiconductor device according to the present embodiment proceeds to the steps shown in FIGS. 15A to 15E. 15A is a plan view showing the semiconductor device 20 under fabrication, and FIGS. 15B to 15E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. is there.

In the active region 21A in the step shown in FIG 15A~ Figure 15E, the silicon oxide film 21Oxd the thickness mentioned above is reduced to 3nm is, the mesa structure _21M A, wet etching from the side wall surface of 21M _B Is removed. Accordingly, the extended portion 21ex _A, wherein in the 21ex _B mesa structure _21M A, the thickness of the sidewall insulating films 21Oxd of 21M _B is reduced to about 3 nm.

Also omitted is shown along with this, the active region 21A in the polysilicon gate electrode _23G A, the silicon oxide film 23O formed on the side wall surface even 23G _B, respectively of the polysilicon gate electrode _23G A, 23G _Although it slightly recedes from the upper end of _B corresponding to the isotropic etching such as repeated wet etching, the receding distance is about 10 nm at the most, so that it is formed on the polysilicon film 23 in the process of FIG. 4M. the silicon nitride film 23n, by forming the film thickness of at least 10 nm, the gate electrode 23G _a or 23G _B are not exposed in the step of FIG 15A~ Figure 15D.

  After the steps shown in FIGS. 15A to 15E, the manufacturing method of the semiconductor device being manufactured proceeds to the steps shown in FIGS. 16A to 16E. Here, FIG. 16A is a plan view of the semiconductor device 20 in this process, and FIGS. 16B to 16E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. .

In the steps shown in FIGS. 16A to 16E, the growth of the silicon epitaxial layers 21ep ₁ , 21ep ₂ and 21ep ₃ in the structure of FIGS. 15A to 15E is resumed under the same conditions as described above. Thus, the trenches 21TR _E , 21TR _F and 21TR _G are filled with the silicon epitaxial layers 21ep ₁ , 21ep ₂ and 21ep _{3 in the} active region 21A. In the cross-sectional view of FIG. 16D the silicon epitaxial layer 21Ep ₁ is coupled to the left side in the drawing the wall of the mesa structure 21M _A, whereas the silicon epitaxial layer 21Ep ₂ is coupled to the right side in the drawing the wall of the mesa structure 21M _A . Also, the silicon epitaxial layer 21Ep ₂ is the mesa structure 21M figure also coupled to the left side wall of _B, whereas the silicon epitaxial layer 21Ep ₃ is coupled to the right side in the drawing the wall of the mesa structure 21M _B. Silicon epitaxial layer 21ep ₁ ~21ep in FIG 16E ₃ correspond respectively to the silicon epitaxial layer 21ep ₁ ~21ep ₃ of Figure 3D.

  After the steps of FIGS. 16A to 16E, the method for manufacturing the semiconductor device according to the present embodiment proceeds to the steps shown in FIGS. 17A to 17E. Here, FIG. 17A is a plan view showing the semiconductor device 20 under fabrication, and FIGS. 17B to 17E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. is there.

In the step shown in FIG 17A~ Figure 17E, an element isolation insulating film of the device isolation region 21I, the silicon nitride film 23N, the gate electrode _23G A, the silicon nitride film 23n and the sidewall insulating films on 23G _B 23Na~ the etched back to mask 23Nd, exposing the SiGe mixed crystal layer 21SG _E ~21SG _G in the element isolation trench 21It. In the illustrated example, the element isolation insulating film is completely removed from the element isolation trench 21It. As shown in the cross-sectional views of FIGS. 17C and 17E, the silicon oxide film 21Oxd is also removed in the trenches 21TR _{A to} 21TR _D.

As further seen from the cross-sectional view of FIG. 17B and FIG. 17E, with the etching back of the device isolation insulating film, the extending portion 21ex _A, shallow are formed the gate electrode _23G A, just below the 23G _B in 21ex _B insulating film region (21IT _{A) A,} is removed (21IT _{B) A,} the void 21IT _A V, 21IT _B V are respectively formed. Here, the central portion (21Ex _{A) A,} and portions of the left and right peripheral portion of the extending portion 21ex _A the extended portion 21ex _A in mesa region 21M _A is in the view _{3E (21Ex A) B, (} 21Ex A) _C is formed. The central portion (21ex _{B) A} and the peripheral portion part of the left and right extending portions 21ex _B in the same manner as the extending portion 21ex mesas 21M _B in _B is FIG _{3E (21Ex B) B, (} 21Ex B) _C is formed.

  After the steps of FIGS. 17A to 17E, the method for fabricating the semiconductor device according to the present embodiment proceeds to the steps shown in FIGS. 18A to 18E. Here, FIG. 18A is a plan view showing the semiconductor device 20 being fabricated, and FIGS. 18B to 18E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. is there.

In the step shown in FIG 18A~ Figure 18E, the silicon nitride film 23N, the gate electrode _23G A, is exposed in the device isolation trench 21It silicon nitride film 23n and the sidewall insulating films 23Na~23Nd on 23G _B to mask wet etching the SiGe mixed crystal layers 21SG _E ~21SG _G, for example, chlorine (Cl ₂₎ and a mixed gas of hydrogen, or by dry etching with hydrogen chloride gas, or using a mixture of hydrofluoric acid or the like and nitric or acetic Then, the silicon substrate 21 and the silicon epitaxial layers 21 ep ₁ , 21 ep ₂ , 21 ep ₃ are selectively etched by dry etching using CF ₄ gas diluted with Ar. SiGe mixed crystal layers 21SG _E , 21SG _F , 21 Each corresponding to the formation region of SG _G, to form a void _21V 1 _{~21V 3.}

  After the steps of FIGS. 18A to 18E, the method for fabricating the semiconductor device according to the present embodiment proceeds to the steps shown in FIGS. 19A to 19E. Here, FIG. 19A is a plan view showing the semiconductor device 20 being fabricated, and FIGS. 19B to 19E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. is there.

In the step shown in FIG 19A~ Figure 19E, the silicon oxide film 41 on the structure shown in FIG 18A~ Figure 18E, for example, by a high-density CVD method, the polysilicon gate electrode _23G A, deposited over the 23G _B and, wherein the void _21V 1 _{~21V 3,} and void 21IT _a V, the 21IT _B V is filled with the silicon oxide film 41.

  After the steps of FIGS. 19A to 19E, the semiconductor device manufacturing method according to the present embodiment proceeds to the steps shown in FIGS. 20A to 20E. 20A is a plan view showing the semiconductor device 20 under fabrication, and FIGS. 20B to 20E are cross-sectional views taken along lines BB ′, CC ′, DD ′ and EE ′, respectively. is there.

  20A to 20E, the silicon oxide film is planarized by chemical mechanical polishing, and then etched until the silicon nitride film 23N covering the tap regions 21Ta and 21Tb is exposed on the silicon substrate 21. Back.

As a result, the polysilicon gate electrode _23G A as shown in FIG. 20A~ Figure 20E, 23G _B are exposed in a state of being covered with the silicon nitride film 23n and the sidewall insulating films 23Na～23Nd. 20C or 20D, the surface of the silicon epitaxial regions 21ep1 to 21ep3 is covered with the silicon oxide film 41 with a thickness substantially corresponding to the silicon oxide film 23O.

  After the steps of FIGS. 20A to 20E, the method for manufacturing the semiconductor device according to the present embodiment proceeds to the steps shown in FIGS. 21A to 21E. Here, FIG. 21A is a plan view showing the semiconductor device 20 being manufactured, and FIGS. 21B to 21E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. is there.

  21A to 21E, the silicon nitride film on the silicon substrate is selectively removed. As a result, the silicon nitride film 23n on the polysilicon gate electrodes 23GA and 23GB is removed, and the silicon oxide film thereunder is removed. The film 23i is exposed and the sidewall insulating films 23Na to 23Nd are all removed. Further, the silicon nitride film 23N is removed in the tap regions 21TA and 21TB, and the underlying silicon oxide film 23O is exposed.

  After the steps of FIGS. 21A to 21E, the semiconductor device manufacturing method according to the present embodiment proceeds to the steps shown in FIGS. 22A to 22E. Here, FIG. 22A is a plan view showing the semiconductor device 20 being fabricated, and FIGS. 22B to 22E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. is there.

In Figure 22A~ view 22E step, the silicon oxide film 41, the polysilicon gate electrode _23G A, a mask 23G _B, the silicon epitaxial layer 21ep ₁ ~21ep ₃ and the tap region _21T A, the surface of the 21T _B It is further etched back until it is exposed. As a result, the original STI-type element isolation structure 21I is recovered in the element isolation trench 21It, and deep insulating film regions (21IT _A ) _{B on} both sides of the shallow insulating film region 21IT _A surrounded by a broken line in FIG. 22A. , (21IT _A ) _C and deep insulating film regions (21IT _B ) _B , (21IT _B ) _C are formed on both sides of the shallow insulating film region 21IT _B so as to be continuous with the element isolation region 21I.

Furthermore, although not shown, the n-type impurity element into said silicon epitaxial layer 21ep in _{1 ~21ep 3} in the structure of FIG. 22 a to 22 e, the polysilicon gate electrode 23GA, n-type, such as As or P to 23GB to mask by the impurity element ion implantation source source extension region 21a and 21b described in the section view of FIG. 3C is in the left and right in Figure the gate electrode 23G _a respectively, also described in the section view of FIG. 3C extension regions 21c and 21d on the left and right in Figure the gate electrode 23G _a respectively, are formed.

Thereafter, the gate electrode _23G A, by forming the sidewall insulating films 24a~24d described in FIG 3A~ to 3E to 23G _B, is ion-implanted n-type impurity element such as As or P again, in FIG. 3D wherein in the silicon epitaxial layer 21Ep ₁ as shown in the sectional view, the sidewall insulation film 24a source extension region n + -type source region 21S _a outside the 21a immediately below are also within the silicon epitaxial layer 21Ep _2, the sidewall insulation drain region 21D _a n + -type outside the drain extension region 21b right under film 24b is formed. Similarly, in the silicon epitaxial layer 21Ep ₂ as shown in the sectional view of FIG. 3D, the sidewall insulation film 24c source extension region 21c n + -type source region 21S _B outside the nadir direction, the n + -type drain of continuously in regions 21da, also said in the silicon epitaxial layer 21Ep _3, the sidewall insulation film 24d drain extension region 21d n + -type drain region 21D _B outside the nadir direction, are formed.

At the same time, the gate electrode _23G A, 23G _B is also doped n + -type respectively.

Further, in the structure thus formed, p + type contact regions 21T _A P and 21T _B P are formed by ion implantation of a p type impurity element such as _B into the tap regions 21T _A and 21T _B , and then exposed. silicon surface, i.e. the polysilicon gate electrode _23G a, the upper surface of 23G _B, the active region 21A source region in 21S _a, the drain region 21S _B, therefore the source region 21S _B, the drain region 21D _B, further the n- type taps region _21T a, the surface to the silicide layer _23G As the _{21T B, 23G Bs, 21S As} , 21D As, 21S Bs, the _{21D Bs,} formed by a salicide method, further the shared contact plug _23T a Sc, said by _23T B Sc before the polysilicon gate electrode 23G _a And electrically connected through the silicide layer _{23G As} and _{21T As} in the serial tap region 21T _A, electrically via the silicide layer _{23G Bs} and _{21T Bs} the polysilicon gate electrode 23G _B in the tap region 21T _B Thus, the transistors Tr _A and Tr _B can be formed as Dt-MOS transistors.

In the Dt-MOS transistors Tr _A and Tr _B formed in this way, the channel region is formed in a part of the original silicon substrate made of a high-quality silicon single crystal, so that carriers are scattered and disappeared in the channel. It is suppressed, and high speed operation is possible with low power consumption.

In the present embodiment, for example, Dt-MOS transistor Tr middle portion of the insulating film region 21IT _A in _A (21IT _{A) A} is shallow, for example, because being shallower than the lower end of said silicon epitaxial layer 21ep ₁ ~21ep ₃ The height of the p-type well 21PW that passes under the central portion (21IT _A ) _A and forms the body of the Dt-MOS transistor Tr _A , that is, the central portion (21Ex _A ) _A of the extending portion 21Ex _A may be reduced. In addition, an increase in resistance of the body can be avoided. The same applies to the Dt-MOS transistor Tr _B.

In the present embodiment, for example, in Dt-MOS transistor Tr _A, the central portion (21IT _A) on both sides of _A insulating film region portion of the thus the insulation film region _{21IT A (21IT A) B,} (21IT A) C Are continuous with the buried insulating regions 21IS _A and 21ID _S formed under the source region 21S _A and the drain region 21D _{A in} the active region 21A, respectively, the source region 21S _A and the drain region 21D _A It is completely separated from the area 21T _A. The same applies to the Dt-MOS transistor Tr _B.

  23A to 23E are diagrams showing a configuration of a semiconductor device according to a modification of the first embodiment. FIG. 23A is a plan view, and FIGS. 23B to 23E are lines BB ′, FIG. It is sectional drawing along CC ', DD', and EE '. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.

Referring to FIGS. 23A to 23E, in this modification, the insulating film region portions corresponding to the central portions (21Ex _A ) _A and (21Ex _B ) _B among the insulating film regions of the extending portions 21Ex _A and 21Ex _B (21IT _{a) a,} omitted (21IT _{B) a,} forming an insulating film region portion _{(21IT a) B, (21IT} a) C, and the insulating film region portion (21IT _{B) B,} only (21IT _{B) C} doing. As a result, in the present modification, the p-type well 21PW has a structure extending along the flat surface of the silicon substrate 21 from the active region 21A to the tap region 21TA.

Even in such a configuration, the Dt-MOS transistors TrA and TrB perform a dynamic threshold operation, and at this time, of the insulating film regions of the extending portions 21Ex _A and 21Ex _B , the central portion (21Ex _A ) _A and (21Ex _B ) The resistance of the body formed by _B can be further reduced.

This modification corresponds to the case where the depth d of the recess 21Pt is zero in the previous embodiment. In the semiconductor device according to the present modification, the surface of the silicon substrate 21, the first insulating film region portion (21IT _{A) B} and the insulating film region portion (21IT _A) between is _C, also the second insulating film region portion (21IT _B ) The well 21PW extends continuously from the active region 21A and is interposed between _B and the insulating film region portion (21IT _B ) _C.

  24A to 24F are views showing a configuration of a semiconductor device according to another modification of the first embodiment, in which FIG. 24A is a plan view, and FIGS. 24B to 24F are lines BB ′ in FIG. 24A, respectively. , CC ′, DD ′, EE ′, and FF ′. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.

Referring to FIG. 24A~ Figure 24E, under the tap regions 21T _A and 21T _B in this modified example, each of the buried insulating film 21ITbT _A and 21ITbT _B extending from the isolation region 21I, the buried insulating The films 21IS _{A to} 21ID _B are formed at the same time and in the same manner.

By forming a buried insulating film 21ITbT _A and 21ITbT _B under this way tap regions 21T _A and 21T _B, it is possible to further reduce the parasitic capacitance of the tap region 21T _A and 21T _B. Such a configuration is applicable not only to the embodiments described above but also to other embodiments described below.

In the above embodiments, the polysilicon gate electrode _23G A, 23G _B and tap region _21T A, the electrical connection 21T _B, shared contact plug _23T A Sc, had been made by _23T B Sc, the present embodiment It is not limited to a specific configuration using such a shared contact plug, and it is also possible to perform electrical connection using a wiring pattern as shown in FIGS. 25A and 25B. 25A is a plan view, and FIG. 25B is a cross-sectional view along the line BB ′ in FIG. 25A. In the plan view of FIG. 25A, for simplicity, the semiconductor device is shown with the wiring pattern removed.

Referring to the plan view of FIG. 25A, the polysilicon gate electrode _23G A in this embodiment, 23G _B is the tap region _21T A, it is formed so as not to reach the 21T _B, instead, the isolation region said on 21I polysilicon gate electrode _23G a, 23G _B by the connection pad region 23GP _a, is 23GP _B, each of the sidewall insulating film 24a, is surrounded by extending sidewall insulating film 24e from 24b, also the sidewall insulation films It is formed surrounded by a sidewall insulating film 24f extending from 24c, 24d. The connection pad region 23GP _A, 23GP _B are each the silicide layer _23G As, silicide layer _23GP As extending from _{23G Bs,} it is covered by 23GP _Bs.

Further, the polysilicon gate electrode 23G A is on the silicon substrate 21 as shown in the sectional view of FIG. _25B, the wiring covering the 23G _B pattern - carries down 27 _A and the insulating film 26 is formed, the forming emission 27A is in contact with said contacted by plug ₂₇ a _{V 1} to the silicide layer _{21T As} covering the tap region 21TA, also via plug ₂₁ a _{V 2} to the silicide layer 23GP _As covering the connection region 23GP _a - wiring pattern Has been. Similarly wiring patterns - emission and the via plug are not shown in the sectional view of FIG. 25B, are formed with respect to the polysilicon gate electrode 23G _B.

In the embodiments thus described above, also in the other embodiments described below, means for electrically connecting the polysilicon gate electrode 23G _A and 23G _B to each body is limited to the shared contact plug It is not a thing.

(Second Embodiment)
26A to 26E are diagrams showing the configuration of the semiconductor device according to the second embodiment. FIG. 26A is a plan view, and FIGS. 26B to 26E are lines BB ′ and CC ′ in FIG. 26A, respectively. , DD ′ and EE ′. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.

Referring to FIG. 26A~ Figure 26E, in the present embodiment has only a single Dt-MOS transistor TrA is formed in the active region 21A, As a result, the source drain region 21D _A is Dt-MOS transistor of the adjacent It is not shared with the area.

As shown in the sectional view of this for Figure 23D, between the mesa structures 21M _A buried insulator region 21IS _A and 21ID _A in, the buried insulating region 21IS _A, so as to be positioned between the upper and lower ends of the 21ID _A It is not necessary to form a pn junction to separate the transistors TrA and TrB, and therefore the n-type well 21NW is not necessarily required.

  Therefore, in the present embodiment, the n-type well 21NW is omitted.

  Even with such a configuration, the Dt-MOS transistor TrA can perform a desired dynamic threshold operation at high speed.

Also in the present embodiment, the central portion (21IT _A ) _A of the insulating film region 21IT _A can be omitted.

(Third embodiment)
27A to 27E are diagrams showing the configuration of the semiconductor device according to the third embodiment. FIG. 27A is a plan view, and FIGS. 27B to 27E are lines BB ′ and CC ′ in FIG. 27A, respectively. , DD ′ and EE ′. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.

Referring to FIG. 27A~ Figure 27E, in the present embodiment has only a single Dt-MOS transistor TrA is formed in the active region 21A, As a result, the source drain region 21D _A is Dt-MOS transistor of the adjacent It is not shared with the area.

In this embodiment, the buried insulating regions 21IS _A and 21ID _A , and hence 21IS _B and the buried insulating region 21ID _B are removed in the active region 21A, and the element isolation is the STI type element isolation region 21I and the p type well 21PW. This is realized by the lower n-type well 21NW.

At that time, in this embodiment of the insulating film region 21IT _A between the active region 21A and the tap region 21T _A, is formed corresponding to the polysilicon gate electrode 23G _A between said sidewall insulating films 24a and 24b The insulating film region portion (21IT _A ) _A is formed shallow, while the insulating film region portions (21IT _A ) _B and (21IT _A ) _C outside the side wall insulating films 24a and 24b are at least the source region 21S _A or drain deeper than the lower end region 21D _a, for example, the by p-type well formed deep so as to reach the n-type well 21NW under 21PW, the source region 21S _a and the drain region 21D buried insulator region under the _a 21IS even not _A or 21ID _A is formed, the source region 21S _A and drain It is possible to electrically isolate the emission region 21D _A from the tap region 21T _A.

Also in the present embodiment, the central portion (21IT _A ) _A of the insulating film region 21IT _A can be omitted.

  28A is a plan view showing one manufacturing process of the semiconductor device according to the present embodiment, and FIGS. 28B to 28E are lines BB ′, CC ′, DD ′ and EE ′ in FIG. 28A. FIG.

In the steps shown in FIGS. 28A to 28E, an element region 210 is defined on the silicon substrate 21 by the STI-type element isolation region 21I by the steps described in FIGS. 4A to 4K, and the insulating film region 21IT _A the surface of the silicon substrate 21 is divided into the active region 21A and the tap region 21T _a in the device region 210 by.

Further, on the previous embodiment as well as the silicon substrate 21, the active region 21A taps from the region 21T _A to the polysilicon gate electrode 23G _A is, in the active region 21A via a gate insulating film 22 _A, also It is formed through the insulating film _{22 Ai} extending from the gate insulating film 22A in the tap region 21T _a. Further, a silicon nitride film on the polysilicon gate electrode 23G _A gate sidewall insulating film 23Na, 23Nb is formed. The upper surface of the polysilicon gate electrode 23G _A is covered with the silicon nitride film 23n.

  After the steps of FIGS. 28A to 28E, the method for fabricating the semiconductor device according to the present embodiment proceeds to the steps shown in FIGS. 29A to 29E. Here, FIG. 29A is a plan view showing the semiconductor device being fabricated, and FIGS. 29B to 29E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. .

Figure In 29A~ view 29E step, the silicon nitride film 23n and the sidewall insulating film 23Na, the insulating film region 21IT _A polysilicon gate electrode 23G _A formed a 23Nb the mask is etched, the sidewall insulation film 23Na, A recess 21PtA is formed on the outer side of 23Nb in the same manner as in the steps of FIGS. 8A to 8E. On the other hand, under the polysilicon gate electrode 23G _A, the remaining central portion (21IT _{A) A} insulating film region 21IT _A.

  After the steps of FIGS. 29A to 29E, the semiconductor device manufacturing method according to the present embodiment proceeds to the steps shown in FIGS. 30A to 30E. Here, FIG. 30A is a plan view showing the semiconductor device being fabricated, and FIGS. 30B to 30E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. .

In Figure 30A~ view 30E step, the silicon nitride film 23n and the sidewall insulating film 23Na, a mask a polysilicon gate electrode 23G _A formed a 23Nb, silicon substrate 21 which is exposed by the recess 21PtA are etched, the sidewall insulating film 23Na, trench 21TR _a outside the 23Nb, have 21TR _B, a mesa structure 21M _a consisting of a portion of the silicon substrate 21 is sandwiched therebetween formed between.

  After the steps of FIGS. 30A to 30E, the semiconductor device manufacturing method according to the present embodiment proceeds to the steps shown in FIGS. 31A to 31E. Here, FIG. 31A is a plan view showing the semiconductor device being manufactured, and FIGS. 31B to 31E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. .

In the steps of FIGS. 31A to 31E, the trenches 21TR _A and 21TR _B are filled with a silicon oxide film, and the insulating film region portion (21IT _A ) _B corresponds to the trench 21TR _A and also corresponds to the trench 21TR _B. Thus, the insulating film region portion (21IT _A ) _C is formed.

  After the steps of FIGS. 31A to 31E, the semiconductor device manufacturing method according to the present embodiment proceeds to the steps shown in FIGS. 32A to 32E. Here, FIG. 32A is a plan view showing the semiconductor device being fabricated, and FIGS. 32B to 32E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. .

Figure In 32A~ view 32E step, the polysilicon gate electrode 23G _A sidewall insulation from film _23N a, 23N _b and the silicon nitride film 23n has is removed, the production of conventional MOS transistor in the active region 21A from the state run the process, a mask the polysilicon gate electrode 23GA in the active region 21A, the n-type impurity element such as P or As ions are implanted, in FIG 32A or FIG 32C of the polysilicon gate electrode 23G _a, An n-type source extension region 21a is formed on the left side, and a p-type drain extension region 21b is formed on the right side.

  After the steps of FIGS. 32A to 32E, the semiconductor device manufacturing method according to the present embodiment proceeds to the steps shown in FIGS. 33A to 33E. Here, FIG. 33A is a plan view showing the semiconductor device being fabricated, and FIGS. 33B to 33E are cross-sectional views taken along lines BB ′, CC ′, DD ′, and EE ′, respectively. .

In the state of FIG. 33A~ Figure 33E, the sidewall insulation film 24a on the polysilicon gate electrode 23G _A is, in the drawing on the left side in FIG. 33A or FIG. 33C, also in the side wall insulating film 24b is the view 33A or FIG. 33C The n-type impurity element is ion-implanted at a higher concentration and deeper again using the polysilicon gate electrode 23GA and the side wall insulating films 24a and 24b as masks. or an n + -type source region 21S _a left outer sides of the sidewall insulating film 24a in the sectional view of FIG. 33C, also the drain region 21D _a n + -type right outside, formed respectively.

Further although not shown, after the p-type impurity element such as B on the surface of the tap region 21T _A to form a high density ion implantation to the p + -type contact region 21T A _P, the polysilicon gate electrode 23S _A on a gate silicide film _{23S As,} the source and drain regions _21S a, silicide layer _21S As on 21S _B, the _{21D As,} after further forming a silicide layer _{21T As} the surface of the tap region 21T _a, for example, the shared By forming the contact plug 23T _A Sc, the semiconductor device described in FIGS. 27A to 27E can be manufactured.

  In each of the above embodiments, the p-type and n-type may be inverted.

Also, the gate electrode _23G A, 23G _B may be composed of amorphous silicon in place of polysilicon.

As mentioned above, although this invention was described about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and change are possible within the summary described in the claim.
(Appendix 1)
A semiconductor substrate;
An element isolation region formed in the semiconductor substrate;
An element region defined by the element isolation region in the semiconductor substrate;
In the semiconductor substrate, an insulating film region formed continuously with the element isolation region and dividing the element region into an active region and a tap region;
A first insulating film region portion formed continuously with the element isolation region in the insulating film region, and having a lower end at a position shallower than the surface of the semiconductor substrate than the lower end of the element isolation region;
A second insulating film region portion formed continuously with the element isolation region in the insulating film region and having a lower end at a position shallower than the lower surface of the element isolation region from the surface of the semiconductor substrate;
The insulating film region is formed continuously between the first insulating film region portion and the second insulating film region portion, and has a lower end of the first insulating film region portion and a second insulating film region portion. A third insulating film region portion having a lower end at a position shallower than the lower surface of the semiconductor substrate,
A gate electrode formed on the active region and the insulating film region and electrically connected to the tap region;
First and second side wall insulating films respectively formed on first and second gate side wall surfaces opposite to the gate electrode;
A body formed on the semiconductor substrate, continuous from the active region along the gate electrode to the tap region under the insulating film region, and having a first conductivity type;
A semiconductor device comprising: a diffusion region formed in the active region with the gate electrode interposed therebetween and having a second conductivity type opposite to the first conductivity type.
(Appendix 2)
The semiconductor device according to appendix 1, wherein a lower end of the first insulating film region portion and a lower end of the second insulating film region portion are located deeper than the lower end of the diffusion region.
(Appendix 3)
2. The semiconductor device according to claim 1, wherein in the semiconductor substrate, the body is provided between the first insulating film region portion and the second insulating film region portion.
(Appendix 4)
The semiconductor substrate includes a well of the second conductivity type under the body, and the lower end of each of the first insulating film region portion and the second insulating film region portion is at least the depth of the well. The semiconductor device according to claim 1, wherein the semiconductor device is reached.
(Appendix 5)
A first buried insulating film region and a second buried insulating film are formed under the diffusion regions of the active region on the first side wall surface side and the first side wall surface side of the gate electrode, respectively. Has an area,
Note that the first buried insulating film region and the second buried insulating film region are respectively continuous with the first insulating film region portion and the second insulating film region portion. 5. The semiconductor device according to 4.
(Appendix 6)
The lower end of the element isolation region is deeper than any one of the lower ends of the first and second buried insulating regions and the lower end of the insulating film region. The semiconductor device described.
(Appendix 7)
The well is deeper than the body, the upper end of the first buried insulating region and the upper end of the second buried insulating region, and the lower end of the first buried insulating region and the second buried insulating region. The semiconductor device according to appendix 5 or 6, wherein a pn junction is formed at a position shallower than the lower end.
(Appendix 8)
The semiconductor device according to any one of appendices 5 to 7, wherein the tap region includes a third buried insulating region under the body.
(Appendix 9)
The gate electrode reaches the tap region beyond the insulating film region, and is connected to the body by a shared contact plug in the tap region. Semiconductor device.
(Appendix 10)
9. The semiconductor device according to claim 1, wherein the gate electrode is electrically connected to the tap region by a wiring pattern.
(Appendix 11)
A first semiconductor substrate;
An element region defined by an element isolation region on the silicon substrate;
An insulating film region formed on the semiconductor substrate in succession to the element isolation region and dividing the element region into an active region and first and second tap regions;
A first insulating film region portion formed continuously with the element isolation region in the insulating film region, the lower end of which is shallower than the lower surface of the element isolation region from the surface of the semiconductor substrate;
A second insulating film region portion formed continuously with the element isolation region in the insulating film region, the lower end of which is shallower than the lower surface of the element isolation region from the surface of the semiconductor substrate;
The insulating film region is formed continuously between the first insulating film region portion and the second insulating film region portion, and the lower ends thereof are the lower end of the first insulating film region portion and the second insulating film region portion. A third insulating film region portion located at a position shallower from the surface of the semiconductor substrate than a lower end of the insulating film region portion; and the insulating film region formed continuously with the element isolation region; A fourth insulating film region portion located shallower from the surface of the semiconductor substrate than the lower end of the region;
A fifth insulating film region portion formed continuously in the insulating film region with the element isolation region, the lower end of which is shallower than the lower surface of the element isolation region from the surface of the semiconductor substrate;
The insulating film region is continuously formed between the fourth insulating film region portion and the fifth insulating film region portion, and the lower ends thereof are the lower end of the first insulating film region portion and the second insulating film region portion. A sixth insulating film region portion located shallower than the lower surface of the insulating film region portion from the surface of the semiconductor substrate; and formed on the active region and the insulating film region, and electrically connected to the first tap region. A first gate electrode connected to
First and second side wall insulating films respectively formed on first and second gate side wall surfaces opposite to the gate electrode;
A second gate electrode formed on the active region and the insulating film region and electrically connected to the second tap region;
Third and fourth sidewall insulating films respectively formed on third and fourth gate sidewall surfaces opposite to the gate electrode;
In the active region, a first diffusion region formed on the semiconductor substrate with the first gate electrode interposed therebetween and having a second conductivity type opposite to the first conductivity type;
The active region is formed on the semiconductor substrate with the second gate electrode interposed therebetween, has the second conductivity type, and is interposed between the first gate electrode and the second gate electrode. A second diffusion region connected to the first diffusion region;
In the active region between the first gate electrode and the second gate electrode, the active region is formed below the first diffusion region and the second diffusion region, and the second insulating film region portion and A central buried insulating film region continuing to the fourth insulating film region portion;
In the active region on the opposite side of the central buried insulating film region across the first gate electrode, the first region is formed below the first diffusion region and is continuous with the first insulating film region portion. The fifth insulating film is formed under the second diffusion region in the active region opposite to the central buried insulating film region with the second gate electrode interposed therebetween. A second buried insulating film region continuous with the region portion; and a third insulating film region portion formed in the semiconductor substrate and extending from the active region to the first tap region along the first gate electrode. A first body continuous through the bottom and having a first conductivity type;
A second conductive layer formed on the semiconductor substrate, continuously extending from the active region to the second tap region along the second gate electrode and under the sixth insulating film region, and having a first conductivity type; Body,
A semiconductor device comprising:
(Appendix 12)
The lower ends of the first, second, fourth, and fifth insulating film region portions are the lower ends of the central buried insulating film region, the first buried insulating film region, and the second buried insulating film region. The semiconductor device according to appendix 11, wherein the semiconductor device is shallower.
(Appendix 13)
Supplementary note 11 or 12 characterized in that the first and second tap regions have third and fourth buried insulating films formed under the first body and the second body, respectively. The semiconductor device described.
(Appendix 14)
Introducing a first impurity element having a first conductivity type into a semiconductor substrate to a first depth;
Forming an element isolation region on the semiconductor substrate, thereby forming an element region surrounded by the element isolation region;
Removing a part of the semiconductor substrate in the element region to form an insulating film region opening in contact with the element isolation region;
Forming an insulating film region by forming a first insulating film in the opening of the insulating film region, the active region surrounded by the element isolation region and the insulating film region; and the element isolation region and Dividing into a tap region surrounded by the insulating film region and continuous to the active region under the insulating film region;
Forming a gate electrode extending from the active region to the insulating film region on the semiconductor substrate;
Forming first and second side wall insulating films on first and second side wall surfaces of the gate electrode facing each other;
Using the gate electrode and the first and second sidewall insulating films as a mask, a part of the first insulating film in the insulating film region is removed until the semiconductor substrate under the insulating film region is exposed, Forming first and second recesses in the semiconductor substrate in the element region;
Removing the semiconductor substrate exposed in at least the first and second recesses using the gate electrode and the first and second sidewall insulating films as a mask;
Forming a second insulating film in the first and second recesses;
Introducing a second impurity element of a second conductivity type different from the first conductivity type into the active region, and forming a diffusion region across the gate electrode;
Electrically connecting the gate electrode to the tap region;
A method for manufacturing a semiconductor device, comprising:
(Appendix 15)
Injecting a third impurity element having the second conductivity type into the semiconductor substrate to a second depth deeper than the first depth;
15. The method of manufacturing a semiconductor device according to claim 14, wherein lower ends of the first and second recesses are deeper than the first depth and shallower than the second depth.
(Appendix 16)
The step of forming the first and second recesses includes removing the semiconductor substrate in the active region using the gate electrode, the first sidewall insulating film, and the second sidewall insulating film as a mask, Forming the third and fourth recesses,
further,
Forming first and second SiGe mixed crystal layers epitaxially in the third and fourth recesses, respectively;
Epitaxially forming first and second silicon epitaxial layers on the first and second SiGe mixed crystal layers, respectively;
Removing the first and second SiGe mixed crystal layers and forming first and second openings under the first and second silicon epitaxial layers, respectively;
Forming an insulating film in the first and second openings;
Including
16. The semiconductor device according to appendix 14 or 15, wherein the step of forming the diffusion region includes introducing the impurity element of the second conductivity type into the first and second silicon epitaxial layers, respectively. Manufacturing method.
(Appendix 17)
The step of forming the gate electrode includes a step of forming a film serving as a stopper against the etching of the semiconductor substrate on the gate electrode,
17. The supplementary notes 14 to 16, wherein in the step of increasing the depth of the first and second recesses, the etching of the semiconductor substrate is performed using the film as an etching stopper. Semiconductor device manufacturing method.

10 Dt-MOS transistors 11, 21 Silicon substrate 11 C Channel regions 11 D, 21 D _A , 21 D _B drain region 11 J Junction 11 P p-type well 11 S, 21 S _A , 21 S _B source region 12 Gate insulating film 13 Gate electrode 21 A Active region 21 Ex _A , 21Ex _B extension part (21Ex _A ) _A , (21Ex _B ) _A extension part central part (21Ex _A ) _B , (21Ex _A ) _C , (21Ex _B ) _B , (21Ex _B ) _C extension part peripheral part 21I isolation region 21IM, 21IT _A M mask opening 21IT _A, 21IT _B insulating film region _{(21IT A) A, (21IT} B) A dielectric film region central portion _{(21IT A) B, (21IT} A) C, (21IT _{B) B, (21IT B)} C insulating film peripheral portion 21It isolation trench 21M _A , 21M _B mesa structure 21NW n-type well 21N, 23N, 23n silicon nitride film 21Pt recess 21PW p-type well _21S As, _{21S Bs} source silicide region 21SG _E ~21SG _G SiGe mixed crystal layer _21T A, 21T _B tap region 21TR _A ~ 21TR _D, 21TR _E ~21TR _G trench _{21V 1 ~21V 3, 21T A V} , 21T B V voids 21a, 21c source extension regions 21b, 21d drain extension region 21ox, 21Ox, 21Oxd thermal oxide film 21ep ₁ ~21ep ₃ silicon epitaxial layers 22A, 22B a gate insulating film 22Ai, 22Bi gate insulating film extending portion _23G a, 23G _B polysilicon gate electrode 23Na~23Nd temporary gate sidewall insulating film 23O, 23oxd, 3i silicon oxide film _23T A Sc, _23T B Sc shared contact plug 24a~24d gate sidewall insulating film 41 a silicon oxide film 210 element region

Claims (9)

A semiconductor substrate;
An element isolation region formed in the semiconductor substrate;
An element region defined by the element isolation region in the semiconductor substrate;
In the semiconductor substrate, an insulating film region formed continuously with the element isolation region and dividing the element region into an active region and a tap region;
Said the insulating film region is formed continuously with the element isolation region, the lower end of the device isolation region, a first insulating film region portion having a lower end at a shallow position from the surface of the semiconductor substrate,
A second insulating film region portion formed continuously with the element isolation region in the insulating film region and having a lower end at a position shallower than the lower surface of the element isolation region from the surface of the semiconductor substrate;
Wherein the insulating film region, the first insulating film is formed continuously between the region part and said second insulating film region portion, a lower end and a second insulating film region portion of the first insulating film region portion A third insulating film region portion having a lower end at a position shallower than the lower surface of the semiconductor substrate,
A gate electrode formed on the active region and the insulating film region and electrically connected to the tap region;
A first and second sidewall insulating films formed on the first and second sides on the walls opposing the gate electrode,
A body formed on the semiconductor substrate, continuous from the active region along the gate electrode to the tap region through the insulating film region, and having a first conductivity type;
In the active region, the formed across the gate electrode, a semiconductor device which comprises a diffusion region having a second conductivity type opposite to the first conductivity type.   2. The semiconductor device according to claim 1, wherein a lower end of the first insulating film region portion and a lower end of the second insulating film region portion are deeper than the lower end of the diffusion region. A first buried insulating film region and a second buried insulating film region under the diffusion regions of the active region on the first side wall surface side and the second side wall surface side of the gate electrode, respectively. Have
2. The first buried insulating film region and the second buried insulating film region are respectively continuous with the first insulating film region portion and the second insulating film region portion. Or the semiconductor device according to 2; The semiconductor substrate has a well formed under the body and having the second conductivity type,
The well and the body, deeper than the upper end of the upper end and the second buried insulating film region of the first buried insulating film region, a lower end and a second implantation of the first buried insulating film region 4. The semiconductor device according to claim 3, wherein a pn junction is formed at a position shallower than a lower end of the insulating film region.   The semiconductor device according to claim 3, wherein the tap region includes a third buried insulating region under the body. A semiconductor substrate, a step of introducing a first impurity element having a first conductivity type first depth,
Forming an element isolation region on the semiconductor substrate, thereby forming an element region surrounded by the element isolation region;
Removing a part of the semiconductor substrate in the element region to form an insulating film region opening in contact with the element isolation region;
Forming an insulating film region by forming a first insulating film in the opening of the insulating film region, the active region surrounded by the element isolation region and the insulating film region; and the element isolation region and Dividing into a tap region surrounded by the insulating film region and continuous to the active region under the insulating film region;
Forming a gate electrode extending from the active region to the insulating film region on the semiconductor substrate;
Forming first and second side wall insulating films on first and second side wall surfaces of the gate electrode facing each other;
Using the gate electrode and the first and second sidewall insulating films as a mask, a part of the first insulating film in the insulating film region is removed until the semiconductor substrate under the insulating film region is exposed, Forming first and second recesses in the semiconductor substrate in the element region;
Removing the semiconductor substrate exposed in at least the first and second recesses using the gate electrode and the first and second sidewall insulating films as a mask;
Forming a second insulating film in the first and second recesses;
Introducing a second impurity element of a second conductivity type different from the first conductivity type into the active region, and forming a diffusion region across the gate electrode;
Electrically connecting the gate electrode to the tap region;
A method for manufacturing a semiconductor device, comprising: Wherein the semiconductor substrate further includes a step of injecting a third impurity element having the second conductivity type in the first depth deeper second depth,
7. The method of manufacturing a semiconductor device according to claim 6, wherein lower ends of the first and second recesses are deeper than the first depth and shallower than the second depth. The step of forming the first and second recesses includes removing the semiconductor substrate in the active region using the gate electrode, the first sidewall insulating film, and the second sidewall insulating film as a mask, Forming the third and fourth recesses,
further,
Forming first and second SiGe mixed crystal layers epitaxially in the third and fourth recesses, respectively;
Epitaxially forming first and second silicon epitaxial layers on the first and second SiGe mixed crystal layers, respectively;
Removing the first and second SiGe mixed crystal layers and forming first and second openings under the first and second silicon epitaxial layers, respectively;
Forming an insulating film in the first and second openings;
Including
8. The method according to claim 6, wherein the step of forming the diffusion region includes introducing an impurity element of the second conductivity type into the first and second silicon epitaxial layers, respectively. A method for manufacturing a semiconductor device. The step of forming the gate electrode includes a step of forming a film serving as a stopper against the etching of the semiconductor substrate on the gate electrode,
9. The method according to claim 6, wherein in the step of increasing the depth of the first and second recesses, the etching of the semiconductor substrate is performed using the film as an etching stopper. The manufacturing method of the semiconductor device of description.