JP5880862B2 - Control system - Google Patents

Description

  The present invention relates to a control system including a plurality of microcomputers.

  Conventionally, as disclosed in, for example, Patent Document 1, an electronic control device including first and second microcomputers has been proposed. Each microcomputer has a built-in nonvolatile memory capable of rewriting data and a communication circuit connected to a communication line. When each microcomputer receives the write target data addressed to itself via the communication circuit, the microcomputer writes the write target data in the nonvolatile memory and updates the data stored in the nonvolatile memory.

JP 2006-268107 A

  As described above, there has been conventionally described an electronic control device that rewrites data in a nonvolatile memory built in each of a plurality of microcomputers. In such an electronic control device, when updating the data stored in the nonvolatile memory of at least one of the plurality of microcomputers, all the microcomputers start from the normal operation mode in which normal processing is performed. Transition to the rewrite mode for performing the rewrite process. If a communication failure occurs at the time of data rewriting and each microcomputer falls, rewriting remains unfinished in some microcomputers. When the electronic control unit is restarted in this state, some microcomputers start up in the rewrite mode, and other microcomputers start up in the normal operation mode.

  As described above, when the normal process is performed, all the microcomputers are in the normal operation mode, and when the rewrite process is performed, all the microcomputers are in the rewrite mode. Therefore, each microcomputer transmits and receives signals suitable for the same mode. However, as described above, when each microcomputer starts up in a different mode due to a communication failure, each microcomputer does not transmit or receive a signal suitable for its own mode. Therefore, malfunction may occur in each microcomputer.

  In view of the above problems, an object of the present invention is to provide a control system in which malfunctions are prevented from occurring in a microcomputer.

To achieve the above object, the present invention includes a memory (12, 22) in which application software and reprogramming software are stored, a CPU (11, 21) that operates based on the application software or reprogramming software, A control system in which a plurality of microcomputers (10, 20) are provided and each of the plurality of microcomputers is electrically connected, and the CPU of each of the plurality of microcomputers is in an application mode that operates based on application software, Or it has the determination part (30) which determines whether it is the reprogram mode which operate | moves based on reprogramming software, and the determination part determines that all of CPUs of a plurality of microcomputers are application modes. All microcomputer CPUs contain instructions for switching to application mode 1 outputs a control signal, when at least one of the plurality of microcomputers CPU but it is determined that the reprogramming mode, all of the plurality of microcomputers CPU, and outputs a second control signal including an instruction to shift to reprogramming mode In the application mode, the CPU of each of the plurality of microcomputers determines whether or not the communication between the plurality of microcomputers is normal. If the communication is determined to be normal, the CPU maintains the application mode and the communication is not normal. If it is determined, the determination unit determines whether or not the second control signal is input. If it is determined that the second control signal is input, the process proceeds to the reprogress mode and the second control signal is input. If it is determined that it is not, an instruction signal including a reset signal transmission instruction is output to an external device electrically connected to itself .

  Thus, according to the present invention, when the determination unit determines that at least one of the CPUs (11, 21) of the plurality of microcomputers (10, 20) is in the reprogram mode, the plurality of microcomputers (10, 20). The second control signal including an instruction to shift to the reprogress mode is output to all the CPUs (11, 21). According to this, even if there is a microcomputer that has not been reprogrammed due to a communication failure or the like, the CPU (11, 21) of each microcomputer (10, 20) is forcibly shifted to the reprogress mode. Therefore, as a result of the mismatch between the modes of the microcomputers (10, 20), it is possible to prevent a suitable signal from being transmitted / received between the microcomputers (10, 20). As a result, malfunctions in the microcomputers (10, 20) are suppressed.

It is a block diagram which shows schematic structure of the control system which concerns on 1st Embodiment. It is a flowchart for demonstrating the process of a microcomputer. It is a block diagram which shows schematic structure of the control system which concerns on 2nd Embodiment. It is a flowchart for demonstrating the process of a 1st microcomputer. It is a flowchart for demonstrating the process of a 2nd microcomputer. It is a block diagram which shows the modification of a control system.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
Based on FIG.1 and FIG.2, the control system which concerns on this embodiment is demonstrated. As shown in FIG. 1, the control system 100 includes a first microcomputer 10, a second microcomputer 20, and a determination unit 30 as main parts. Each of the microcomputers 10 and 20 and the determination unit 30 are electrically connected, and each of the microcomputers 10 and 20 is electrically connected to an external device such as a rewriting device.

  Each of the microcomputers 10 and 20 is configured to be activated by a signal input from an external device. Specifically, each of the microcomputers 10 and 20 is configured to be activated when the reset signal input from the external device is released. The timing at which the reset signal is released is the same for each of the microcomputers 10 and 20, and each of the microcomputers 10 and 20 is activated simultaneously.

  The first microcomputer 10 has a first CPU 11 and a first memory 12, and the second microcomputer 20 has a second CPU 21 and a second memory 22. Each of the memories 12 and 22 stores application software (hereinafter referred to as an application) and reprogramming software (hereinafter referred to as a replog), and each of the CPUs 11 and 21 operates based on the application or the replog.

  Each of the CPUs 11 and 21 performs normal processing in the case of the application mode that operates based on the application, and stores in the memories 12 and 22 based on the data input from the rewriting device in the case of the reprogram mode that operates based on the reprogramming. The rewriting process of the recorded data is performed. In addition, each of the CPUs 11 and 21 outputs a first mode signal including that it is in the application mode to the determination unit 30 in the application mode, and includes a second information that indicates that it is in the reprogram mode in the reprogress mode. The mode signal is output to the determination unit 30. Each of the CPUs 11 and 21 is forcibly shifted to the application mode when a first control signal to be described later is input from the determination unit 30, and is forced to enter the reprogress mode when a second control signal to be described later is input. To be migrated. Incidentally, the first mode signal according to the present embodiment is a Lo signal having a low voltage level, and the second mode signal is a Hi signal having a voltage level higher than that of the Lo signal.

  The determination unit 30 determines whether each of the CPUs 11 and 21 is in the application mode or the reprogress mode. When the determination unit 30 determines that each of the CPUs 11 and 21 is in the application mode, the determination unit 30 outputs a first control signal including an instruction to shift to the application mode to each of the CPUs 11 and 21, and at least one of the CPUs 11 and 21 is in the reprogram mode. When it is determined that the second control signal is included, the CPU 11 and the CPU 21 output a second control signal including an instruction to shift to the reprogress mode. As described above, each of the CPUs 11 and 21 outputs a mode signal corresponding to each mode to the determination unit 30. When the first mode signal is input from each of the CPUs 11 and 21, the determination unit 30 outputs the first control signal to each of the CPUs 11 and 21. In this way, each of the CPUs 11 and 21 is set to the application mode. In contrast, when the second mode signal is input from at least one of the CPUs 11 and 21, the determination unit 30 outputs a second control signal to each of the CPUs 11 and 21, respectively. By doing so, the determination unit 30 sets each of the CPUs 11 and 21 to the replog mode. The determination unit 30 according to the present embodiment includes an OR, the first control signal is a Lo signal, and the second control signal is a Hi signal.

  Next, the starting operation of the control system 100 according to the present embodiment will be described with reference to FIG. When the reset signals input to the CPUs 11 and 21 are canceled and the CPUs 11 and 21 are activated, the processes shown in FIG. 2 are performed simultaneously.

  First, each of the CPUs 11 and 21 determines whether or not the writing process of the memories 12 and 22 has been completed normally. When each of the CPUs 11 and 21 determines that the writing process in the memories 12 and 22 has not been normally completed, the process proceeds to step S20, and when the CPU 11 and 21 determines that the writing process in the memories 12 and 22 has been normally completed. Control goes to step S40. The above is step S10.

  After shifting to step S20, each of the CPUs 11 and 21 shifts to the reprolog mode. The above is step S20.

  After step S20, each of the CPUs 11 and 21 outputs a second mode signal to the determination unit 30, and performs a rewrite process. The above is step S30.

  In contrast, when the process proceeds to step S40, each of the CPUs 11 and 21 transitions to the application mode. The above is step S40.

  After step S40, each of the CPUs 11 and 21 outputs a first mode signal to the determination unit 30. The above is step S50.

  After step S50, each of the CPUs 11 and 21 determines whether or not the communication between the microcomputers 10 and 20 is normal. When each of the CPUs 11 and 21 determines that communication between the microcomputers 10 and 20 is normal, the CPUs 11 and 21 perform normal processing while maintaining the application mode. On the other hand, if each of the CPUs 11 and 21 determines that the communication between the microcomputers 10 and 20 is not normal, the process proceeds to step S70. The above is step S60.

  In step S <b> 70, each of the CPUs 11 and 21 determines whether or not the second control signal is input from the determination unit 30. When each of the CPUs 11 and 21 determines that the second control signal is input, the CPU 11 and 21 shift to step S20 and shift to the reprogress mode. Then, the rewriting process is performed through step S30 described above. In contrast to this, when each of the CPUs 11 and 21 determines that the second control signal is not input, it determines that a communication failure has occurred and sends an instruction signal including a reset signal transmission instruction to the writing device. Output and perform reset processing.

  Each of the CPUs 11 and 21 determines whether the communication between the microcomputers 10 and 20 is normal and whether or not the second control signal is input when the application mode is entered in step S40. Start doing at the same time. The length of time for determining whether or not communication is normal is longer than the length of time for determining whether or not the second control signal is input. Specifically, the time for determining whether the communication is normal is set to about twice the time for determining whether the second control signal is input. Therefore, after determining whether or not the communication is normal, it is determined whether or not the second control signal is input.

  Next, effects of the control system 100 according to the present embodiment will be described. For example, when the rewriting process is normally completed in the first microcomputer 10 due to a communication failure or the like, but the rewriting is not completed in the second microcomputer 20, the first microcomputer 10, 20 is activated at the first time. A first mode signal is output from the microcomputer 10 and a second mode signal is output from the second microcomputer 20. As a result, the second control signal is input from the determination unit 30 to the CPUs 11 and 21, and the CPUs 11 and 21 enter the reprogress mode. On the contrary, if the rewriting process is not completed in the first microcomputer 10 but the rewriting is normally completed in the second microcomputer 20, the second microcomputer 20 starts the second process from the first microcomputer 10 to the second process. A mode signal is output, and a first mode signal is output from the second microcomputer 20. As a result, the second control signal is input from the determination unit 30 to the CPUs 11 and 21, and the CPUs 11 and 21 enter the reprogress mode.

  According to this, even if each of the first microcomputer 10 and the second microcomputer 20 is activated in different modes due to communication failure, the first microcomputer 10 and the second microcomputer 20 are shifted to the same mode. Therefore, as a result of the mismatch between the modes of the microcomputers 10 and 20, it is possible to suppress the transmission and reception of suitable signals between the microcomputers 10 and 20. For this reason, it is suppressed that malfunction occurs in each of the microcomputers 10 and 20.

  Incidentally, when the rewriting process is normally completed in each of the microcomputers 10 and 20, the first mode signal is output from each of the microcomputers 10 and 20 when the microcomputers 10 and 20 are activated. Therefore, the first control signal is input from the determination unit 30 to the CPUs 11 and 21, and each of the CPUs 11 and 21 shifts to the application mode. On the other hand, when the rewriting process is not completed in each of the microcomputers 10 and 20, the second mode signal is output from each of the microcomputers 10 and 20 when the microcomputers 10 and 20 are activated. Therefore, the second control signal is input from the determination unit 30 to the CPUs 11 and 21, and each of the CPUs 11 and 21 shifts to the reprogress mode.

  As described above, the first microcomputer 10 and the second microcomputer 20 are shifted to the same mode regardless of which mode is activated. Therefore, as a result of the mismatch between the modes of the microcomputers 10 and 20, it is possible to suppress the transmission and reception of suitable signals between the microcomputers 10 and 20. For this reason, it is suppressed that malfunction occurs in each of the microcomputers 10 and 20.

  Each of the CPUs 11 and 21 performs the process shown in FIG. According to this, compared with the configuration in which each of the CPUs 11 and 21 performs different processes, the time for creating a program for performing the processes is shortened.

  When a communication failure occurs, there is a possibility that a microcomputer in which reprogramming is not completed may occur. Therefore, in this embodiment, each of the CPUs 11 and 21 determines whether or not the communication between the microcomputers 10 and 20 is normal. In this way, it is determined whether or not a microcomputer for which reprogramming has not been completed has occurred.

  Each of the CPUs 11 and 21 starts to simultaneously determine whether or not the communication between the microcomputers 10 and 20 is normal and whether or not the second control signal is input. The length of time for determining whether the communication is normal is longer than the length of time for determining whether the second control signal is input. According to this, unlike the configuration in which the length of time for determining whether or not the communication is normal is shorter than the length of time for determining whether or not the second control signal is input, It is possible to suppress a malfunction of determining whether or not the second control signal is input before determining whether or not the communication is normal.

(Second Embodiment)
Next, 2nd Embodiment of this invention is described based on FIGS. Since the control system 100 according to the second embodiment is often in common with the control system 100 according to the first embodiment, the detailed description of the common parts will be omitted below, and different parts will be described mainly. In addition, the same code | symbol is provided to the element same as the element shown in 1st Embodiment.

  In the first embodiment, each of the microcomputers 10 and 20 is configured to be activated by canceling an input of a reset signal input from an external device. An example in which each of the 20 is simultaneous is shown. On the other hand, in the present embodiment, the first microcomputer 10 is activated by releasing the input of the reset signal input from the external device, whereas the second microcomputer 20 is activated by the first microcomputer 10. It is characterized in that it is activated by canceling the input of the reset signal input from. Therefore, unlike the first embodiment, in the present embodiment, after the first microcomputer 10 is activated, the second microcomputer 20 is activated.

  Further, in the present embodiment, the first microcomputer 10 activates the second microcomputer 20 after it operates based on an application or a reprogram. Then, as shown in FIG. 5, the second microcomputer 20 first determines whether or not the second control signal is input from the determination unit 30 after being activated (step S <b> 90). When determining that the second control signal is input, the second CPU 21 proceeds to step S20 and transitions to the reprogress mode. Then, the rewriting process is performed through step S30 described above. Further, when the second CPU 21 determines that the second control signal is not input, the second CPU 21 performs the processes of steps S10 to S70 in the same manner as in the first embodiment.

  According to this, when the second microcomputer starts up, the second CPU determines whether or not the reprogram rewriting process has been completed, and then determines whether or not the second control signal is input from the determination unit. The time for determining whether the second CPU 21 operates based on the app or whether it operates based on the reprogram is shortened. As a result, it is possible to prevent the second CPU 21 from malfunctioning due to disturbance noise.

  In the first embodiment, each of the CPUs 11 and 21 determines whether or not the communication between the microcomputers 10 and 20 is normal and whether or not the second control signal is input when the mode is changed to the application mode in step S40. Start making judgments at the same time. In the example, the length of time for determining whether the communication is normal is longer than the length of time for determining whether the second control signal is input. On the other hand, in this embodiment, when the first CPU 11 shifts to the application mode in step S40, it is determined whether or not the communication between the microcomputers 10 and 20 is normal and whether the second control signal is input. Start to make the same judgment. Then, after the first CPU 11 outputs the first mode signal in step S50, the first CPU 11 determines whether the time required for determining whether the communication is normal and whether the second control signal is input. The system waits for a standby time longer than the time required for (step S80 shown in FIG. 4 is performed). After the standby time has elapsed, the first CPU 11 proceeds to step S60 and performs a process of determining whether or not the communication between the microcomputers 10 and 20 is normal.

  According to this, it is possible to prevent the first CPU 11 from malfunctioning to determine whether or not the second control signal is input before determining whether or not the communication is normal.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  In each embodiment, the example in which each of the microcomputers 10 and 20 is electrically connected to an external device is shown. However, as shown in FIG. 6, a configuration in which only the first microcomputer 10 is electrically connected to an external device may be employed.

  In the present embodiment, an example in which the first mode signal is the Lo signal and the second mode signal is the Hi signal is shown. However, the first mode signal may be a Hi signal and the second mode signal may be a Lo signal.

  In the present embodiment, an example in which the first control signal is the Lo signal and the second control signal is the Hi signal has been described. However, the first control signal may be a Hi signal and the second control signal may be a Lo signal.

  In each embodiment, the determination part 30 showed the example containing OR. However, as illustrated in FIG. 6, a configuration in which the determination unit 30 includes NOR can be employed. Although not shown, the determination unit 30 may employ a configuration including NAND or AND.

  Incidentally, when the determination unit 30 includes NOR, the first mode signal is the Lo signal, the second mode signal is the Hi signal, the first control signal is the Hi signal, and the second control signal is the Lo signal. When the determination unit 30 includes a NAND, the first mode signal is a Hi signal, the second mode signal is a Lo signal, the first control signal is a Lo signal, and the second control signal is a Hi signal. When the determination unit 30 includes AND, the first mode signal is the Hi signal, the second mode signal is the Lo signal, the first control signal is the Hi signal, and the second control signal is the Lo signal.

10 ... 1st microcomputer 11 ... 1st CPU
12 ... 1st memory 20 ... 2nd microcomputer 21 ... 2nd CPU
22 ... Second memory 30 ... Determination unit 100 ... Control system

Claims (5)

A plurality of microcomputers (10, 20) having memories (12, 22) storing application software and reprogramming software and CPUs (11, 21) operating based on the application software or the reprogramming software are provided. A control system in which each of the plurality of microcomputers is electrically connected,
A determination unit (30) for determining whether a CPU of each of the plurality of microcomputers is in an application mode that operates based on the application software or a reprogram mode that operates based on the reprogramming software; ,
The determination unit
When it is determined that all of the CPUs of the plurality of microcomputers are in the application mode, a first control signal including an instruction to shift to the application mode is output to all of the CPUs of the plurality of microcomputers,
If it is determined that at least one of the CPUs of the plurality of microcomputers is in the reprolog mode, a second control signal including an instruction to shift to the reprolog mode is output to all of the CPUs of the plurality of microcomputers ;
The CPU of each of the plurality of microcomputers is
In the case of the application mode, it is determined whether communication between the plurality of microcomputers is normal,
If it is determined that the communication is normal, the application mode is maintained,
When it is determined that the communication is not normal, the determination unit determines whether the second control signal is input,
When it is determined that the second control signal is input, the mode is shifted to the reprogress mode,
When it is determined that the second control signal is not input , the control system outputs an instruction signal including a reset signal transmission instruction to an external device electrically connected to the second control signal . The CPU of each of the plurality of microcomputers outputs a first mode signal to the determination unit in the application mode, and outputs a second mode signal to the determination unit in the reprogress mode,
When the first mode signal is input from all of the CPUs of the plurality of microcomputers, the determination unit outputs the first control signal to all of the CPUs of the plurality of microcomputers. 2. The control system according to claim 1, wherein when the second mode signal is input from at least one of the second control signal, the second control signal is output to all of the CPUs of the plurality of microcomputers. One of the first mode signal and the second mode signal is a Hi signal,
The other of the first mode signal and the second mode signal is a Lo signal having a lower voltage level than the Hi signal.
One of the first control signal and the second control signal is the Hi signal,
The control system according to claim 2, wherein the other of the first control signal and the second control signal is the Lo signal. The CPU determines whether or not communication between the plurality of microcomputers has elapsed after the time required to determine whether the communication is normal and the time required to determine whether the second control signal is input. The control system according to claim 1 , wherein a process for determining whether or not the communication is normal is performed . The activation of the second microcomputer (20) is controlled by the first microcomputer (10) which is one of the plurality of microcomputers,
The CPU (11) of the first microcomputer activates the second microcomputer after operating in the application mode or the reprolog mode,
CPU (21) of the second microcomputer, after started, claims 1 to 4, wherein the first control signal or the second control signal from said decision unit is characterized in that determining whether the inputted The control system according to any one of the above.

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