JP5882363B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a termination structure of a semiconductor element and a technique for forming an alignment mark.

  Semiconductor elements using silicon carbide (SiC) are promising as next-generation switching elements that can achieve high breakdown voltage, low loss, and high heat resistance, and are expected to be applied to power semiconductor devices such as inverters. However, many problems to be solved remain in the SiC semiconductor device. One of them is an electric field in a terminal portion (for example, an end portion of a Schottky electrode of a Schottky barrier diode or an end portion of a pn junction of a pn diode or MOSFET (Metal Oxide Semiconductor Field Effect Transistor)) that is an outer peripheral portion of the semiconductor element. This is a problem that the withstand voltage characteristic of the semiconductor device deteriorates due to concentration.

  Typical examples of the termination structure for relaxing the electric field generated at the termination portion of the semiconductor element include a guard ring structure, a JTE (Junction Termination Extension) structure, and an FLR (Field Limiting Ring) structure (for example, Patent Documents 1 and 2). . These are impurity regions formed so as to surround the semiconductor element. In general, the JTE structure is provided for the purpose of reducing the surface electric field, and has a structure in which the impurity concentration gradually decreases from the terminal portion of the semiconductor element to the outside. On the other hand, the FLR structure is composed of a plurality of impurity regions having the same concentration.

  For example, Patent Document 1 below discloses a termination structure that combines a guard ring and JTE. The termination structure of Patent Document 1 is a structure in which a JTE having a lower impurity concentration than the guard ring is disposed outside the guard ring. Further, in Patent Document 1, the guard ring and the JTE are formed under the recess provided on the surface of the semiconductor layer, thereby increasing the distance between the bottom end of the guard ring and the JTE where the electric field concentration is likely to occur and the surface of the semiconductor layer. A technique for further relaxing the electric field on the surface of the semiconductor layer has been proposed.

  Patent Documents 3 to 5 disclose techniques for determining the depth of an alignment mark used for alignment of a semiconductor wafer according to the wavelength of the detection light of the alignment mark.

International Publication No. 2009/116444 JP 2010-68008 A JP-A-7-283103 JP-A-8-64500 JP-A-63-153818

  In general, impurities implanted into silicon (Si) diffuse to some extent, but impurities implanted into SiC hardly diffuse. Therefore, when an impurity region (hereinafter referred to as “termination region”) such as a guard ring or JTE of an SiC semiconductor device is formed under the recess as in Patent Document 1, a termination region having a high impurity concentration is formed in the very vicinity of the bottom of the recess. Is done. When the impurity concentration in the termination region is high, the depletion layer extends little when a high voltage is applied, and a high electric field is generated in the termination region. In particular, electric field concentration is likely to occur at the bottom end of the recess on the termination region, which causes dielectric breakdown at that portion.

  As a countermeasure, in the termination structure of Patent Document 1, the termination region is formed so as to extend to the outer edge of the recess above it (that is, the width of each termination region is wider than the width of the recess above it). As a result, the longitudinal cross-sectional area of the termination region is increased, and the electric field concentration at the bottom end of the recess is alleviated. However, in order to form the termination region wider than the recess, an etching mask (etching mask) for forming the recess and an ion implantation mask (implantation mask) for forming the termination region are separately prepared. Since the manufacturing process is complicated, the manufacturing time is prolonged and the cost is increased.

  Therefore, in the SiC semiconductor device, from the viewpoint of achieving both simplification of the manufacturing process and high withstand voltage of the termination region, a termination structure having no recess and a flat top surface may be preferable as in Patent Document 2. However, since it is necessary to directly form a recess alignment mark for alignment of each implantation mask on the substrate in the manufacture of the SiC semiconductor, the conventional manufacturing method uses a termination structure with a flat upper surface. In addition to the implantation mask for forming the termination region, an etching mask for forming the alignment mark is required.

  Conventionally, the depth of the recess-shaped alignment mark is not optimized, and when the refractive index of the film covering the alignment mark changes during the manufacturing process, the intensity of the diffracted light for detecting the alignment mark changes greatly. In that case, the positioning accuracy of the mask using the alignment mark is lowered, and the overlay error may be increased. As a result, there arises a problem that the manufacturing yield of the semiconductor device is lowered.

  The present invention has been made to solve the above-described problems, and is capable of reducing the number of masks during manufacturing and improving the detection accuracy of alignment marks while suppressing a decrease in breakdown voltage of the termination region. An object is to provide a semiconductor device.

In the method for manufacturing a silicon carbide semiconductor device according to the present invention , (a) a resist pattern having a first opening and a second opening is formed on a silicon carbide semiconductor layer on a region serving as a terminal portion of a semiconductor element. And (b) forming a recess having a depth of 50 nm or less into the silicon carbide semiconductor layer under the first opening by etching using the resist pattern as a mask, and silicon carbide under the second opening. A step of forming alignment marks each having a depth of 50 nm or less in the semiconductor layer; and (c) after the step (b), impurities are ion-implanted using the resist pattern as a mask, so that a termination region is formed under the recess. And (d) irradiating the silicon carbide semiconductor layer with mark detection irradiation light, and the mark detection irradiation light is reflected at an edge portion of the alignment mark. Detecting the alignment mark by detecting diffracted light for mark detection that is incident light and enters a specific optical path different from the direction of reflected light other than the edge portion, and includes the step (d ), The maximum value of the refractive index of the film formed on the alignment mark is n _max , and the wavelength of the mark detection irradiation light irradiated to the silicon carbide semiconductor layer for detection of the alignment mark is λ Then, the depth of the alignment mark is λ / n _max / 6 or less.

  The recess formed on the termination region of the silicon carbide semiconductor device according to the present invention can be formed simultaneously with the alignment mark. In other words, since the termination region pattern and the alignment mark pattern can be formed simultaneously using the same mask, the number of masks required can be reduced as compared with the prior art, and the manufacturing cost can be reduced. Further, by setting the depth of the recess on the termination region to 50 nm or less, the step on the upper surface of the termination region is reduced, so that electric field concentration at the bottom surface of the recess in the termination region is suppressed, and the breakdown voltage of the termination region is increased. Can be planned.

  The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

It is a figure which shows the structure of the termination | terminus structure and alignment mark of the semiconductor device which concerns on Embodiment 1 of this invention. It is a manufacturing process figure (resist pattern formation process) of the semiconductor device which concerns on Embodiment 1 of this invention. It is a manufacturing process figure (SiC etching process) of the semiconductor device concerning Embodiment 1 of the present invention. It is a manufacturing process figure (ion implantation process) of the semiconductor device concerning Embodiment 1 of the present invention. It is a manufacturing process figure (resist removal and high temperature annealing process) of the semiconductor device concerning Embodiment 1 of the present invention. It is a graph which shows the relationship between the depth of the recess on a termination area | region, and the electric field strength in the bottom part of this recess. It is an expanded sectional view of the edge part of an alignment mark. It is a graph which shows the relationship between the mark level | step difference (0-500 nm) and the normalized intensity | strength of the diffracted light from the upper part and lower part of the edge of an alignment mark. It is a graph which shows the relationship between mark level | step difference (0-100 nm) and the normalized intensity | strength of the diffracted light from the upper part and lower part of the edge of an alignment mark. It is a figure which shows the experimental result which changes the depth of an alignment mark and confirms the detection possibility of the said alignment mark. It is a figure which shows the relationship between the depth of the recess on a termination area | region, and the ratio of each destruction factor of a semiconductor device. It is a figure which shows the structure of the termination | terminus structure and alignment mark of the semiconductor device which concerns on Embodiment 2 of this invention. It is a manufacturing-process figure (resist pattern formation process) of the semiconductor device which concerns on Embodiment 2 of this invention. It is a manufacturing-process figure (SiC etching process) of the semiconductor device which concerns on Embodiment 2 of this invention. It is a manufacturing-process figure (ion implantation process) of the semiconductor device which concerns on Embodiment 2 of this invention. It is a manufacturing-process figure (resist removal and high temperature annealing process) of the semiconductor device which concerns on Embodiment 2 of this invention.

<Embodiment 1>
FIG. 1 is a diagram showing the termination structure and alignment mark configuration of the semiconductor device according to the first embodiment of the present invention. Here, as an example, a configuration is shown in which a guard ring is provided as a termination region on the outer periphery of a Schottky barrier diode formed using a silicon carbide (SiC) semiconductor.

  The semiconductor device is formed using an epitaxial substrate including an n-type SiC substrate 1 and an n-type SiC epitaxial layer 2 grown on the upper surface (first main surface) of the SiC substrate 1. A surface electrode 4 is disposed on the upper surface of the SiC epitaxial layer 2 via a Schottky electrode 3 that is in Schottky connection with the SiC epitaxial layer 2. The upper surface of the semiconductor device is covered with a surface protective film 7 such as polyimide. However, since the surface electrode 4 functions as a pad electrode for connecting the wiring, a portion of the surface protective film 7 on the surface electrode 4 is removed. Yes. A back electrode 6 is disposed on the lower surface (second main surface) of SiC substrate 1 via ohmic electrode 5 that is in ohmic contact with SiC substrate 1.

  A termination region 8 (guard ring), which is a p-type impurity region 8a, is formed in a region including the lower portion of the Schottky electrode 3 on the upper surface portion of the SiC epitaxial layer 2 in order to ensure a horizontal breakdown voltage. .

  In addition, recess-like alignment marks 9 used for alignment of various masks are formed on the upper surface of the SiC epitaxial layer 2.

As shown in FIG. 1, a recess 10 is formed on the upper surface of the termination region 8. Since the recess 10 is formed simultaneously with the alignment mark 9, the alignment mark 9 and the recess 10 have substantially the same depth. The alignment mark 9 and the recess 10 are formed very shallowly, and the depths thereof are 50 nm or less and λ / n _max / 6 or less (n _max is a resist formed on the SiC epitaxial layer 2 in the manufacturing process). The maximum refractive index of the film such as λ is the wavelength of the detection light of the alignment mark 9).

  Although details will be described later, when the alignment mark 9 and the recess 10 are shallow enough to satisfy the above conditions, the alignment mark 9 always obtains strong mark detection diffracted light when detecting the alignment mark 9. Detection accuracy is improved. Further, in the termination region 8, the electric field strength at the bottom surface of the recess 10 is suppressed to a level close to the case where there is no recess 10. That is, it is possible to improve both the alignment accuracy of the mask by improving the detection accuracy of the alignment mark 9 and to improve the breakdown voltage by suppressing the electric field concentration in the termination region 8.

  2 to 5 are process diagrams showing a Schottky barrier diode shown in FIG. 1, its termination structure, and a method of forming an alignment mark. Hereinafter, based on these drawings, a method for manufacturing the semiconductor device according to the first embodiment will be described.

First, an n-type SiC substrate 1 is prepared, and an n-type SiC epitaxial layer 2 is grown thereon. As the SiC substrate 1, for example, a substrate having a polytype of 4H and having an upper surface (first main surface) inclined by a certain off angle from the plane orientation (0001) can be used. The SiC epitaxial layer 2 has a doping concentration of 1 to 20 × 10 ¹⁵ / cm ³ and a film thickness of about ³ to 50 μm. The n-type impurity introduced into the SiC substrate 1 and the SiC epitaxial layer 2 is, for example, nitrogen (N).

  After forming an oxide film (not shown) on the SiC epitaxial layer 2, a transfer process of a resist pattern 11 that also serves as an implantation mask for forming the termination region 8 and an etching mask for forming the alignment mark 9 is performed. (FIG. 2). That is, the resist pattern 11 has an opening 12b (first opening) located on the formation region of the termination region 8 and an opening 12a (second opening) located on the formation region of the alignment mark 9. It has a shape to have.

  Next, a recess-shaped alignment mark 9 is formed in the SiC epitaxial layer 2 under the opening 12a by etching using the resist pattern 11 as a mask (FIG. 3). At this time, the portion of the SiC epitaxial layer 2 exposed in the opening 12b (formation region of the termination region 8) is also etched, so that the recess 10 is formed simultaneously with the alignment mark 9, as shown in FIG. At this time, the alignment mark 9 and the recess 10 are formed extremely shallow.

  If there is a deep recess (high step) on the upper surface of the termination region, electric field concentration tends to occur at the step portion (bottom end portion of the recess), which can cause a breakdown voltage to deteriorate. In particular, the SiC semiconductor has a breakdown voltage about 10 times higher than that of the Si semiconductor due to its material characteristics, and it is difficult for impurities to diffuse, and the impurity concentration in the upper surface portion of the termination region becomes high. . In the present embodiment, the problem is avoided by making the recess 10 located on the termination region 8 very shallow.

  After the alignment mark 9 and the recess 10 are formed, a p-type impurity is ion-implanted using the remaining resist pattern 11 as a mask, thereby forming an impurity region 8a serving as a termination region 8 in the upper surface portion of the SiC epitaxial layer 2. (FIG. 4). At this time, since the p-type impurity is ion-implanted into the SiC epitaxial layer 2 exposed at the openings 12a and 12b, an impurity region 8a similar to the termination region 8 is formed at the bottom of the alignment mark 9. An example of the p-type impurity is aluminum (Al).

  Subsequently, the resist pattern 11 is removed, and the SiC substrate 1 and the SiC epitaxial layer 2 are heated to a temperature of 1500 ° C. or higher in order to activate the p-type impurity introduced into the termination region 8 (FIG. 5).

  Thereafter, an ohmic electrode 5 of silicide (eg, NiSi) is formed by forming a metal film such as nickel (Ni) on the lower surface (back surface) of the SiC substrate 1 and performing annealing. Further, the back electrode 6 is formed on the ohmic electrode 5. As the back electrode 6, for example, a two-layer structure of a Ni layer and an Au layer can be used. In this case, when the back surface of the semiconductor device is die-bonded using solder, the wettability of the solder is improved.

  Further, a Schottky electrode 3 is formed by forming a metal film such as titanium (Ti) on the upper surface of the SiC substrate 1. Further, a surface film 4 is formed on the Schottky electrode 3 by forming a metal film such as aluminum thereon. Then, a surface protective film 7 is formed on the SiC epitaxial layer 2 and the surface electrode 4 by applying and baking a surface sealing material such as polyimide.

  Through the above steps, the Schottky barrier diode shown in FIG. 1, the termination region 8 having the recess 10 on the upper surface, and the recess-shaped alignment mark 9 are formed.

  Here, the recess 10 and the alignment mark 9 on the upper surface of the termination region 8 in the semiconductor device of the first embodiment are characterized in that the depth is very shallow. Hereinafter, the depth (height of the step) of the recess 10 and the alignment mark 9 will be described.

  First, the depth of the recess 10 on the termination region 8 will be described. As described above, the greater the depth (step) of the recess on the termination region, the higher the electric field strength at the bottom of the recess, and the breakdown voltage of the termination region tends to deteriorate due to electric field concentration at the bottom end of the recess. In particular, the SiC semiconductor is less likely to diffuse impurities, and the impurity concentration in the vicinity of the bottom of the termination region becomes high, and this tendency becomes remarkable.

  The inventor has verified the relationship between the depth of the recess on the termination region and the electric field strength at the bottom of the recess by experiments. FIG. 6 is a graph showing the simulation results, and is a graph showing the relationship between the depth of the recess formed on the termination region and the electric field strength at the bottom of the recess. In FIG. 6, the electric field strength at the bottom of the recess increases as the depth of the recess increases. On the other hand, when the depth of the recess on the termination region is 50 nm or less, the electric field strength is significantly reduced and there is no recess. It turned out to be very close to this state.

  Therefore, if the depth of the recess 10 on the termination region 8 is set to 50 nm or less as in the present embodiment, the electric field strength at the bottom of the recess 10 can be suppressed, and the electric field concentration at the bottom end is reduced. Thus, it is possible to make the state close to a state without a recess. Thereby, it is possible to increase the breakdown voltage of the terminal portion of the semiconductor element. This is particularly effective for a SiC semiconductor device in which the impurity concentration near the bottom of the termination region 8 tends to be high.

  Since the electric field distribution at the termination does not depend so much on the breakdown voltage of the semiconductor element itself, this effect has a wide breakdown voltage range from, for example, a low breakdown voltage semiconductor device of several hundred volts to a high breakdown voltage semiconductor device of 3000 V or higher. It can be obtained in a semiconductor device.

  Next, the depth of the alignment mark 9 will be described. In general, a stepper is used in an exposure process for manufacturing a semiconductor device. An alignment mark used in a stepper has a configuration in which a plurality of rectangular patterns are arranged as disclosed in, for example, Japanese Patent Publication No. 6-72766. In this case, the alignment mark is detected by detecting light on which diffracted light from the plurality of rectangular patterns is superimposed.

  FIG. 7 is an enlarged cross-sectional view of an edge portion of one alignment mark 9. When detecting the position of the alignment mark 9, the upper surface of the SiC epitaxial layer 2 is irradiated with laser light for mark detection (irradiation light for mark detection).

  As shown in FIG. 7, it is assumed that the mark detection irradiation light 40 enters the alignment mark 9 from a direction perpendicular to the upper surface of the SiC epitaxial layer 2. Most of the mark detection irradiation light 40 that reaches the SiC epitaxial layer 2 becomes reflected light 41, but part of it is reflected by the edge portion of the alignment mark 9 to become diffracted light 41 a. Further, a part of the diffracted light 41 a becomes mark detecting diffracted light 41 b that enters an optical path for detecting the position of the alignment mark 9.

A mark detecting diffracted light 41b ₁ diffracted by the upper edge of the alignment mark 9, since the mark detecting diffracted light 41b ₁ diffracted by the lower interfere, as a result, the diffracted light 41b for mark detection containing them Is determined by the phase difference between the mark detection diffracted lights 41b ₁ and 41b ₂ . Since the phase difference between the two mark detection diffracted lights 41b ₁ and 41b ₂ depends on the path difference between the two, the intensity of the mark detection diffracted light 41b is determined by the step of the edge of the alignment mark 9.

FIG. 8 shows the normalized etching depth (alignment mark step) of the alignment mark 9 formed on the upper surface of the SiC epitaxial layer 2 and the mark detection diffracted light 41b by the mark detection diffracted lights 41b ₁ and 41b ₂ . It is a graph which shows the relationship with light intensity (normalized light intensity). The solid line graph shown in FIG. 8 shows the case where the alignment mark 9 is covered with a resist having a refractive index of 1.6, and the broken line graph shows the alignment mark 9 covered with polysilicon having a refractive index of 4. The case where it is broken is shown. In both cases, the wavelength of the mark detection irradiation light 40 is 633 nm.

As can be seen from FIG. 8, the step of the alignment mark 9 for the normalized light intensity of the mark detection diffracted light 41 b to approach 1 differs depending on the material of the film covering the alignment mark 9. In the example shown in FIG. 8, when the step of the alignment mark 9 is near 0 nm or 400 nm, the mark detection diffracted light 41b becomes strong regardless of whether the alignment mark 9 is covered with resist or polysilicon. In particular, when the step of the alignment mark 9 is 50 nm or less, preferably 20 nm or less, the path difference between the mark detection diffracted lights 41b ₁ and 41b ₂ is small, so the alignment mark 9 is covered with any film other than resist or polysilicon. Even if it is broken, the mark detection diffracted light 41b becomes strong.

FIG. 9 is a graph corresponding to a portion where the alignment mark step in the graph of FIG. 8 is 0 to 100 nm. The light intensity of the mark detection diffracted light 41b is stronger than when there is no interference when the normalized light intensity is 0.25 or more. When the alignment mark 9 is covered with a resist having a refractive index of 1.6, the normalized light intensity of the mark detection diffracted light 41b becomes 0.25 or more due to interference of the mark detection diffracted lights 41b ₁ and 41b _2. This is when the depth of the alignment mark 9 is about 50 nm or less. When the alignment mark 9 is covered with a polysilicon film having a refractive index of 4, the normalized light intensity of the mark detection diffracted light 41b is 0.25 or more because the depth of the alignment mark 9 is about 20 nm. When:

Further, when the step edge of the alignment mark 9 is deep, or stepped reversed tapered shape by etching, by Dari recessed shape under step, alignment marks for mark detection diffracted light 41b ₂ from the bottom of the step 9 may not be used for detection. In such a case, interference of the mark detection diffracted lights 41b ₁ and 41b ₂ from the upper and lower portions of the step does not occur, the light intensity for detecting the alignment mark 9 decreases, and the alignment accuracy deteriorates. To do.

Therefore, when the step of the edge of the alignment mark 9 is made extremely shallow as in the present embodiment, a strong mark detection diffracted light 41b can be obtained regardless of the material of the film covering the alignment mark 9. Specifically, the maximum value of the refractive index of a film (for example, a resist, an oxide film, polysilicon, or the like) formed on the alignment mark 9 during the process of detecting the alignment mark 9 in the manufacture of the semiconductor device is represented by n _max. Assuming that the wavelength of the mark detection irradiation light 40 is λ, if the depth (step) of the alignment mark 9 is λ / n _max / 6 or less, the alignment mark 9 is covered with any of these films. since below retardation lambda / 3 mark detecting diffraction light _41b 1, 41b _2, the mark detecting diffracted light _41b 1, 41b ₂ will be mutually reinforce each other, always be obtained strong mark detecting diffracted light 41b Can do. As a result, misalignment of the mask can be prevented and the yield can be improved.

Normally, the detection process of the alignment mark 9 in the manufacture of semiconductor devices is performed a plurality of times, there is a case where the film where the step is formed on the alignment mark 9 each time carried out are different, the above n _max is The maximum value through these multiple detection steps.

In addition, if the step of the edge of the alignment mark 9 is smaller than the surface roughness (about 5 nm) in the flat portion of the SiC epitaxial layer 2, the alignment mark 9 cannot be distinguished from other portions. It must be larger than the surface roughness of the epitaxial layer 2. That is, the depth of the alignment mark 9 of the present embodiment is preferably larger than the surface roughness (5 nm) of the SiC epitaxial layer 2 on which it is formed and λ / n _max / 6 or less.

Thus, the depth of the recess 10 on the termination region 8 is preferably 50 nm or less from the viewpoint of ensuring the breakdown voltage of the termination region 8, and the depth of the alignment mark 9 is from the viewpoint of ensuring the detection accuracy of the alignment mark 9. From this, it can be seen that it is preferably λ / n _max / 6 or less. In the present embodiment, in order to ensure both the breakdown voltage of the termination region 8 and the detection accuracy of the alignment mark 9, the depths of the termination region 8 and the alignment mark 9 are 50 nm or less and λ / n _max / 6 or less. It is said.

  As described above, according to the first embodiment, since the recess 10 on the termination region 8 is extremely shallow, electric field concentration in the termination region 8 can be suppressed, and a high breakdown voltage termination structure can be obtained. Further, since the implantation mask for forming the termination region 8 and the etching mask for forming the alignment mark 9 are realized by the same resist pattern 11, the number of necessary masks can be reduced and the manufacturing cost can be reduced. Can contribute to the reduction. Furthermore, since the alignment mark 9 is also formed to be extremely shallow, even if the film covering the alignment mark 9 changes during the manufacturing process of the semiconductor device, the intensity of the mark detection diffracted light 41b can be maintained high, and the mask can be formed multiple times. The alignment can always be made good, and the yield in manufacturing the SiC semiconductor device is improved.

  Since the resist is basically exposed with g-rays (wavelength 436 nm) and i-rays (wavelength 365 nm) in the ultraviolet region, the wavelength of the detection light (mark detection irradiation light) of the alignment mark 9 may cause the resist to be exposed. It is desirable that the red or infrared region on the long-wavelength side without any light is present, and a He—Ne laser (wavelength 633 nm) is generally used. In the above description, it is assumed that the wavelength of the detection light of the alignment mark 9 is 633 nm. However, the mark detection irradiation light applicable to the present invention is not limited to this, and there is no problem even if a red or infrared semiconductor laser (wavelength 650 nm or 780 nm) is used.

  Here, the experimental result regarding the depth of the alignment mark 9 and the recess 10 is shown. FIG. 10 is a diagram illustrating a result of an alignment mark detection experiment performed by changing the depth of the alignment mark 9. In this experiment, the depth of the alignment mark 9 was changed in the range of 20 nm to 80 nm, and whether or not the alignment mark 9 could be detected in each case was confirmed.

  In general, a semiconductor device manufacturing process includes a process in which an alignment mark is covered with a resist and a process in which the alignment mark is covered with a metal film. In this experiment, by simulating the manufacturing process of such a semiconductor device, (1) when no film is formed on the alignment mark 9, (2) a resist having a thickness of 2.3 μm is formed on the alignment mark 9. When formed, (3) When Ti having a thickness of 200 nm is formed on the alignment mark 9, (4) Ti having a thickness of 200 nm and a resist having a thickness of 2.3 μm are superimposed on the alignment mark 9. Whether or not the alignment mark 9 can be detected was confirmed for the four types of structures formed.

  As shown in FIG. 10, even when the depth of the alignment mark 9 was reduced to 20 nm, the alignment mark 9 could be detected in all the four types of structures. This is presumably because even if the alignment mark 9 is shallow, the intensity of the diffracted light received by the optical system for detecting the alignment mark 9 does not decrease but rather increases.

  FIG. 11 is a result of an experiment in which the depth of the recess on the termination region is changed and the breakdown factor of the semiconductor device is examined in each case. The relationship between the depth of the recess on the termination region and the ratio of each breakdown factor of the semiconductor device is shown. Showing the relationship. The cause of the breakdown that occurs when a high voltage is applied to the SiC semiconductor device is mainly due to various defects such as carrot defects and triangular defects included in the SiC epitaxial layer, in addition to the breakdown due to the electric field concentration at the terminal portion. There are destruction and destruction caused by foreign matters generated during the manufacturing process.

  In this experiment, the reverse IV (current-voltage) characteristics of a silicon carbide Schottky barrier diode (SiC-SBD) according to the present invention in which the depth of the recess 10 on the termination region 8 is 20 nm are examined. Was done. For comparison, the same characteristics were also examined for SiC-SBD having no recess 10 on the termination region 8 and SiC-SBD having a depth of the recess 10 on the termination region 8 of 300 nm or more.

  As shown in FIG. 11, in the SiC-SBD in which the depth of the recess 10 is deepened to 300 nm or more, there are about 30% of the breakdown due to the electric field concentration in the terminal portion. However, none of the SiC-SBD having the recess 10 and the SiC-SBD having the recess 10 having a depth of 20 nm were destroyed due to the same cause. From this result, it is confirmed that when the depth of the recess 10 on the termination region 8 is reduced as in the present invention, the electric field distribution in the termination region 8 is close to the state without the recess 10 and the termination portion has a high breakdown voltage. It was done.

<Embodiment 2>
FIG. 12 is a diagram showing the structure of the termination structure and alignment mark of the semiconductor device according to the second embodiment of the present invention. Here, as an example, a configuration in which a guard ring is provided as a termination region on the outer periphery of a Schottky barrier diode formed using a silicon carbide (SiC) semiconductor is shown. In FIG. 12, elements having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted here.

  The configuration of the semiconductor device according to the second embodiment is almost the same as that of the first embodiment (FIG. 1), but the edge portions of the recess 10 and the alignment mark 9 on the termination region 8 are more gradual than in the first embodiment. It is a gentle slope. That is, the recess 10 and the alignment mark 9 have a tapered shape (forward tapered shape) whose bottom is narrower than the top. Further, the termination region 8 (impurity region 8a) is also tapered such that the bottom is narrower than the top. Due to the shape of the termination region 8, the lateral profile of the p-type impurity concentration is less steep than that of the first embodiment at both ends of the termination region 8.

In the present embodiment, as in the first embodiment, the alignment mark 9 and the recess 10 are formed to be very shallow, and the depth thereof is 50 nm or less and λ / n _max / 6 or less (n _max is the maximum refractive index of a film such as a resist formed on the SiC epitaxial layer 2 in the manufacturing process, and λ is the wavelength of the detection light of the alignment mark 9).

  According to this configuration, in addition to the same effects as in the first embodiment, the horizontal profile of the implantation concentration of the p-type impurity concentration at both ends of the termination region 8 is not steep, so that The electric field concentration can be suppressed, and the effect of further increasing the breakdown voltage of the termination region 8 can be obtained.

  13 to 16 are process diagrams showing the Schottky barrier diode shown in FIG. 12, its termination structure, and a method of forming an alignment mark. Hereinafter, based on these drawings, a method of manufacturing the semiconductor device according to the second embodiment will be described.

  First, similarly to the first embodiment, an n-type SiC substrate 1 is prepared, and an n-type SiC epitaxial layer 2 is grown thereon.

  Thereafter, an oxide film (not shown) is formed on SiC epitaxial layer 2, and then a resist pattern 11 serving also as an implantation mask for forming termination region 8 and an etching mask for forming alignment mark 9 is formed. It is formed by a transfer process (FIG. 13). That is, the resist pattern 11 has a shape having an opening 12 b located on the formation region of the termination region 8 and an opening 12 a located on the formation region of the alignment mark 9.

  In the present embodiment, the formed resist pattern 11 is heated or etched to incline the side surface of the resist pattern 11 as shown in FIG. Each of the openings 12a and 12b has a tapered shape whose bottom is narrower than the top.

  The resist pattern 11 whose side surface is inclined is formed in the process of forming the side surface of the resist pattern 11 by, for example, greatly shifting the focus of the transfer device during exposure of the photoresist or using a photoresist having poor resolution. It can also be formed by degrading the verticality of the film. In that case, the above heating or etching for the resist pattern 11 can be omitted.

  Next, alignment mark 9 and recess 10 are formed in SiC epitaxial layer 2 by etching using resist pattern 11 as a mask (FIG. 14). Also in this embodiment, the alignment mark 9 and the recess 10 are formed extremely shallow. Thereby, as in the first embodiment, the effects of improving the detection accuracy of the alignment mark 9 and suppressing the electric field concentration in the termination region 8 are obtained.

  In this embodiment, since the side surface of the resist pattern 11 is inclined, the side surface of the resist pattern 11 gradually recedes during this etching process. For this reason, the side surfaces of the alignment mark 9 and the recess 10 to be formed are also inclined, and the alignment mark 9 and the recess 10 are tapered.

  Subsequently, by using the remaining resist pattern 11 as a mask, p-type impurities are ion-implanted, thereby forming an impurity region 8a serving as a termination region 8 in the upper surface portion of the SiC epitaxial layer 2 (FIG. 15). At this time, an impurity region 8 a similar to the termination region 8 is also formed at the bottom of the alignment mark 9. An example of the p-type impurity is aluminum (Al).

  In the present embodiment, since the side surface of resist pattern 11 that is an implantation mask is inclined, a part of the p-type impurity implanted into the side surface reaches SiC epitaxial layer 2. As a result, the shape of termination region 8 (impurity region 8a) becomes tapered, and the lateral profile of the p-type impurity concentration becomes gentle at the end. Thereby, the effect of suppressing the electric field concentration at the end of the termination region 8 is obtained.

  Thereafter, similarly to the first embodiment, resist pattern 11 is removed, and SiC substrate 1 and SiC epitaxial layer 2 are heated to a temperature of 1500 ° C. or higher in order to activate the p-type impurity introduced into termination region 8. (FIG. 16).

  Then, the ohmic electrode 5 and the back electrode 6 are formed on the lower surface (rear surface) of the SiC substrate 1, and the Schottky electrode 3, the surface electrode 4 and the surface protective film 7 are formed on the upper surface of the SiC substrate 1, whereby FIG. The Schottky barrier diode shown, the termination region 8 having the recess 10 on the upper surface, and the recess-shaped alignment mark 9 are formed.

  As described above, according to the second embodiment, the recess 10 on the termination region 8 is extremely shallow and the lateral profile of the impurity concentration of the termination region 8 is not steep, so that the termination is further made than in the first embodiment. Electric field concentration in the region 8 can be suppressed, and a high breakdown voltage termination structure can be obtained. Similarly to the first embodiment, since the implantation mask for forming the termination region 8 and the etching mask for forming the alignment mark 9 are realized by the same resist pattern 11, the necessary number of masks. This can contribute to a reduction in manufacturing costs. Furthermore, since the alignment mark 9 is also formed to be extremely shallow, even if the film covering the alignment mark 9 changes during the manufacturing process of the semiconductor device, the intensity of the mark detection diffracted light 41b can be maintained high, and the mask can be formed multiple times. The alignment can always be made good, and the yield in manufacturing the SiC semiconductor device is improved.

  In the present embodiment, the termination region 8 is a guard ring, but the above manufacturing process can also be applied to the formation of the FLR. The FLR has basically the same structure as the guard ring except that there are a plurality of impurity concentrations. Therefore, in the step of forming the resist pattern 11 (FIGS. 2 and 13), if a plurality of resist patterns 11 are used, an FLR can be formed.

  In the above description, the Schottky barrier diode is exemplified as the semiconductor element. However, the present invention can also be applied to a termination structure such as IGBT or MOSFET, for example, JTE.

  Furthermore, the application of the present invention is not limited to a semiconductor device formed using silicon carbide (SiC), but can also be applied to the manufacture of a semiconductor device using a semiconductor material having a property that impurities are difficult to diffuse. For example, GaN, which is known as a wide band gap semiconductor along with SiC, has a property that impurities are difficult to diffuse. The same effect as described above can also be obtained for a semiconductor device in which the present invention is formed using GaN.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It is understood that countless variations that are not illustrated can be envisaged without departing from the scope of the present invention.

  1 SiC substrate, 2 SiC epitaxial layer, 3 Schottky electrode, 4 surface electrode, 5 ohmic electrode, 6 back electrode, 7 surface protective film, 8 termination region, 8a impurity region, 9 alignment mark, 11 resist pattern, 40 mark detection Irradiation light, 41 reflected light, 41a diffracted light, 41b diffracted light for mark detection.

Claims (4)

(A) forming a resist pattern having a first opening and a second opening on the silicon carbide semiconductor layer over a region serving as a terminal portion of the semiconductor element;
(B) By etching using the resist pattern as a mask, a recess having a depth of 50 nm or less is formed in the silicon carbide semiconductor layer under the first opening, and a recess is formed in the silicon carbide semiconductor layer under the second opening. Forming an alignment mark having a thickness of 50 nm or less,
(C) after the step (b), forming a termination region under the recess by ion-implanting impurities using the resist pattern as a mask;
(D) The silicon carbide semiconductor layer is irradiated with mark detection irradiation light, and the mark detection irradiation light is reflected light reflected at an edge portion of the alignment mark, and the direction of reflected light other than the edge portion Detecting the alignment mark by detecting diffracted light for mark detection entering a different specific optical path; and
With
In the step (d) , the maximum refractive index of the film formed on the alignment mark is n _max , and the silicon carbide semiconductor layer is irradiated with the mark detection irradiation light for detecting the alignment mark Where λ is the wavelength of
The depth of the alignment mark, the method for manufacturing the silicon carbide semiconductor device, characterized in that at λ _/ n _max / ₆ or less. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein a depth of the alignment mark is equal to a depth of the recess formed on an outer periphery of the semiconductor element. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the depth of the recess is deeper than 5 nm. 4. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the recess and the alignment mark have a tapered shape with a bottom portion narrower than an upper portion. 5.

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