JP5893260B2 - Plasma processing apparatus and processing method - Google Patents

Description

  The present invention relates to a plasma processing apparatus and a processing method suitable for performing an etching process on a material to be processed such as a semiconductor element substrate using plasma.

  In the semiconductor manufacturing process, dry etching using plasma is generally performed. Various types of plasma processing apparatuses for performing dry etching are used. In general, a plasma processing apparatus includes a vacuum processing chamber, a gas supply device connected to the vacuum processing chamber, a vacuum exhaust system for maintaining the pressure in the vacuum processing chamber at a desired value, an electrode on which a wafer substrate is placed, a plasma in the vacuum processing chamber. It comprises plasma generating means for generating. The processing gas supplied from the shower plate or the like into the vacuum processing chamber by the plasma generating means is changed to a plasma state, whereby the wafer substrate held by the wafer mounting electrode is etched.

  With the recent increase in the degree of integration of semiconductor devices, fine processing, that is, improvement in processing accuracy is required, and in-plane uniformity of the etching rate or in-plane uniformity of the CD value (Critical Dimension) in the etching shape, etc. Improvement is required. The uniformity of the in-plane etching rate of the material to be etched is susceptible to the following effects. Plasma density distribution, radical distribution, gas flow distribution, in-plane temperature distribution during etching of the material to be etched, reaction product distribution due to etching reaction, temperature setting of processing chamber side wall, etc. The influence of these distributions depends on the material properties of each layer film. In the case of plasma etching, the conditions of the etching process (for example, plasma excitation power, type of gas used, gas mixture ratio, gas pressure, bias RF power) It is necessary to optimize the temperature setting of the electrode or reactor wall etc. according to the material of each film layer. Therefore, it is difficult to obtain highly accurate in-plane uniformity of the etching rate and the etching shape (for example, CD) at the time when the etching of the multilayer film is completed. Further, in recent semiconductor processing, with the miniaturization, uniformity of etching characteristics is required on the order of nanometers or sub-nanometers.

  Due to the non-uniformity of the etching process due to electromagnetic and thermodynamic factors around the periphery of the wafer, the semiconductor device is processed around the periphery of the wafer. May be difficult. In such a case, in general, the device is designed not to be formed in a region where it is difficult to process the semiconductor device. In such a device design on the wafer, the unused area around the outer periphery of the wafer is referred to as edge exclusion (EE). E. The size of the area is a factor that greatly affects the semiconductor price. In recent years, in particular E.I. E. There is a need to reduce the area. E. Area 2 mm, and even E.I. E. There is a strong demand for an area of 1 mm.

  E. mentioned above. E. In order to reduce the area as much as possible and increase the number of chips that can be obtained from one wafer, various studies have been made on improving the uniformity within the wafer surface in the plasma processing apparatus. This E.I. E. In order to reduce the area, there has been proposed a method for improving the electromagnetic problem around the periphery of the wafer, particularly the curvature of the equipotential surface formed on the wafer. (Refer to Patent Document 1 or Patent Document 2) The proposed improvement method is a method in which a member called a high-frequency edge ring is arranged on the outer periphery of the wafer, and the sheath distribution on the wafer is made uniform from the center to the outer periphery. It has a structure of a processing apparatus that can obtain an etching result.

Japanese Patent No. 3881290 JP 2005-260011 A

  As a result of examining the configurations of Patent Documents 1 and 2, it has been found that there is a limit, although some improvement in uniformity is recognized around the periphery of the wafer. Therefore, the reason was further examined. As a result, the following was found.

  In the structures of Patent Documents 1 and 2, the upper surface height of the high-frequency edge ring disposed on the outer periphery of the wafer is lower than the uppermost surface of the wafer mounting electrode. This structure is described on the premise that the bias power applied to the wafer mounting electrode is coupled to the plasma through a cover ring provided on the outer periphery of the wafer mounting electrode. In other words, the bias power is combined with the plasma through the cover ring, and a thick high frequency sheath is formed on the upper surface of the cover ring to correct the curvature of the equipotential surface around the outer periphery of the wafer. In an actual plasma etching apparatus in recent years, the cover ring is formed with a certain finite thickness from the viewpoint of manufacturing processability and life, and is provided on the outer peripheral portion of the wafer mounting electrode. Most plasma etching apparatuses in recent years cannot pass through a cover ring formed with a finite thickness with an applied bias power, and it is difficult to form a sheath by combining with plasma. Therefore, it has been found that even if the structures as in Patent Documents 1 and 2 are used, it is actually difficult to sufficiently correct the curvature of the equipotential surface at the periphery of the wafer. That is, E.I. E. The uniformity of the etching rate of the portion cannot be sufficiently improved, and E.E. E. Area 2 mm or E.I. E. The performance of the area of 1 mm cannot be satisfied. Any published gazette including the above-mentioned Patent Documents 1 and 2 can be used for E. coli. E region 2 mm or E.I. E. It was impossible to correct the curvature of the equipotential surface around the outer periphery of the wafer, which was defined as an area of 1 mm.

  An object of the present invention is to provide a plasma processing apparatus and a processing method capable of reducing an edge exclusion (EE) region where etching characteristics are non-uniform.

In the present invention, the stage for holding the wafer has a convex part on the upper part and a step part arranged on the outer peripheral side thereof, the diameter of the convex part is smaller than the diameter of the wafer, and the wafer is placed on the upper surface thereof. The step portion is provided with the convex portion so as to have the same potential as an electrode to which a high-frequency power for forming a bias potential is applied to a stage for holding the wafer, and the upper surface thereof is the upper surface of the wafer. A higher ring-shaped member made of a conductor is disposed on the outside of the convex portion and is made of a dielectric material. The high-frequency power applied to the ring-shaped member covering the upper portion of the ring-shaped member is by having the above processing said consists so as not to be applied to the plasma cover chamber during processing to improve the curvature of the equipotential surfaces near the wafer outer peripheral portion, and the wafer equipotential surface surrounding the wafer outer peripheral portion Parallel And vertical trajectory of the ions incident on the wafer to the wafer, E. The etching rate of the E portion can be made uniform with high accuracy.

  According to the present invention, the edge exclusion (E) in which the etching characteristics become non-uniform by disposing the ring provided at the outer peripheral portion so as to be higher than the upper surface height of the wafer holding means and at the same potential. E.) It is possible to provide a plasma processing apparatus and a processing method capable of reducing the region.

1 is a longitudinal sectional view of a microwave ECR etching apparatus that is an embodiment of the present invention. The longitudinal cross-sectional view of the outer peripheral part vicinity of the wafer in a prior art example. The longitudinal cross-sectional view of the outer peripheral part vicinity of the wafer in a present Example. The etching rate distribution of the outer peripheral portion of the wafer in this example.

  A microwave ECR (Electron Cyclotron Resonance) etching apparatus according to an embodiment of the present invention will be described below with reference to FIG. A processing chamber 104 is formed by installing a dielectric window 103 (for example, made of quartz) for enclosing an etching gas in the vacuum vessel 101 on the upper portion of the vacuum vessel 101 whose top is opened. A shower plate 102 (for example, made of quartz) for introducing an etching gas into the vacuum container 101 is installed on the upper part of the vacuum container 101, and a gas supply device 117 for flowing the etching gas is connected to the shower plate 102. The A vacuum exhaust device 108 is connected to the vacuum vessel 101 through a vacuum exhaust port 106. A waveguide 107 (or an antenna) that radiates electromagnetic waves is provided above the dielectric window 103 in order to transmit power for generating plasma to the processing chamber 104. The electromagnetic wave transmitted to the waveguide 107 (or antenna) is oscillated from the electromagnetic wave generating power source 109. The frequency of the electromagnetic wave is not particularly limited, but a microwave of 2.45 GHz is used in this embodiment. A magnetic field generating coil 110 that forms a magnetic field is provided on the outer periphery of the processing chamber 104, and the electric power oscillated from the electromagnetic wave generation power source 109 is high-density plasma in the processing chamber 104 due to the interaction with the formed magnetic field. Is generated.

  Further, a wafer mounting electrode 111 is provided below the vacuum vessel 101 so as to face the dielectric window 103. The wafer mounting electrode 111 has an electrode surface covered with a sprayed film (not shown), and is connected to a DC power source 116 via a high frequency filter circuit 115. Further, a high frequency power supply 114 is connected to the wafer mounting electrode 111 via a matching circuit 113. The wafer 112 transferred into the processing chamber 104 is adsorbed on the wafer mounting electrode 111 by the electrostatic force of the DC voltage applied from the DC power supply 116, and after supplying a desired etching gas into the processing chamber 104, The inside of the vacuum chamber 101 is set to a predetermined pressure, and plasma is generated in the processing chamber 104. By applying a high frequency power from a high frequency power source 114 connected to the wafer mounting electrode 111, ions are drawn from the plasma into the wafer, and the wafer 112 is etched. Reference numeral 105 denotes a cover ring.

  FIG. 2 shows the structure of the periphery of the wafer in a conventional etching apparatus. In the conventional etching apparatus, the diameter of the upper surface of the wafer mounting electrode 111 is smaller than the diameter of the wafer 112 by several millimeters. Therefore, the upper surface outer peripheral side of the wafer mounting electrode 111 has a step shape. Further, as shown in FIG. 2, in order to prevent the stepped portion and the outer peripheral side surface of the wafer mounting electrode 111 from coming into contact with plasma, a cover ring 105 made of a dielectric material is attached to the wafer mounting electrode 111. It is provided at the step. With this structure, the wafer mounting electrode 111 is not in direct contact with the plasma, and the damage to the electrode surface and the consumption of the electrode surface due to the surface reaction caused by the plasma are suppressed. The cover ring is different from a general focus ring having a focusing effect for concentrating plasma on the wafer 112.

The cover ring 105 has a taper shape around the wafer 112 so as to have a function of guiding when the wafer 112 is transferred and a function of centering when the wafer 112 is transferred. The cover ring 105 is generally made of a quartz material, a ceramic material such as alumina, or a yttria material (Y ₂ O ₃ ).

  FIG. 2 shows the equipotential surface 201 of the electric field formed on the wafer 112 and the ion trajectory 202 drawn by the electric field. In general, a space charge layer called a plasma sheath is formed on the surface of a substance in contact with plasma. The equipotential surface 201 shown in FIG. 2 shows a situation at a certain moment in the electric field formed by the high frequency power supplied from the high frequency power supply 114 connected to the wafer 112 via the wafer mounting electrode 111. . When the conventional cover ring 105 as shown in FIG. 2 is used, the diameter of the convex portion of the wafer mounting electrode 111 that supports the wafer 112 is smaller than that of the wafer 112, and the stepped portion is the wafer 112 and the wafer mounting electrode 111. Therefore, there is a problem in that the equipotential surface on the wafer 112 is curved at the outer peripheral portion of the wafer 112. 2, the equipotential surface 201 is kept parallel to the wafer on the center side (region other than the outer peripheral portion) of the wafer 112, and the ion trajectory 202 incident on the wafer 112 is also perpendicular to the wafer. I understand. However, the equipotential surface 201 is curved at the outer peripheral portion (EE portion) of the wafer 112, so that the ion trajectory 202 incident on the wafer 112 is not perpendicular to the wafer but is greatly inclined. Therefore, the number of ions incident on the outer peripheral portion (EE portion) of the wafer 112 is increased compared to the center side (region other than the outer peripheral portion) of the wafer 112, and the outer peripheral portion (EE portion) of the wafer 112 is increased. ) Will increase the etching rate. That is, there is a problem that the uniformity of the etching rate at the outer peripheral portion (EE portion) of the wafer 112 is lowered, the electrical characteristics and performance of the semiconductor device at the outer peripheral portion are deteriorated, and the yield is lowered. Further, since the ions do not enter the wafer 112 vertically at the outer peripheral portion of the wafer 112 but enter the wafer 112 at a certain angle, the etching shape cannot be maintained. Since the etching shape cannot be controlled with high accuracy, the electrical characteristics and performance of the semiconductor device at the outer peripheral portion are deteriorated, and there is a problem that the yield is reduced.

Next, FIG. 3 shows the structure of the wafer periphery in this embodiment. In the present embodiment, the high frequency ring 303 is installed so as to surround the convex portion on the step portion on the outer peripheral side surface of the wafer mounting electrode 111 having a convex portion whose upper surface is circular (not shown). The material of the high frequency ring 303 is a metal conductor, for example, aluminum. Covering with a dielectric coating such as anodic oxidation treatment (anodized or the like) or surface treatment such as thermal spraying (thermal spray coating) as necessary can suppress plasma-induced surface reactions, abnormal discharge, and the like. The wafer mounting electrode 111 and the high frequency ring 303 are set to the same potential. In order to set the wafer mounting electrode 111 and the high frequency ring 303 to the same potential, for example, the wafer mounting electrode 111 and the high frequency ring 303 are metal-touched. The high frequency ring 303 is connected to the wafer mounting electrode 111 with a conductive bolt or the like. A plurality of methods are conceivable, such as fastening with a screw. Further, the wafer mounting electrode 111 may be formed as shown in FIG. 3 from the beginning without forming the high-frequency ring 303 as a separate part, and may be an integral part. A cover ring 105 is attached to the high frequency ring 303 in order to protect the high frequency ring 303 from plasma. The cover ring 105 covers the outer diameter side as well as the inner diameter side and the upper surface of the high frequency ring 303. With this structure, the wafer mounting electrode 111 and the high-frequency ring 303 are not in direct contact with plasma, and surface damage and surface wear due to surface reactions caused by plasma are suppressed. The cover ring 105 has a taper shape around the wafer 112 so as to have a function of guiding when the wafer 112 is transferred and a function of centering when the wafer 112 is transferred. The cover ring 105 is generally made of a quartz material, a ceramic material such as alumina, or a yttria material (Y ₂ O ₃ ).

  Here, the height of the upper surface of the high frequency ring 303 must be higher than the height of the upper surface of the wafer mounting electrode 111. If possible, the height of the upper surface of the high frequency ring 303 should be higher than the height of the upper surface of the wafer 112. By providing the upper surface height of the high frequency ring 303 higher than the upper surface of the wafer 112, the equipotential surface near the outer periphery of the wafer 112 is improved to be parallel to the wafer 112. Actually, in order to suppress the curvature of the equipotential surface in the vicinity of the outer peripheral portion of the wafer 112 and make it parallel to the wafer 112, the height of the upper surface of the high-frequency ring 303 is higher than the upper surface of the wafer mounting electrode 111. , 0.0 mm or more and 5.0 mm or less. When the upper surface of the high-frequency ring 303 is lower than the upper surface of the wafer 112, the effect of suppressing the curvature of the equipotential surface in the vicinity of the outer peripheral portion of the wafer 112 is reduced, and the wafer 112 and the equipotential surface are parallel in the outermost periphery of the wafer 112. It will be difficult to do. Further, by making the inner diameter of the high-frequency ring 303 closer to the outer diameter of the wafer, it is possible to suppress the curvature of the equipotential surface in the vicinity of the outer peripheral portion of the wafer 112. However, if the wafer 112 and the high frequency ring are too close to each other, abnormal discharge or the like occurs. Therefore, the outer diameter of the wafer 112 and the inner diameter of the high frequency ring 303 may be separated from each other by 1.0 mm or more. It is desirable to insert a dielectric such as the cover ring 105 into the gap. Therefore, the gap interval between the inner diameter of the high frequency ring 303 and the outer diameter of the wafer is preferably 1.0 mm or more and 10 mm or less. The thickness of the dielectric material is preferably in the range of 1.0 mm to 5.0 mm. A thickness of 1.0 mm or less is not desirable from the viewpoint of fabrication workability of the dielectric material and transmission of bias power, and a thickness of 5.0 mm or more tends to cause a problem of retention of reaction products generated from the wafer during the etching process. Therefore, the height of the upper surface of the cover ring 105 from the upper surface of the wafer mounting electrode 111 is preferably 10 mm or less.

  As described above, the structure of the wafer peripheral portion as shown in FIG. 3 can further suppress the curvature of the equipotential surface near the outer peripheral portion of the wafer 112, and the vicinity of the center and the outer periphery in the processing of the wafer 112. And more uniform plasma treatment can be performed.

  FIG. 3 shows an equipotential surface 301 of an electric field formed on the wafer 112 and an ion trajectory 302 drawn by the electric field. In general, a space charge layer called a plasma sheath is formed on the surface of a substance in contact with plasma. The equipotential surface 301 shown in FIG. 3 shows a situation at a certain moment in the electric field formed by the high-frequency power supplied from the high-frequency power supply 114 connected to the wafer 112 through the wafer mounting electrode 111. . When the high-frequency ring 303 and the cover ring 105 as shown in FIG. 3 according to the present embodiment are used, the equipotential surface on the wafer 112 is not curved at the outer peripheral portion of the wafer 112 and can be made parallel to the wafer 112. As shown in FIG. 3, the equipotential surface 301 is kept parallel to the wafer from the center to the outer periphery of the wafer 112, and the ion trajectory 302 incident near the outer periphery of the wafer 112 is also perpendicular to the wafer. I understand that there is. Therefore, the number of ions incident on the outer peripheral portion from the central portion of the wafer 112 can be made uniform, and the etching rate can be made uniform within the surface of the wafer 112. In other words, the uniformity of the etching rate from the central portion of the wafer 112 to the outer peripheral portion (EE portion) is improved, and in particular, the electrical characteristics and performance of the semiconductor devices on the outer peripheral portion of the wafer 112 are not deteriorated and the yield is improved. effective. In addition, ions also enter the wafer 112 vertically at the outer periphery of the wafer 112, and the etching shape becomes a vertical shape. The etching shape can be controlled with high accuracy, and there is an effect of improving the yield without deteriorating the electrical characteristics and performance of the semiconductor device at the outer peripheral portion.

  Further, due to the structure of the periphery of the wafer as shown in FIG. 3, the potential on the wafer 112 and the surface potential of the high frequency ring 303 are always equal, and even if the process conditions (especially wafer bias power) for the wafer 112 change, The curvature of the equipotential surface of the part can be suppressed. That is, even if the process conditions change, the equipotential surface in the vicinity of the outer periphery of the wafer 112 can be made parallel to the wafer 112 without optimizing the dimensions of the high frequency ring 303 each time, and the efficiency of plasma processing is improved.

  Next, FIG. 4 shows an actual etching rate result. In this embodiment, the material to be etched is a silicon nitride film, and for example, tetrafluoromethane gas, oxygen gas, or trifluoromethane gas is used as an etching gas. A curve 401 shows the in-plane distribution of the etching rate when etching is performed with the conventional structure of the peripheral portion of the wafer as shown in FIG. 2, particularly the wafer outer peripheral portion (EE portion). A curve 402 shows the in-plane distribution of the etching rate, particularly the wafer outer peripheral portion (EE portion) when etching is performed with the structure provided with the high frequency ring 303 shown in FIG.

  As indicated by the curve 401, when etching is performed with the conventional structure of the peripheral portion of the wafer, the etching rate of the peripheral portion of the wafer 112 increases rapidly, and the uniformity within the surface of the wafer 112 decreases. On the other hand, by providing the structure of the wafer peripheral portion as shown in FIG. 3 according to the present embodiment as indicated by the curve 402, the rapid increase in the etching rate of the peripheral portion of the wafer 112 is suppressed, Etch rate uniformity is improved. As described above, when the high-frequency ring 303 and the cover ring 105 as shown in FIG. 3 are used, the equipotential surface on the wafer 112 is not curved at the outer periphery of the wafer 112 and can be made parallel to the wafer 112. The equipotential surface is kept parallel to the wafer from the center to the outer periphery of the wafer 112, and the trajectory of ions incident near the outer periphery of the wafer 112 can be made perpendicular to the wafer. E. Area 2 mm, E.I. E. Etching characteristics (processed shape, etching rate, etc.) at the outer periphery of the wafer in an area of 1 mm can be made highly uniform (reduction of the EE area). Therefore, the number of ions incident on the outer peripheral portion from the center side of the wafer 112 can be made uniform within the surface, and the etching rate within the wafer surface can be made uniform. In other words, the uniformity of the etching rate from the central portion of the wafer 112 to the outer peripheral portion (EE portion) is improved, and in particular, the electrical characteristics and performance of the semiconductor device on the outer peripheral portion of the wafer 112 are not deteriorated, and the yield is improved. There is an effect of improving. In addition, ions also enter the wafer 112 vertically at the outer periphery of the wafer 112, and the etching shape becomes a vertical shape. The etching shape can be controlled with high accuracy, and the region where the electrical characteristics and performance of the semiconductor device are not deteriorated is expanded in the outer peripheral portion, and the yield is improved.

  As described above, when the conventional wafer peripheral structure as shown in FIG. 2 is used, the trajectory of ions incident on the outer periphery of the wafer 112 is bent toward the center of the wafer 112. These ions whose bent trajectories are incident not only on the outer periphery of the wafer but also on the inner periphery of the cover ring 105, that is, on the surface of the cover ring 105 near the outermost periphery of the wafer 112. Since the ions incident on the inner peripheral surface of the cover ring 105 are bent toward the wafer center when the conventional wafer peripheral structure as shown in FIG. 2 is used, the inner peripheral portion of the cover ring 105 is The wafer 112 is consumed toward the center. That is, the inner peripheral portion of the cover ring 105 is not consumed in the vertical direction but is consumed in the horizontal direction. Therefore, the life of the cover ring 105 is determined by the diameter of the step portion of the wafer mounting electrode 111. The step portion of the wafer mounting electrode 111 preferably has a diameter smaller than that of the wafer 112 in order to suppress plasma-induced surface reaction. However, by reducing the diameter, the temperature during the etching process of the wafer 112 is reduced. The controllability and the adsorptive power are reduced. Therefore, the diameter of the stepped portion of the wafer mounting electrode 111 cannot be made smaller than the optimum diameter. When the conventional structure of the peripheral portion of the wafer as shown in FIG. It was difficult to prolong. On the other hand, when the structure using the high frequency ring 303 and the cover ring 105 as shown in FIG. 3 is used, the trajectory of ions incident on the outer periphery of the wafer 112 can be perpendicular to the wafer 112 as described above. . Therefore, when the structure of the peripheral portion of the wafer of this embodiment as shown in FIG. 3 is used, ions incident on the surface of the peripheral portion of the inner diameter of the cover ring 105 are incident in a direction perpendicular to the wafer, and the peripheral portion of the inner diameter of the cover ring 105 Is consumed in the vertical direction. That is, the inner peripheral portion of the cover ring 105 is not consumed in the horizontal direction toward the center of the wafer 112 but is consumed only in the vertical direction. Therefore, the life of the cover ring can be determined by the thickness of the cover ring 105 regardless of the diameter of the step portion of the wafer mounting electrode 111. Specifically, the structure around the wafer as shown in FIG. 3 according to the present embodiment has an effect of extending the life of the cover ring 105. As a result, the maintenance time of the plasma processing apparatus can be reduced, the number of parts replacements can be reduced, and the productivity of semiconductor devices can be improved and the number of semiconductor devices can be reduced.

  In this embodiment, the material to be etched is a silicon nitride film, and the above-described tetrafluoromethane gas, oxygen gas, and trifluoromethane gas are used as an etching gas, but the material to be etched is not only a silicon nitride film, Polysilicon film, photoresist film, antireflection organic film, antireflection inorganic film, organic material, inorganic material, silicon oxide film, silicon nitride oxide film, silicon nitride film, low-k material, high-k material, amorphous The same effect can be obtained with carbon films, Si substrates, metal materials, etc. Etching gas may be, for example, chlorine gas, hydrogen bromide gas, tetrafluoromethane gas, trifluoromethane, difluoride methane, argon gas, helium gas, oxygen gas, nitrogen gas, carbon dioxide. , Carbon monoxide, hydrogen, ammonia, propane octafluoride, nitrogen trifluoride, sulfur hexafluoride gas, methane gas, silicon tetrafluoride gas, silicon tetrachloride gas, chlorine gas, hydrogen bromide gas, tetrafluoromethane gas , Methane trifluoride, methane difluoride, argon gas, helium gas, oxygen gas, nitrogen gas, carbon dioxide, carbon monoxide, hydrogen, ammonia, propane octafluoride, nitrogen trifluoride, sulfur hexafluoride gas, Used by methane gas, silicon tetrafluoride gas, silicon tetrachloride gas, helium gas, neon gas, krypton gas, xenon gas, radon gas, etc. Kill.

  In the above embodiments, an etching apparatus using microwave ECR discharge has been described as an example, but other discharges (magnetic field UHF discharge, capacitively coupled discharge, inductively coupled discharge, magnetron discharge, surface wave excited discharge, The same effect can be obtained in a dry etching apparatus using a coupled discharge). In each of the above embodiments, the etching apparatus has been described. However, other plasma processing apparatuses that perform plasma processing, such as a plasma CVD apparatus, an ashing apparatus, and a surface modification apparatus, have similar operational effects.

  In addition, this invention is not limited to an above-described Example, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described.

DESCRIPTION OF SYMBOLS 101 ... Vacuum container, 102 ... Shower plate, 103 ... Dielectric window, 104 ... Processing chamber, 105 ... Covering, 106 ... Vacuum exhaust port, 107 ... Waveguide Tube ... 108 ... Vacuum evacuation device, 109 ... Electromagnetic wave generation power supply, 110 ... Magnetic field generation coil, 111 ... Wafer mounting electrode, 112 ... Wafer, 113 ... Matching circuit, 114 ... high frequency power supply, 115 ... high frequency filter circuit, 116 ... DC power supply, 117 ... gas supply device, 201 ... equipotential surface, 202 ... ion orbit, 301 ... etc. Potential plane, 302 ... ion orbit, 303 ... high frequency ring, 401 ... etching rate (conventional), 402 ... etching rate (present invention).

Claims (6)

A processing chamber to which an evacuation apparatus is connected and whose inside can be depressurized, a device for supplying gas into the processing chamber, a table for holding a material to be processed in the processing chamber, and plasma in the processing chamber In a plasma processing apparatus having plasma generating means for generating and a high-frequency power source configured to be able to variably supply the magnitude of high-frequency power for forming a bias potential on a stage holding the material to be processed,
The base has a convex part on the upper part and a step part arranged on the outer peripheral side thereof, the diameter of the convex part is smaller than the diameter of the material to be processed, and the material to be processed is placed on the upper surface thereof. The stepped portion has a ring-shaped member made of a conductor having the same potential as an electrode to which the high-frequency power is applied, and having an upper surface higher than the upper surface of the material to be processed. Is disposed on the outside of the convex portion, is made of a dielectric material, and the high-frequency power applied to the ring-shaped member so as to cover the upper portion of the ring-shaped member is generated in the processing chamber during the processing of the material to be processed. the plasma processing apparatus characterized by comprising a structure made a cover so as not to be applied to the plasma. The plasma processing apparatus according to claim 1,
The plasma processing apparatus, wherein an upper surface of the ring-shaped member is disposed at a height in a range of 5.0 mm or less higher than an upper surface of the processing object. The plasma processing apparatus according to claim 1,
The plasma processing apparatus, wherein an inner diameter of an upper surface of the ring-shaped member is larger in a range of 1.0 mm to 10 mm than an outer diameter of the processing object. The plasma processing apparatus according to claim 1,
The plasma processing apparatus, wherein the ring-shaped member and the base are configured as the same part. The plasma processing apparatus according to any one of claims 1 to 4 ,
The height of the equipotential surface in the plasma sheath formed above the top surface of the material to be treated during the processing of the material to be treated is the same as the height of the equipotential surface in the plasma sheath formed above the top surface of the ring-shaped member. A plasma processing apparatus characterized by being equal . A material to be processed is placed on and held on a base in the processing chamber whose pressure has been reduced, a gas is supplied into the processing chamber to generate plasma in the processing chamber, and a high frequency for forming a bias potential from a high frequency power source to the base. In the plasma processing method of processing the material to be processed by applying electric power,
The high-frequency power source is capable of variably adjusting the magnitude of the high-frequency power, and the platform has a convex part on the upper part and a step part arranged on the outer peripheral side thereof, and the diameter of the convex part is the covered part. It is made of a conductor that is smaller than the diameter of the treatment material and on which the treatment material is placed, and whose upper surface is higher than the upper surface of the treatment material on the step portion outside the convex portion . cover made of a dielectric material covering the upper ring-shaped member and the ring-shaped member is disposed, said high frequency power the ring-shaped member is provided in the table are such that the electrodes at the same potential applied And processing the material to be processed in a state in which the high-frequency power applied to the ring member is not applied to the plasma in the processing chamber.

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