JP5899793B2 - Semiconductor integrated circuit, infrared imaging device, and readout method - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, an infrared imaging device, and a reading method.

There is known an infrared imaging device that can capture an imaging target using infrared rays at night or the like.
The infrared imaging device includes a plurality of pixel circuits having sensors that detect infrared rays emitted from an imaging target. The sensor has an electric resistance that changes in accordance with the amount of incident infrared rays. When a bias voltage is applied to each sensor, a pixel value (voltage value) corresponding to the amount of current flowing through each sensor is read from each pixel circuit in time series by, for example, a shift register.

The read pixel value is amplified, subjected to A / D (analog / digital) conversion, pixel value correction processing, and the like, then D / A converted and output to the display device.
In recent years, the power consumption of an amplifying circuit that amplifies the read pixel value has increased due to the increase in the pixel format.

JP 2004-364241 A

  Since the level of the read pixel value varies from sensor to sensor, the power consumption of the amplifier circuit that amplifies the pixel value varies, and the amount of heat generated also varies. As a result, there is a problem that an infrared detection sensor sensitive to temperature fluctuation is affected, and an appropriate pixel value cannot be read from the pixel circuit.

  According to one aspect of the invention, a sensor that passes a current corresponding to the amount of incident infrared rays, an integration unit that integrates the current flowing through the sensor and converts the current into a voltage value, and a holding unit that holds the converted voltage value A plurality of pixel circuits, a readout circuit that reads out pixel values corresponding to voltage values held in the holding unit from the plurality of pixel circuits, and pixel values read out from the plurality of pixel circuits. A semiconductor integrated circuit comprising: an amplifier circuit that amplifies; and a control signal generation circuit that generates a control signal that causes an operation stop period of the readout circuit before or during the integration period of the current in the integration unit Is provided.

  Also, according to one aspect of the invention, a sensor that passes a current according to the amount of infrared rays incident thereon, an integration unit that integrates the current flowing through the sensor and converts the current into a voltage value, and the converted voltage value A plurality of pixel circuits including a holding unit for holding, a read circuit for reading out a pixel value corresponding to a voltage value held in the holding unit from the plurality of pixel circuits, and a read out from the plurality of pixel circuits. An amplification circuit that amplifies the pixel value, a control signal generation circuit that generates a control signal that causes an operation stop period of the readout circuit before or during the integration period of the current in the integration unit, and the sensor There is provided an infrared imaging device including a cooling unit for cooling.

  According to an aspect of the invention, the current flowing through the sensor is integrated and converted into a voltage value according to the amount of infrared light incident on the plurality of pixel circuits having the sensor, and the voltage value is held. An operation stop period of the readout circuit that reads out and amplifies pixel values corresponding to the held voltage values from the plurality of pixel circuits, and reads out the pixel values before or during the integration period of the current Is provided.

  According to the disclosed semiconductor integrated circuit, infrared imaging device, and readout method, it is possible to suppress the influence of fluctuations in the amount of heat generated by the amplification circuit that amplifies the read pixel value on the sensor.

It is a figure which shows an example of the infrared imaging device of this Embodiment. It is a figure which shows an example of a cooling unit. It is a figure which shows an example of the fluctuation | variation of element temperature, the element current, and the voltage of storage capacity. It is a figure which shows the other example of the fluctuation | variation of element temperature, the element current, and the voltage of storage capacity. It is a figure which shows the example of a fluctuation | variation of element temperature at the time of stopping reading of a pixel value in a certain period before the start of an integration period. It is a figure which shows the example of a fluctuation | variation of element temperature when reading of a pixel value is stopped in a certain period in an integration period. It is a figure which shows an example of the fluctuation | variation of element temperature at the time of providing two reading stop periods, element current, and the voltage of storage capacity. It is a figure which shows an example of the control signal which produces the operation stop period of a read circuit. It is a figure which shows an example of a control signal generation circuit. 3 is a timing chart illustrating an example of an operation of a control signal generation circuit.

Hereinafter, the present embodiment will be described with reference to the drawings.
FIG. 1 is a diagram illustrating an example of an infrared imaging device according to the present embodiment.
The infrared imaging device 1 includes a semiconductor integrated circuit 2, a lens unit 10, a pulse generation circuit 11, a signal processing circuit 12, a display device 13, and a cooling unit 14. Note that a circuit for supplying a power supply voltage to each unit of the infrared imaging device 1 and a control unit that controls each unit of the infrared imaging device 1 are not shown.

  The semiconductor integrated circuit 2 includes a plurality of pixel circuits 3-1, 3-2, 3-3, 3-4, a readout circuit 4, an amplifier circuit 5, a control signal generation circuit 6, and vertical signal lines 7-1 and 7-2. , Horizontal signal lines 8-1 and 8-2, an output line 9, and transistors Tr 1, Tr 2 and Tr 3.

  In the example of the infrared imaging device 1 shown in FIG. 1, 2 × 2 pixel circuits 3-1 to 3-4 are shown to simplify the illustration, but there are five or more pixel circuits. Needless to say.

The pixel circuit 3-1 includes a sensor 3a, an input transistor 3b, an integration unit 3c, a holding unit 3d, and transistors 3e and 3f.
The sensor 3a is an element in which the electric resistance changes according to the amount of infrared rays and the flowing current changes. For this reason, the sensor 3 a passes a current corresponding to the amount of incident infrared light incident through the lens unit 10.

  The input transistor 3b is, for example, an n-channel MOSFET (Metal-Oxide Semiconductor Field Effect Transistor). The input transistor 3b is connected between the sensor 3a and the integration unit 3c, and connects or disconnects the current path between the sensor 3a and the integration unit 3c in accordance with a signal input to the gate. Although not shown, a signal from a control signal generation circuit 6 described later is input to the gate of the input transistor 3b.

  The integrating unit 3c includes a transistor 3c1 and a storage capacitor 3c2. The transistor 3c1 is, for example, a p-channel MOSFET, a power supply voltage is supplied to the source, and one terminal of the storage capacitor 3c2 is connected to the drain. Although not shown, the reset signal from the pulse generation circuit 11 is input to the gate of the transistor 3c1. When the pixel circuit 3-1 is reset, the transistor 3c1 is turned on, and the storage capacitor 3c2 is charged by the power supply voltage. The other terminal of the storage capacitor 3c2 is grounded. A node between the transistor 3c1 and the storage capacitor 3c2 is connected to the input transistor 3b and the holding unit 3d.

  When the input transistor 3b is on (integration period) and the transistor 3c1 is off, the integrating unit 3c accumulates (integrates) the current flowing through the sensor 3a with the storage capacitor 3c2 and converts it into a voltage value.

  For example, as shown in FIG. 1, the holding unit 3d is a sample-and-hold circuit, and includes a transistor 3d1 that is an n-channel MOSFET, a transistor 3d2 that is a p-channel MOSFET, and a capacitor 3d3. . The transistors 3d1 and 3d2 are connected between a node between the transistor 3c1 and the storage capacitor 3c2 of the integrating unit 3c and one terminal of the capacitor 3d3. The other terminal of the capacitor 3d3 is grounded. Although not shown, when the signal from the pulse generation circuit 11 is input to the gates of the transistors 3d1 and 3d2 and both the transistors 3d1 and 3d2 are on, the voltage value obtained by integration with the storage capacitor 3c2 Is held in the capacitor 3d3.

  The transistors 3e and 3f are, for example, n-channel MOSFETs, and a power supply voltage is applied to the drain of the transistor 3e. The source of the transistor 3e is connected to the drain of the transistor 3f, and the source of the transistor 3f is connected to the vertical signal line 7-1. The gate of the transistor 3e is connected to a node between the transistors 3d1 and 3d2 and the capacitor 3d3. The gate of the transistor 3f is connected to the horizontal signal line 8-1.

When the transistor 3f is on, a voltage value corresponding to the gate voltage of the transistor 3e (hereinafter, this voltage value is referred to as a pixel value) is applied to the vertical signal line 7-1.
Although not shown, the other pixel circuits 3-2 to 3-4 will be described below as having the same elements as the pixel circuit 3-1.

  The readout circuit 4 reads out pixel values corresponding to the voltage values held in the pixel circuits 3-1 to 3-4. The readout circuit 4 has a vertical shift register 4a and a horizontal shift register 4b.

  The vertical shift register 4a controls the transistor 3f according to a signal from the pulse generation circuit 11 to connect the pixel circuits 3-1 to 3-4 connected to the horizontal signal lines 8-1 and 8-2 to the horizontal signal line 8. Select every -1,8-2. For example, when the pixel circuits 3-1 and 3-2 are selected, the vertical shift register 4a supplies an H (High) level signal to the horizontal signal line 8-1, turns on the transistor 3f, and sets the pixel value. Is transmitted to the vertical signal lines 7-1 and 7-2.

  The horizontal shift register 4b controls the transistors Tr1 and Tr2 by a signal from the pulse generation circuit 11 or the control signal generation circuit 6, and converts the pixel values read out to the vertical signal lines 7-1 and 7-2 into horizontal signals. The lines 8-1 and 8-2 are selected for each line and transmitted to the output line 9.

The amplifier circuit 5 is an operational amplifier, for example, and amplifies and outputs the pixel value read out to the output line 9.
The control signal generation circuit 6 generates a control signal that causes an operation stop period of the read circuit 4 before or during the integration period of the current in the integration unit 3c. In the example of the semiconductor integrated circuit 2 shown in FIG. 1, the control signal generation circuit 6 generates a control signal that causes an operation stop period of the horizontal shift register 4b and supplies the control signal to the horizontal shift register 4b.

  The transistor Tr3 connected to the output line 9 is, for example, an n-channel MOSFET, and the output line 9 is connected to the drain and the source is grounded. During operation of the semiconductor integrated circuit 2, a power supply voltage is applied to the gate of the transistor Tr 3, the transistor Tr 3 is turned on, and a constant current serving as a bias current for the amplifier circuit 5 is supplied to the output line 9.

In the infrared imaging device 1, the lens unit 10 collects infrared rays from the imaging target and enters the pixel circuits 3-1 to 3-4.
The pulse generation circuit 11 generates and supplies pulse signals for operating the pixel circuits 3-1 to 3-4, the readout circuit 4, and the control signal generation circuit 6. For example, the pulse generation circuit 11 supplies a predetermined timing (for example, one frame of pixels from the pixel circuits 3-1 to 3-4 to the gate of the transistor 3c1 in the integration unit 3c of the pixel circuits 3-1 to 3-4. A reset signal is supplied at the time of reading the value). The pulse generation circuit 11 supplies the control signal generation circuit 6 with a horizontal clock pulse or a data pulse for the horizontal shift register 4b.

  The signal processing circuit 12 performs signal processing on the pixel value amplified by the amplifier circuit 5 and outputs the processed signal to the display device 13. For example, the signal processing circuit 12 includes an A / D conversion circuit, an arithmetic circuit, and a D / A conversion circuit. The signal processing circuit 12 converts an analog signal, which is an output signal of the amplifier circuit 5, into a digital signal. Gain correction is performed, and the corrected digital signal is converted into an analog signal.

The display device 13 is a liquid crystal display, for example, and receives an analog signal output from the signal processing circuit 12 and displays an infrared image to be imaged.
The cooling unit 14 cools the semiconductor integrated circuit 2 and adjusts the temperature of the sensor 3a to, for example, about 70K to 80K. The cooling unit 14 may have a heater for temperature adjustment.

FIG. 2 is a diagram illustrating an example of the cooling unit.
1 includes a refrigerator (for example, a Stirling refrigerator) 20, a vacuum vessel 21, a stem 22, an infrared transmission window 23, a cold shield 24, a temperature sensor 25, a heater, as shown in FIG. 26, a temperature regulator 27, and wirings 28 and 29.

  The refrigerator 20 introduces a displacer 20a, in which an animal cooler is housed, into the vacuum vessel 21, and cools the semiconductor integrated circuit 2 disposed on the stem 22 attached to the tip of the displacer 20a.

  The infrared transmission window 23 introduces infrared rays incident through the lens unit 10 shown in FIG. The infrared rays introduced into the vacuum chamber 21 through the infrared transmission window 23 are limited in view by the cold shield 24, and unnecessary incident light is cut and incident on the semiconductor integrated circuit 2.

Further, a temperature sensor 25 and a heater 26 are arranged on the stem 22, and the temperature sensor 25 and the heater 26 are connected to a temperature regulator 27 via wirings 28 and 29.
The temperature adjuster 27 controls the heater 26 according to the temperature detected by the temperature sensor 25 and adjusts the temperature so as to be a set temperature (for example, 70K to 80K).

  In the infrared imaging device 1 and the semiconductor integrated circuit 2 as described above, the pixel value for one frame is read from the pixel circuits 3-1 to 3-4 by the reading circuit 4 for each unit time, and the amplification circuit 5 The amplified signal is processed by the signal processing circuit 12 and displayed on the display device 13.

  In order to increase the throughput, at the time of reading, integration for determining pixel values to be read in the next frame is also performed by the pixel circuits 3-1 to 3-4. That is, while the pixel value corresponding to the voltage value held in the holding unit 3d of the pixel circuits 3-1 to 3-4 is being read, the current flowing through the sensor 3a is integrated by the integrating unit 3c. When reading out the pixel values for one frame, the power consumption in the amplifier circuit 5 mainly fluctuates according to the pixel value, and the amount of heat generation also fluctuates. Thereby, the temperature (element temperature) of the sensor 3a varies.

FIG. 3 is a diagram illustrating an example of a variation in device temperature, a device current, and a storage capacitor voltage.
FIG. 3 shows an example of changes in element temperature, element current, and voltage of the storage capacitor 3c2 on the same time axis. When the element temperature fluctuates as shown in FIG. 3 with respect to the set temperature in the cooling unit 14, the dark current flowing through the sensor 3a is affected, and the element current also fluctuates and deviates from the ideal value. .

In the element current integration period (timing t1 to t2), when the fluctuation of the element current having a long period as shown in FIG. 3 occurs, the voltage of the storage capacitor 3c2 becomes lower than the ideal value.
FIG. 4 is a diagram showing other examples of fluctuations in device temperature and device current and storage capacitor voltage.

  FIG. 4 also shows an example of changes in element temperature, element current, and voltage of the storage capacitor 3c2 on the same time axis. When the element temperature fluctuates as shown in FIG. 4 with respect to the set temperature in the cooling unit 14, the element current also fluctuates and deviates from the ideal value.

In the integration period (timing t3 to t4) of the element current, when a fluctuation as shown in FIG. 4 occurs, the voltage of the storage capacitor 3c2 becomes higher than the ideal value.
When a deviation from the ideal value of the voltage of the storage capacitor 3c2 as shown in FIGS. 3 and 4 occurs, the screen becomes bright and dark regardless of the amount of incident infrared light, which causes so-called flickering. Increasing the heat capacity of the sensor 3a can reduce the influence of fluctuations in heat generation. However, the refrigerator 20 and the heater 26 required for temperature adjustment of the sensor 3a are required to have high output.

  In order to suppress such a deviation of the voltage of the storage capacitor 3c2 from the ideal value, in the infrared imaging device 1 of the present embodiment, the control signal generation circuit 6 causes the element current integration period before or during the integration period. For a certain period, the reading operation of the pixel value by the reading circuit 4 is stopped.

  Thus, during the operation stop period of the readout circuit 4, the pixel value is not output from the amplifier circuit 5, the power consumption of the amplifier circuit 5 is constant, and the fluctuation of the heat generation amount is suppressed. Therefore, the element temperature approaches the set temperature.

FIG. 5 is a diagram illustrating a variation example of the element temperature when reading of the pixel value is stopped in a certain period before the start of the integration period. The vertical axis represents element temperature, and the horizontal axis represents time.
A dotted line indicates an example of variation in element temperature when reading of pixel values is not stopped.
In the example shown in FIG. 5, the period from timing t5 to t6 before the start of the integration period is set as a read stop period (operation stop period of the read circuit 4).

  When the reading of the pixel value from the pixel circuits 3-1 to 3-4 is stopped at the timing t5, the variation in the amount of heat generated in the amplifier circuit 5 according to the pixel value is suppressed, and the element temperature approaches the set temperature. . Thereby, the fluctuation | variation with respect to setting temperature of element temperature can be suppressed also in the integration period of subsequent timing t6-t7.

  As shown in FIG. 3 and FIG. 4, since the element current fluctuates in the same manner as the element temperature, the element current can be brought close to the ideal value by bringing the element temperature in the integration period closer to the set value. Deviation from the ideal value of the voltage of the storage capacitor 3c2 can be suppressed.

  In the example shown in FIG. 5, the end timing of the read stop period is made coincident with the start timing of the integration period, but it is not always necessary to make it coincide. However, in order to further suppress fluctuations in the element temperature during the integration period, it is desirable to set a read stop period immediately before the start of the integration period.

FIG. 6 is a diagram illustrating a variation example of the element temperature when reading of the pixel value is stopped in a certain period during the integration period. The vertical axis represents element temperature, and the horizontal axis represents time.
A dotted line indicates an example of variation in element temperature when reading of pixel values is not stopped.

In the example illustrated in FIG. 6, a period from timing t9 to t10 in the integration period (timing t8 to t11) is set as a reading stop period.
When the reading of the pixel value from the pixel circuits 3-1 to 3-4 is stopped at the timing t9, the variation in the heat generation amount in the amplifier circuit 5 according to the pixel value is suppressed, and the element temperature approaches the set temperature. . Thereby, the fluctuation amount of the element temperature with respect to the set temperature during the integration period can be suppressed.

  As shown in FIG. 3 and FIG. 4, since the element current fluctuates in the same manner as the element temperature, the element current can be brought close to the ideal value by bringing the element temperature in the integration period closer to the set value. Deviation from the ideal value of the voltage of the storage capacitor 3c2 can be suppressed.

  In this way, the readout circuit 4 stops the readout of the pixel values from the pixel circuits 3-1 to 3-4 for a certain period before the start of the integration period or during the integration period. It is possible to suppress the influence of the variation in the amount of heat generated by the amplification circuit 5 to be amplified on the sensor 3a. For this reason, the deviation of the voltage value of the storage capacitor 3c2 from the ideal value can be suppressed, the influence of fluctuations in the heat generation amount of the amplifier circuit 5 on the pixel value read in the next frame can be reduced, and flickering of the screen can be suppressed. .

  Incidentally, fluctuations in element temperature at the start and end of integration are easily reflected in the noise of the output voltage of the semiconductor integrated circuit 2. Therefore, it is also desirable to stop the readout of pixel values by the readout circuit 4 during a period from a certain timing before the start of integration to an integration start timing and a period from a certain timing during the integration period to the integration end timing.

  FIG. 7 is a diagram illustrating an example of fluctuations in element temperature, element current, and storage capacitor voltage when two reading stop periods are provided. An example of changes in element temperature, element current, and voltage of the storage capacitor 3c2 on the same time axis is shown. In the example of FIG. 7, the period of timing t20 to t21 immediately before the start of the integration period (timing t21 to t23) and the period of timing t22 to t23 immediately before the end of the integration period are set as the read stop period.

  By providing the read stop period at such timing, the variation of the element temperature with respect to the set temperature during the integration period can be further suppressed as compared with the case where the read stop period of one period as described above is provided. Therefore, as shown in FIG. 7, the element current in the integration period can be made closer to the ideal value, and as a result, the deviation of the voltage of the storage capacitor 3c2 from the ideal value can be significantly suppressed.

  5 to 7 occurs when the control signal generation circuit 6 stops the operation of the read circuit 4 for a certain period. The control signal generation circuit 6 generates a control signal that causes an operation stop period of the readout circuit 4 before or during the integration period of the current in the integration unit 3 c and supplies the control signal to the readout circuit 4.

FIG. 8 is a diagram illustrating an example of a control signal that causes the operation stop period of the readout circuit.
The output waveform from the amplifier circuit 5 on the same time axis, the horizontal clock (control signal) output from the control signal generation circuit 6, and the state of the gate voltage of the input transistor 3b are shown.

  In the output waveform, a wide pulse indicates a vertical blanking period, and a narrow pulse indicates a horizontal blanking period. A period between two vertical blanking periods is a reading period of pixel values of one frame. The integration period for determining the pixel value to be read out in the next frame is a period during which the gate voltage of the input transistor 3b is at the H level (timing t31 to t33).

  When the control signal generation circuit 6 receives the horizontal clock for driving the horizontal shift register 4b from the pulse generation circuit 11, as shown in FIG. 8, for example, during the period from timing t30 to t31 immediately before the integration period, Does not output the clock. Further, the control signal generation circuit 6 does not output a horizontal clock during a period of timing t32 to t33 immediately before the end of the integration period. As a result, regardless of the horizontal clock output from the pulse generation circuit 11, the horizontal shift register 4b stops, and a read stop period as shown in FIG. 7 occurs.

  When the horizontal shift register 4b is stopped, a pulse having a longer horizontal blanking period appears in the output waveform of the amplifier circuit 5, as in the periods of timing t30 to t31 and timing t32 to t33 in FIG. Since the output value is constant during this period, the amount of heat generated by the amplifier circuit 5 does not fluctuate, and fluctuations in the element temperature during the integration period are suppressed as described above.

Next, an example of the control signal generation circuit 6 that generates the control signal as shown in FIG. 8 is shown.
FIG. 9 is a diagram illustrating an example of the control signal generation circuit.
The control signal generation circuit 6 includes a delay circuit 30, an XOR circuit 31, an inverter circuit 32, and an AND circuit 33.

  The delay circuit 30 receives an integration signal for causing the pixel circuits 3-1 to 3-4 to integrate the element current from the pulse generation circuit 11, and delays it. The delayed integration signal is supplied to the gates of the XOR circuit 31 and the input transistors 3b of the pixel circuits 3-1 to 3-4.

The XOR circuit 31 receives the integration signal and the integration signal delayed by the delay circuit 30, and outputs an exclusive OR of both.
The inverter circuit 32 inverts the signal level of the output signal of the XOR circuit 31.

  The AND circuit 33 receives a horizontal clock from the pulse generation circuit 11 and also receives an output signal of the inverter circuit 32 and outputs a logical product of both. The output terminal of the AND circuit 33 is connected to the horizontal shift register 4b, and a control signal based on the logical product of the horizontal clock and the output signal of the inverter circuit 32 is supplied to the horizontal shift register 4b.

  Note that the delay time generated in the delay circuit 30 is based on the magnitude of the temperature fluctuation of the sensor 3a due to the heat fluctuation of the heat generating element including the amplifier circuit 5 when the pixel value is read. The cooling unit 14 is set according to the time for which the sensor 3a is set to the set temperature.

  For example, in the example of FIG. 5 described above, when the operation of the read circuit 4 is stopped at the timing t5, the element temperature becomes the set temperature at the timing t6. Therefore, the time from timing t5 to t6 is the time for the cooling unit 14 to set the sensor 3a to the set temperature when the operation of the readout circuit 4 is stopped. In the example of FIG. 6 described above, when the operation of the readout circuit 4 is stopped at the timing t9, the element temperature becomes the set temperature at the timing t10. Therefore, the time from timing t9 to t10 is the time for the cooling unit 14 to set the sensor 3a to the set temperature when the operation of the readout circuit 4 is stopped.

  The time during which the cooling unit 14 sets the sensor 3a to the set temperature is calculated according to the heat capacity of the cooling target including the sensor 3a, the performance of the cooling unit 14, and the magnitude of the temperature fluctuation of the sensor 3a with respect to the set temperature.

  For example, as shown in FIG. 2, in the cooling unit 14, the temperature of the stem 22 on which the cold shield 24 and the semiconductor integrated circuit 2 are mounted is adjusted by the temperature sensor 25 and the heater 26 under the control of the temperature regulator 27. Is done. The sum of the heat capacities of the semiconductor integrated circuit 2, the stem 22, the cold shield 24, the temperature sensor, and the heater 26 to be cooled is A (J / K), and the capacity of the heater 26 or the refrigerator 20 is B (W). At this time, the time T required to warm (or cool) the temperature of the semiconductor integrated circuit 2 by C (K) is T = A × C / B (sec).

  Therefore, for the delay time, the fluctuation range of the element temperature with respect to the set value of the cooling unit 14 is estimated from the fluctuation amount of the heat generation of the semiconductor integrated circuit 2, and is applied as “C” in the above equation, and the above equation is calculated. The approximate value is obtained.

The heat generation element is mainly the amplification circuit 5 (the heat generation amount is large), but there are other parts such as transistors 3e and 3f in the pixel circuits 3-1 to 3-4, for example.
FIG. 10 is a timing chart illustrating an example of the operation of the control signal generation circuit.

  From above, the integration signal output from the pulse generation circuit 11, the output signal of the delay circuit 30, the XOR circuit 31, and the inverter circuit 32, the horizontal clock output from the pulse generation circuit 11, and the control signal (the output signal of the AND circuit 33) It is shown.

  Until the timing t40, the integration signal, the output signals of the delay circuit 30 and the XOR circuit 31 are assumed to be L (Low) level, and the output signal of the inverter circuit 32 is assumed to be H level. Therefore, the control signal output from the AND circuit 33 is a horizontal clock.

  When the integration signal supplied from the pulse generation circuit 11 becomes H level at timing t40, the output signal of the XOR circuit 31 becomes H level and the output signal of the inverter circuit 32 becomes L level. Thereby, the control signal output from the AND circuit 33 becomes L level, the supply of the horizontal clock to the horizontal shift register 4b is stopped, and the reading of the pixel value by the reading circuit 4 is stopped.

  When the output signal of the delay circuit 30 becomes H level at the timing t41 delayed by the delay time described above from the timing t40, the output signal of the XOR circuit 31 becomes L level and the output signal of the inverter circuit 32 becomes H level. As a result, the control signal output from the AND circuit 33 becomes a horizontal clock, the horizontal shift register 4b starts operating, and the readout of the pixel value by the readout circuit 4 is resumed.

  When the integration signal becomes L level at timing t42, the output signal of the XOR circuit 31 becomes H level and the output signal of the inverter circuit 32 becomes L level. As a result, the control signal output from the AND circuit 33 becomes L level, the supply of the horizontal clock to the horizontal shift register 4b is stopped, and the reading of the pixel value by the reading circuit 4 is stopped again.

  When the output signal of the delay circuit 30 becomes H level at the timing t43 delayed by the delay time described above from the timing t42, the output signal of the XOR circuit 31 becomes L level and the output signal of the inverter circuit 32 becomes H level. As a result, the control signal output from the AND circuit 33 becomes a horizontal clock, the horizontal shift register 4b starts operating, and the readout of the pixel value by the readout circuit 4 is resumed.

  In the control signal generation circuit 6 as shown in FIG. 9, the output signal of the delay circuit 30 is supplied to the gate of the input transistor 3b, and the period during which the output signal is at the H level is the integration period. In the example of the timing chart of FIG. 10, the period between timings t41 and t43 is an integration period, and timings t40 to t41 before the start of the integration period and timings t42 to t43 before the end of the integration period are pixel value readout stop periods. .

  8 and 9, the example of the control signal generation circuit 6 that generates the control signal based on the horizontal clock among the signals for operating the horizontal shift register is shown, but the present invention is not limited to this. It is also possible to receive a data pulse input from the first data terminal of a plurality of flip-flop groups connected in series (not shown) of the horizontal shift register 4b from the pulse generation circuit 11 and generate the control signal as described above. A similar circuit is possible.

  FIG. 9 shows an example of the control signal generation circuit 6 that causes the operation stop period of the readout circuit 4 at the timing shown in FIG. 8, but the control signal generation circuit 6 operates before the integration period or during one period of the integration period. A circuit that causes the stop period can be realized by appropriately changing the circuit.

  As described above, one aspect of the semiconductor integrated circuit, the infrared imaging device, and the reading method of the present invention has been described based on the embodiments. However, these are merely examples, and the present invention is not limited to the above description.

  For example, in the above description, the control signal generation circuit 6 generates the control signal for stopping the operation of the horizontal shift register 4b in the readout circuit 4, but the control signal for stopping the operation of the vertical shift register 4a. May be generated. In that case, a circuit similar to that shown in FIG. 8 can be applied. That is, the control signal generation circuit 6 may receive a vertical clock or a data pulse for the vertical shift register 4a from the pulse generation circuit 11 and generate a control signal that causes an operation stop period of the vertical shift register 4a. Well, the same effect can be obtained.

  Further, the operation stop period is not limited to one or two locations, and three or more locations may be provided in reading one frame. However, if the operation stop period becomes longer, reading is affected, so it is desirable that the operation stop period be shorter.

Further, the control signal generation circuit 6 may not be provided in the semiconductor integrated circuit 2, and the pulse generation circuit 11 and the signal processing circuit 12 may be provided in the semiconductor integrated circuit 2.
The following additional notes are further disclosed with respect to the plurality of embodiments described above.

(Supplementary note 1) A plurality of sensors each including a sensor for supplying a current corresponding to the amount of incident infrared rays, an integration unit for integrating the current flowing through the sensor into a voltage value, and a holding unit for holding the converted voltage value. A pixel circuit of
A readout circuit that reads out a pixel value corresponding to a voltage value held in the holding unit from the plurality of pixel circuits;
An amplification circuit for amplifying pixel values read from the plurality of pixel circuits;
A control signal generation circuit that generates a control signal that causes an operation stop period of the readout circuit before or during the integration period of the current integration period in the integration unit;
A semiconductor integrated circuit comprising:

(Supplementary Note 2) The readout circuit includes a shift register,
The control signal generation circuit stops the operation of the shift register during the operation stop period regardless of a signal for operating the shift register before or during the integration period of the current integration period in the integration unit. The semiconductor integrated circuit according to appendix 1, characterized by:

(Supplementary Note 3) The readout circuit includes a horizontal shift register,
The control signal generation circuit is configured to operate the operation stop period regardless of a horizontal clock or a data pulse for the horizontal shift register that operates the horizontal shift register before or during the integration period of the current in the integration unit. 2. The semiconductor integrated circuit according to appendix 1, wherein the operation of the horizontal shift register is stopped.

  (Supplementary Note 4) The operation stop period includes a period from a first timing before the start of the integration period to a start timing of the integration period, and a timing from the second timing in the integration period to the end timing of the integration period. 4. The semiconductor integrated circuit according to any one of appendices 1 to 3, wherein the period is a period up to.

(Additional remark 5) The sensor which flows the electric current according to the amount of infrared rays of incident infrared rays, the integration part which integrates the electric current which flows into the said sensor, and converts it into a voltage value, The holding | maintenance part which hold | maintains the converted voltage value A plurality of pixel circuits comprising:
A readout circuit that reads out a pixel value corresponding to a voltage value held in the holding unit from the plurality of pixel circuits;
An amplification circuit for amplifying pixel values read from the plurality of pixel circuits;
A control signal generation circuit that generates a control signal that causes an operation stop period of the readout circuit before or during the integration period of the current integration period in the integration unit;
A cooling unit for cooling the sensor;
An infrared imaging device comprising:

  (Additional remark 6) The said operation stop period is based on the magnitude | size of the temperature fluctuation of the said sensor by the fluctuation | variation of the emitted-heat amount of the heat generating element containing the said amplifier circuit at the time of reading of these pixel values. The infrared imaging device according to appendix 5, wherein the cooling unit is set according to a time for which the sensor is set to a set temperature when the operation is stopped.

  (Additional remark 7) The time which the said cooling part makes the said sensor the said setting temperature is calculated according to the heat capacity of the cooling object containing the said sensor, the performance of the said cooling part, and the magnitude | size of the said temperature fluctuation with respect to the said setting temperature. The infrared imaging device according to appendix 6, wherein:

(Supplementary note 8) In accordance with the amount of infrared rays incident on a plurality of pixel circuits having a sensor, the current flowing through the sensor is integrated and converted into a voltage value, and the voltage value is held.
The pixel value corresponding to the held voltage value is read from the plurality of pixel circuits and amplified,
A readout method comprising: an operation stop period of a readout circuit that reads out the pixel value before or during the integration period of the current.

DESCRIPTION OF SYMBOLS 1 Infrared imaging device 2 Semiconductor integrated circuit 3-1 to 3-4 Pixel circuit 3a Sensor 3b Input transistor 3c Integration part 3c1, 3d1, 3d2, 3e, 3f, Tr1-Tr3 Transistor 3c2 Storage capacity 3d Holding part 3d3 Capacity 4 Reading circuit 4a Vertical shift register 4b Horizontal shift register 5 Amplifier circuit 6 Control signal generation circuit 7-1, 7-2 Vertical signal line 8-1, 8-2 Horizontal signal line 9 Output line 10 Lens unit 11 Pulse generation circuit 12 Signal processing circuit 13 Display device 14 Cooling unit

Claims (6)

A plurality of pixel circuits each including a sensor for passing a current corresponding to the amount of infrared rays of incident infrared rays, an integration unit for integrating the current flowing through the sensor into a voltage value, and a holding unit for holding the converted voltage value; ,
A readout circuit that reads out a pixel value corresponding to a voltage value held in the holding unit from the plurality of pixel circuits;
An amplification circuit for amplifying pixel values read from the plurality of pixel circuits;
A control signal generation circuit that generates a control signal that causes an operation stop period of the readout circuit before and during the integration period of the current integration period in the integration unit;
A semiconductor integrated circuit comprising: The readout circuit has a shift register,
The control signal generation circuit stops the operation of the shift register during the operation stop period regardless of a signal for operating the shift register before and during the integration period of the current in the integration unit. The semiconductor integrated circuit according to claim 1.   The operation stop period is a period from the first timing before the start of the integration period to the start timing of the integration period, and a period from the second timing in the integration period to the end timing of the integration period. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is provided. A plurality of pixels including a sensor that passes a current according to the amount of infrared rays incident thereon, an integration unit that integrates the current flowing through the sensor and converts the current into a voltage value, and a holding unit that holds the converted voltage value. Circuit,
A readout circuit that reads out a pixel value corresponding to a voltage value held in the holding unit from the plurality of pixel circuits;
An amplification circuit for amplifying pixel values read from the plurality of pixel circuits;
A control signal generation circuit that generates a control signal that causes an operation stop period of the readout circuit before and during the integration period of the current integration period in the integration unit;
A cooling unit for cooling the sensor;
An infrared imaging device comprising: The operation stop period, during the read of the multiple pixel values, on the basis of the magnitude of the temperature variation of the sensor due to the heat generation amount of the variation of the heat generation element including the amplifier circuit, when the operation stop of the readout circuit, The infrared imaging device according to claim 4, wherein the cooling unit is set according to a time for which the sensor is set to a set temperature. In accordance with the amount of infrared rays incident on a plurality of pixel circuits having a sensor, the current flowing through the sensor is integrated and converted into a voltage value, and the voltage value is held.
The pixel value corresponding to the held voltage value is read from the plurality of pixel circuits and amplified,
A readout method comprising: an operation stop period of a readout circuit that reads out the pixel value before and during the integration period of the current.

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