JP5901461B2 - Optical transmission apparatus and optical transmission method - Google Patents

Description

  The present invention relates to an optical transmission device and an optical transmission method.

  For example, an optical transmission apparatus that performs optical signal modulation in consideration of an optical phase such as conventional QPSK (Quadrature Phase Shift Keying), for example, splits transmission light into two, and modulates the intensity with different optical modulation units, respectively. In this configuration, one modulated light is delayed and combined with the other so that their phases are orthogonal to each other. At this time, the delayed signal is called a Qch (Quadrature-phase Channel) signal, and the other is called an Ich (In-phase Channel) signal.

  In the optical transmission device configured as described above, when a skew of a symbol period or less occurs between the input signal to the Ich optical modulation unit and the input signal to the Qch optical modulation unit, the eye pattern at the time of demodulation is closed. Transmission quality deteriorates. In addition, even when skew occurs in symbol cycle units, for example, when differential encoding is performed, it is difficult to restore data during demodulation. Therefore, conventionally, a skew control between the Ich input signal and the Qch input signal is suppressed by providing a clock timing and phase delay control mechanism.

  On the other hand, in recent years, in order to transmit a large amount of data, a circuit that generates an electric signal to be input to the optical modulation unit has a high-speed and large-scale circuit configuration. In such a circuit configuration, signal timing design becomes strict, and various signal processing circuits are integrated into one integrated circuit for processing.

  For example, in Patent Document 1, a circuit until two modulation signals for Ich and Qch obtained by multiplexing parallel input signals using a multiplexer and converting them into serial signals is output to an optical modulator with a single integrated circuit. ing. In this integrated circuit, as a method of suppressing skew generated between Ich and Qch in the electric transmission path from the signal input to the optical modulator, the clock for driving the Ich and Qch multiplexers is set from the outside in the integrated circuit. How to adjust is shown. Here, a first-in first-out (FIFO) buffer is used to absorb the shift between the phase of the multiplexer driving clock and the phase of the multiplexer input data. In addition, there is shown a method of simultaneously resetting the multiplexers of these two channels in order to synchronize the clock timing between Ich and Qch.

Special table 2010-539818 gazette

  The technique described in Patent Document 1 has a small circuit scale because the circuit to be integrated mainly performs only multiplexing processing, and it is possible to realize both the Ich and Qch processing circuits with a single integrated circuit. Is possible. However, when the intensity information of the Ich signal and Qch signal is multi-valued, such as 16QAM (Quadrature Amplitude Modulation), it corresponds to each input bit of a large-scale arithmetic processing circuit, high-speed DA converter, and DA converter. Such a parallel multiplexing circuit is required. Therefore, it is difficult to realize two signal processes for Ich and Qch with a single integrated circuit because the circuit scale and power consumption increase.

  For this reason, it is conceivable to configure Ich and Qch by two different integrated circuits. In this case, it is necessary to perform timing control in two integrated circuits.

  Here, in the multilevel optical QAM, the optical modulator controls the intensity and phase of light by a combination of Ich and Qch optical signals, and includes information in the multilevel signal points. In this case, the timing control between the two integrated circuits is controlled so that the relationship between the modulation signals of Ich and Qch always becomes the intended relationship until each clock timing reaches a phase of the clock period or less. Is strongly demanded.

  Also, in a circuit that performs QAM differential encoding processing, the input data processed by each channel processing circuit needs to be the same. Therefore, it is also necessary to synchronize the timing of signal processing and waveform output between the two integrated circuits.

  In order to perform these timing controls, for example, if the reference clock is shared, the FIFO buffer, clock division, etc. operate independently, so that the Ich output and Qch output signal processing is not intended for clock timing. May be executed. In addition, when a difference in internal delay occurs between two integrated circuits due to temperature fluctuation, a delay equal to or shorter than the clock cycle occurs, and the optical signal cannot be appropriately modulated, resulting in a deterioration in transmission quality.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an optical transmission apparatus and the like that can transmit large-capacity data and has high transmission quality and resistance to environmental fluctuations.

In order to achieve the above object, an optical transmission device of the present invention includes:
An optical modulator that multiplexes and outputs optical signals that are respectively optically modulated by two or more modulation units using two or more modulation signals;
Two or more modulation signal generation circuits for generating two or more modulation signals based on an externally input main signal and a main signal parallel clock;
An optical transmission device comprising: a delay control circuit that generates two or more reference signal clocks that have been subjected to phase delay adjustment with respect to an externally input reference reference clock, and outputs the reference signal clock to each of the two or more modulation signal generation circuits Because
Modulation signal generating circuit,
A clock generator for generating a multiplied clock and divided clock the 逓 time clock obtained by dividing obtained by multiplying the synchronous criteria signal clock standards signal clock are entered from the delay control circuit,
Write data from an external input Ru main signal in the memory by the main signal parallel running clock, and data reading unit for reading the data written to the memory by the standards signal clock,
The criteria signals clock or operate using 逓 time clock or the divided clock to generate a modulated signal to enter the modulation unit based on the data of the main signals read from the data reading unit A modulation signal generation processing unit,
Delay control circuit, each 2 or more modulation signal generation circuit clock generator compares the divided clock of the phase that generates two or more Ri by the delaying controlled to be in phase with each other Generate a reference signal clock,
It is characterized by that.

  According to the present invention, it is possible to transmit a large amount of data while maintaining high transmission quality and resistance to environmental fluctuations.

It is a block diagram which shows the structure of an optical transmitter in embodiment. It is a block diagram which shows the internal structure of an optical modulator. It is a block diagram which shows the internal structure of a modulation signal generation circuit. It is a block diagram which shows the internal structure of a delay control circuit. It is a block diagram which shows the internal structure of CMU. It is a figure which shows the input / output signal of MUX. It is a figure which shows the digital signal waveform of the input / output data of MUX.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

As shown in FIG. 1, the optical transmitter 1 according to this embodiment includes an optical modulator 10, a modulation signal generation circuit 20-1, a modulation signal generation circuit 20-2, a delay control circuit 30, an amplifier 40-1, 40-2. Here, components having the same numerals before “−” (Hai Phong) have substantially the same configuration. In the following description, components having the same numerals before “−” are denoted by “−”. ”May be omitted for explanation. The optical transmitter 1 receives a reference reference clock, a 2 ^L- bit parallel main signal and a main signal parallel clock that are frequency-synchronized with the reference reference clock, and outputs an optical signal. Note that L is an arbitrary natural number.

  The modulation signal generation circuit 20-1 is driven by the main signal parallel clock and the reference signal clock input from the delay control circuit 30, and generates an Ich (In-phase-channel) modulation signal based on the parallel main signal input. The signal amplified by the amplifier 40-1 is output to the optical modulator 10.

  Similarly, the modulation signal generation circuit 20-2 is driven by the main signal parallel clock and the reference signal clock input from the delay control circuit 30, and generates a Qch (Quadrature-channel) modulation signal based on the parallel main signal input. The signal amplified by the amplifier 40-2 is output to the optical modulator 10.

  The parallel main signal, main signal parallel clock, read reset signal, and write reset signal input to the two modulation signal generation circuits 20-1 and 20-2 may be inputs from different signal systems, respectively. One input may be divided into two.

The delay control circuit 30, ^{2 N} divided clock which is ^{2 N} dividing the multiplied clock to be outputted from the modulation signal generating circuit 20-1 and 20-2 are input. The delay control circuit 30 compares the phase of the input ^2N frequency-divided clock, and based on the result, a reference signal that allows each of the multiplied clocks to be in phase and output the Ich modulation signal and the Qch modulation signal at the same timing Generate and output a clock. The modulation signal generation circuits 20-1 and 20-2 output an Ich modulation signal and a Qch modulation signal, respectively, at the timing of the multiplied clock generated based on the reference signal clock.

  As shown in FIG. 2, the optical modulator 10 includes a light source 101, an optical coupler 102 that splits light, an Ich modulator 103, a Qch modulator 104, a delay unit 105, and an optical coupler 106 that optically multiplexes. An Ich modulation signal generated and amplified by the modulation signal generation circuit 20-1 is input to the Ich modulation unit 103, and an Qch modulation signal generated and amplified by the modulation signal generation circuit 20-2 is input to the Qch modulation unit 104. Is done.

  The optical signal output from the light source 101 is branched into two by the optical coupler 102 and input to the Ich modulation unit 103 and the Qch modulation unit 104. The light input to the Ich modulation unit 103 and the Qch modulation unit 104 is intensity-modulated with an Ich modulation signal and a Qch modulation signal, respectively. The optical signal modulated by the Qch modulation unit 104 is delayed by a quarter wavelength by the delay unit 105. That is, the phase is adjusted such that the phase difference between the signal output from the Ich modulation unit 103 and the signal output from the delay unit 105 is 90 °. Then, the signal output from the Ich modulation unit 103 and the signal output from the delay unit 105 are combined by the optical coupler 106. The combined optical signal is an optical QAM (Quadrature Amplitude Modulation) signal obtained by multiplexing Ich signal components and Qch signal components orthogonal to each other. In this embodiment, a 16QAM signal having 16 signal points is used.

  As shown in FIG. 3, the modulation signal generation circuits 20-1 and 20-2 include a CMU (Clock Multiplier Unit) 210, a FIFO (First-in First-out Buffer) 211, and a mapper processing unit. 212, M MUXs (Multiplexers) 213-1 to M, and DACs (Digital-Analog Converters) 214. Here, for example, the mapper processing unit 212 of the modulation signal generation circuit 20-1, the M MUXs 213-1 to M, and the DAC 214 function as a modulation signal generation processing unit for generating an Ich modulation signal, and the modulation signal generation circuit The 20-2 mapper processing unit 212, M MUXs 213-1 to M, and DAC 214 function as a modulation signal generation processing unit for generating a Qch modulation signal. M is an arbitrary natural number. For example, when the modulation method is 16QAM, the natural number is 2 or more.

The CMU 210 generates a ^2N- times multiplied clock that is synchronized with the reference signal clock input from the delay control circuit 30 and a divided clock obtained by dividing the multiplied clock. The FIFO 211 and the mapper processing unit 212 are driven by the reference signal clock, the MUXs 213-1 to M are driven by the divided clock, and the DAC 214 is driven by the multiplied clock. N is an arbitrary natural number.

  The parallel main signal data input to the modulation signal generation circuit 20 is stored in the internal memory of the FIFO 211 using the main signal parallel clock as a write clock. Then, the parallel main signal data stored in the internal memory is read using the reference signal clock as a read clock. By passing through the FIFO 211, the parallel main signal is output in a state where the phase shift between the main signal parallel clock and the reference signal clock is absorbed.

The parallel main signal output from the FIFO 211 is input to the mapper processing unit 212. The mapper processor 212 calculates a parallel Ich signal component or a parallel Qch signal component of the 16QAM signal based on the input parallel main signal, and outputs a 2 ^N- bit low-speed parallel signal as a calculation result to each of the MUXs 213-1 to M. Output.

  The low-speed parallel signals input to each of the MUXs 213-1 to M are time-multiplexed, that is, parallel / serial converted, in the MUXs 213-1 to M. The M series serial signals obtained by time multiplexing by the MUXs 213-1 to M are subjected to digital / analog conversion by the DAC 214, and the obtained analog signals are output as Ich modulation signals or Qch modulation signals.

As shown in FIG. 4, the delay control circuit 30 includes a phase comparator 301, a delay unit 302, and an amplifier 303. The delay control circuit 30, and reference reference clock, and ^{2 N} divided clock output from CMU210 of the modulation signal generating circuit 20-1, ^{2 N} divided clock output from CMU210 of the modulation signal generating circuit 20-2 Is entered. The delay control circuit 30 outputs a signal obtained by amplifying the reference reference clock by the amplifier 303 to the modulation signal generation circuit 20-2 as a Qch reference signal clock.

And ^{2 N} divided clock output from CMU210 of the modulation signal generating circuit 20-1, ^{2 N} divided clock output from CMU210 of the modulation signal generating circuit 20-2 are input to the phase comparator 301, compares the phases The result is output to the delay unit 302. The delay unit 302 outputs a signal obtained by shifting the phase of the reference reference clock by a phase corresponding to the phase shift of both ^2N frequency-divided clocks to the modulation signal generation circuit 20-1 as an Ich reference signal clock.

Thus, based on the respective reference signal clocks, the CMU circuits 210 of the respective modulation signal generation circuits 20-1 and 20-2 generate the multiplied clocks and the respective divided clocks, and the generated ^2N divided clocks are generated. The phase is fed back to the phase comparator of the delay control circuit 30 for phase control. By this control, the multiplied clocks that control the timing of the output signals of the modulation signal generation circuit 20-1 and the modulation signal generation circuit 20-2 are in phase.

  That is, the delay control circuit 30 automatically adjusts the delay even when the delay from the reference signal clock of the modulation signal generation circuits 20-1 and 20-2 to the CMU output fluctuates due to thermal fluctuation and other component performance variations. Therefore, the output signals of the modulation signal generation circuits 20-1 and 20-2 are always in phase.

  Hereinafter, each component of the modulation signal generation circuit 20 will be described in detail.

As shown in FIG. 5, the CMU 210 includes N number of frequency dividers 2101-1 to 2101-1 to N, a phase frequency comparator 2102, and a VCO (Voltage Controlled Oscillator) 2103. The CMU 210 generates a ^2N times multiplied clock with respect to the inputted reference signal clock by the VCO 2103 and outputs it. Further, the multiplied clock by sequentially divided by two by two frequency divider 2101-1～N, ^{2 1-divided} clock, ^{2 2} divided clock, ... generate ^{2 N} divided clock, N-bit parallel signals The divided clock is output.

The reference signal clock and the ^2N frequency-divided clock are input to the phase frequency comparator 2102, and the phase and frequency of the two clocks are compared to perform feedback control on the VCO 2103 that generates the multiplied clock. That is, the CMU 210 is configured by a PLL that receives the reference signal clock, so that the phase of the multiplied clock and the ^2N divided clock is synchronized with the reference signal clock, and the frequency of the ^2N divided clock is the reference signal. It is controlled to be the same as the clock frequency. ^{2 N} divided clock generated by CMU210 is also output to the outside of the modulation signal generating circuit 20.

  The FIFO 211 includes a memory, a counter that holds a memory write address, and a counter that holds a memory read address. The FIFO 211 receives a read reset signal for resetting a read address counter and a write reset signal for resetting a write address counter.

  When the parallel main signal is input, the FIFO 211 stores the data of the parallel main signal in the memory using the main signal parallel clock as the write clock from the address indicated by the write address counter. Further, the data stored in the memory is read from the address indicated by the read address counter, and the reference signal clock is read and read.

  Here, normally, the main signal parallel clock of the write clock and the reference signal clock of the read clock are frequency-synchronized with the reference reference clock, but when the transmitter power is turned on, the frequency of each clock, Since the phase is unstable, the address states of the FIFO 211 of the modulation signal generation circuit 20-1 and the modulation signal generation circuit 20-2 are not always the same.

  Therefore, after the frequency of the external reference clock, the main signal parallel clock, and the reference signal clock is stabilized, the read reset signal and the write reset are simultaneously performed on the FIFO 211 of the modulation signal generation circuit 20-1 and the modulation signal generation circuit 20-2. A signal is input. For example, a read reset signal and a write reset signal may be input to both modulation signal generation circuits 20 after a preset time from power-on.

  As a result, the address states of the FIFO 211 of the modulation signal generation circuit 20-1 and the modulation signal generation circuit 20-2 match, and the modulation signal generation circuit 20-1 and the modulation signal generation circuit 20-2 have the same clock timing on the system. Data can be read from the FIFO 211.

The mapper processing unit 212 maps low-speed parallel signals to the MUXs 213-1 to M so that a modulation signal for generating a 16QAM signal is output from the DAC 214 by being input to the modulation unit of the optical modulator 10. It has a function. Specifically, the mapper processing unit 212 of the modulation signal generation circuit 20-1 inputs an Ich modulation signal that can generate a 16QAM signal by being input to the Ich modulation unit 103 of the optical modulator 10 into the modulation signal generation circuit 20. -1 to generate a low-speed parallel signal to be output from the DAC 214. Also, the mapper processing unit 212 of the modulation signal generation circuit 20-2 inputs a Qch modulation signal that can be generated into a 16QAM signal by being input to the Qch modulation unit 104 of the optical modulator 10 into the modulation signal generation circuit 20-2. A low-speed parallel signal to be output from the DAC 214 is generated.

Here, since the modulation signal output from the DAC 214 is an analog signal indicating an M-bit amplitude value with respect to the sample time of the DAC 214, the mapper processing unit 212 performs the DAC 214 based on the data read from the FIFO 211. The data corresponding to the 1 to ^M bits input to is calculated as 2 ^N- bit low-speed parallel signals and output to the MUXs 213-1 to M, respectively.

  The number of steps required for the calculation in the mapper processing unit 212 is the same in the modulation signal generation circuit 20-1 and the modulation signal generation circuit 20-2, and the output timing to the MUXs 213-1 to M in the subsequent stage is the same clock timing.

The MUXs 213-1 to M time-multiplex the 2 ^N- bit low-speed parallel signals output from the mapper processing unit 212, convert the signals into serial signals, and output the serial signals. MUX213 is composed of multiple circuits of a plurality of stages, a clock for driving each multiplexing circuit 2,4,8 ... output from CMU210, a ^{2 N} divided clock. MUX213, as shown in FIG. 6, ^{2 N} input ports from ^{2 N} bits of the low-speed parallel signal (1) ~ ^{(2 N)} is input, the divided clock is input from the N input ports, serial signal Is output.

The input / output data of the MUX 213 will be described with reference to the digital signal waveform diagram of FIG. Counter values 0 to 2 ^N −1 can be acquired from the signal states of the divided clocks of the N ports.

The MUX 213 outputs any one of the low-speed parallel signals (1) to (2 ^N ) at the rising and falling timings of the divide-by-2 clock. Among the low-speed parallel signal input, Which signal is output, first, a 2 ^N divided clock as MSB (Most Significant bit), with the initial value when the fall or rise of 2 ^N divided clock, the division The clock values are sequentially selected corresponding to the counter value indicated by the clock value. That is, the MUX 213 outputs the low-speed parallel signal (1) when the total frequency-divided clock is 0 and the counter value is 0, and outputs the next low-speed parallel signal every time the counter value increases by 1. .

Here, in both the modulation signal generating circuit 20-1 of the modulation signal generating circuit 20-2 also, the phase frequency comparator 2102 CMU210, feeding back the results of comparing ^{2 N} divided clock and the phase of the reference clock Therefore, each of the divided clocks is controlled so as to be synchronized with the reference signal clock. Therefore, the counter values of the modulation signal generation circuit 20-1 and the modulation signal generation circuit 20-2 are also synchronized, and each MUX 213 is output. The same clock timing is also guaranteed.

  The DAC 214 is driven by a multiplied clock signal generated by the CMU 210 and outputs an analog electrical waveform corresponding to the output of the M columns MUX 213-1 to M input. That is, the analog intensity signal indicating the M-bit amplitude value output from the DAC 214 is the modulation signal. Since the multiplication clock that drives the DAC 214 of the modulation signal generation circuit 20-1 and the modulation signal generation circuit 20-2 is controlled to be in phase with the reference signal clock, the modulation signal generation circuit 20-1 and the modulation signal generation The Ich modulation signal and Qch modulation signal output from the circuit 20-2 are output in phase.

As described above, according to the present embodiment, the delay control circuit so that the ^2N frequency-divided clock output from the CMU 210 is in phase between the modulation signal generation circuit 20-1 and the modulation signal generation circuit 20-2. the reference signal clock that is delayed adjusted in 30, CMU210 by using a 2 ^N multiplying divided clock multiplication clock and multiplied clock obtained by dividing the the Ich modulation signal and Qch modulation signal, modulation signal generating circuit 20- 1 and the modulation signal generation circuit 20-2 are respectively operated and output. Thereby, even when the delay from the reference signal clock input to the CMU 210 output of the modulation signal generation circuits 20-1 and 20-2 fluctuates due to thermal fluctuation and other component performance variations, the delay control circuit 30 automatically delays. By adjusting, the output signals of the modulation signal generation circuits 20-1 and 20-2 are always in phase.

  In addition, the write address counter and the read address counter of the FIFO 211 are simultaneously reset by the modulation signal generation circuit 20-1 and the modulation signal generation circuit 20-2. As a result, the address states of the FIFO 211 of the modulation signal generation circuit 20-1 and the modulation signal generation circuit 20-2 match, data can be read from the FIFO 211 at the same clock timing, and a modulation signal can be generated based on the data. .

  As described above, according to the present invention, in two or more modulation signal generation circuits to which a reference signal clock having a phase delay adjusted with respect to the reference reference clock is input, a multiplied clock obtained by multiplying the reference signal clock and a multiplied clock are separated. High-quality transmission by calculating and outputting modulated signals using the divided clocks, and combining and transmitting optical signals that have been optically modulated by two or more modulation units using the modulated signals. In addition, large-capacity data having resistance to environmental fluctuations can be optically transmitted.

  In addition, this invention is not limited to the said embodiment, Of course, the various change in the range which does not deviate from the summary of this invention is possible.

  For example, in the above embodiment, the mapper processing unit 212 performs the waveform calculation of the 16QAM optical signal, but the present invention is not limited to this, and QPSK (Quaternary Phase-Sift Keying), 8PSK (8 Phase-Sift) Keying) and 32QAM may be used to calculate the waveform of an optical modulation signal using a modulation scheme other than 16QAM. In addition, although the two modulation signal generation circuits 20 for calculating the modulation signal are provided, the number of the modulation signal generation circuits 20 is not limited to two and may be any number greater than or equal to two. When a modulation scheme such as QPSK or 8PSK is used, it is possible to transmit a larger amount of data by providing a modulation signal generation circuit according to the number of modulation units that output optical signals whose phases are shifted.

  In addition, when using the polarization multiplexing modulation method, it is necessary to synchronize the timing between the X-polarization modulation signal and the Y-polarization modulation signal, so that the waveform calculation of the X-polarization modulation signal is generated as a modulation signal. The synchronization may be obtained by performing the waveform calculation of the Y-polarized modulation signal in the circuit 20-1 and performing the waveform calculation in the modulation signal generation circuit 20-2. In the case of combining polarization multiplexing modulation and QAM or phase modulation, synchronization may be achieved using four modulation signal generation circuits.

  In addition, when a modulator configuration using a main signal modulation unit and a pulse shaping modulation unit is employed, timing synchronization must be established between the pulse shaping modulation signal and the main signal modulation signal. The modulation of the modulation signal of the signal modulation unit is performed by the modulation signal generation circuit 20-1, and the modulation of the modulation signal of the modulation unit for pulse shaping is performed by the modulation signal generation circuit 20-2. You may do it.

  Further, as the waveform calculation processing in the mapper processing unit 212, calculation of intensity compensation or phase compensation corresponding to transmission path characteristics such as transmission signal pre-emphasis may be performed. When phase compensation is performed as a waveform calculation process, compensation by combining the Ich and Qch signals by synchronizing the timings of the Ich and Qch signals is necessary even for binary modulation schemes such as OOK and BPSK. The invention can be applied. In this case, the waveform calculation of the Ich modulation signal is performed by the modulation signal generation circuit 20-1, and the waveform calculation of the Qch modulation signal is performed by the modulation signal generation circuit 20-2.

  The present invention is also applicable when optical OFDM is used as the modulation method. The present invention may be applied to the synchronization between the Ich and Qch signals in the case where modulation is performed using a signal in which subcarrier multiplexing is electrically performed on a single wavelength optical carrier. At this time, the modulation operation of the Ich modulation signal is performed by the modulation signal generation circuit 20-1, and the modulation operation of the Qch modulation signal is performed by the modulation signal generation circuit 20-2. Can be output.

  In order to realize optical OFDM, the present invention is applied to the synchronization of a modulation signal that modulates each subcarrier light using the present invention when a method of modulating a plurality of subcarrier lights with different modulation units is used. May be. In the case of this method, the plurality of modulation signal generation circuits 20 output a modulation signal for modulating each subcarrier light, so that the optical modulation unit outputs an optical OFDM signal. Similarly, in order to realize optical OFDM, the present invention may be applied between modulated signals that modulate subcarriers even when a method of modulating an optical carrier with a signal that modulates a plurality of electrical subcarriers is used. . In the case of these methods, the plurality of modulation signal generation circuits 20 output modulation signals for modulating each electric subcarrier, so that the optical modulation unit outputs an optical OFDM signal.

The delay control circuit 30 may be configured to add an offset to the delay amount of the delay unit 302. This makes it possible to compensate for skew from the modulation signal generation circuits 20-1 and 20-2 to the Ich modulation unit 103 and the Qch modulation unit 104 .

  In addition, the optical modulator 10 divides the output light of the light source 101 into two, modulates each of them, and multiplexes them after delaying one of them by 90 °. However, the configuration of the optical modulator 10 is not limited to this, and is arbitrary. Configuration may be sufficient. For example, the delay unit 105 may be inserted before the Qch modulation unit 104.

DESCRIPTION OF SYMBOLS 1 Optical transmitter 10 Optical modulator 101 Light source 102 Optical coupler 103 Ich modulation part 104 Qch modulation part 105 Delay part 106 Optical coupler 20, 20-1, 20-2 Modulation signal generation circuit 210 CMU
2101-1 to N 2 frequency divider 2102 phase frequency comparator 2103 VCO
211 FIFO
212 Mapper processing unit 213, 213-1 to M MUX
214 DAC
30 delay control circuit 301 phase comparator 302 delay unit 303 amplifier 40-1, 40-2 amplifier

Claims (11)

An optical modulator that multiplexes and outputs optical signals that are respectively optically modulated by two or more modulation units using two or more modulation signals;
Two or more modulation signal generation circuits for generating the two or more modulation signals based on a main signal inputted externally and a main signal parallel clock;
An optical transmission comprising: a delay control circuit that generates two or more reference signal clocks that are phase-adjusted with respect to an externally input reference reference clock, and outputs the reference signal clock to each of the two or more modulation signal generation circuits. A device,
The modulation signal generation circuit includes:
A clock generation unit that generates a multiplied clock obtained by multiplying the reference signal clock in synchronization with the reference signal clock input from the delay control circuit and a divided clock obtained by dividing the multiplied clock;
A data reading unit for writing the data of the main signal inputted externally into the memory by the main signal parallel clock, and reading out the data written in the memory by the reference signal clock;
A modulation signal that operates using the reference signal clock, the multiplied clock, or the frequency-divided clock, and generates the modulation signal to be input to the modulation unit based on the data of the main signal read from the data reading unit A generation processing unit,
The delay control circuit compares the two or more of the divided clock phases of the clock generator of the modulation signal generating circuit respectively generates, of the two or more by the delay control so that the same phase with each other Generate a reference signal clock,
An optical transmitter characterized by the above. The main signal input to the modulation signal generation circuit is a parallel signal,
The modulation signal generation processing unit of the modulation signal generation circuit,
Mapper processing means that operates with the reference signal clock and maps the main signal output from the data reading unit to a plurality of parallel output signals that are slower than the main signal;
A plurality of time multiplexing means for outputting a plurality of time multiplexed signals obtained by time-multiplexing each of the plurality of parallel output signals output from the mapper processing means by the divided clock generated by the clock generation unit;
A DA converter that converts the plurality of time-multiplexed signals into the modulation signal of the analog signal input to the modulation unit using the multiplied clock output from the clock generation unit;
The optical transmitter according to claim 1. The data reading unit has means for resetting a write address indicating a write start position and a read address indicating a read start position;
Simultaneously resetting the write address of the data read section of the two or more modulation signal generation circuits, and simultaneously resetting the read address of the data read section of the two or more modulation signal generation circuits;
The optical transmission device according to claim 1, wherein the optical transmission device is an optical transmission device. The optical modulator includes a modulation unit that modulates an Ich optical signal and a modulation unit that modulates a Qch optical signal having a predetermined phase difference from the Ich, and the two or more modulation signal generation circuits include a first modulation signal The first modulation signal generation circuit includes a signal generation circuit and a second modulation signal generation circuit, the first modulation signal generation circuit outputs a modulation signal that modulates the Ich optical signal, and the second modulation signal generation circuit includes the Qch optical signal. By outputting a modulation signal that modulates the signal, the optical modulator performs optical intensity and optical phase modulation;
The optical transmission device according to claim 1, wherein the optical transmission device is an optical transmission device. The optical modulator includes a modulation unit that modulates an X polarization of an optical signal and a modulation unit that modulates a Y polarization, and the two or more modulation signal generation circuits include a first modulation signal generation circuit and a second modulation signal. Including two generation circuits, wherein the first modulation signal generation circuit outputs a modulation signal that modulates the X polarization, and the second modulation signal generation circuit outputs a modulation signal that modulates the Y polarization. The optical modulator outputs a polarization multiplexed modulated optical signal,
The optical transmission device according to claim 1, wherein the optical transmission device is an optical transmission device. The optical modulator includes a modulation unit that modulates a main signal of an optical signal and a modulation unit that performs optical pulse shaping. The two or more modulation signal generation circuits include a first modulation signal generation circuit and a second modulation signal generation circuit. The first modulation signal generation circuit outputs a modulation signal that modulates the main signal of the optical signal, and the second modulation signal generation circuit outputs a modulation signal that performs optical pulse shaping, thereby The optical modulator outputs a pulse-shaped optical signal,
The optical transmission device according to claim 1, wherein the optical transmission device is an optical transmission device. The optical modulator includes a modulation unit that modulates an Ich optical signal and a modulation unit that modulates a Qch optical signal having a predetermined phase difference from the Ich, and the two or more modulation signal generation circuits include a first modulation signal Including a signal generation circuit and a second modulation signal generation circuit, wherein the first modulation signal generation circuit performs phase compensation corresponding to the characteristics of the transmission path, and outputs a modulation signal for modulating the optical signal of the Ich, The second modulation signal generation circuit outputs a modulation signal for modulating the optical signal of the Qch, which performs phase compensation corresponding to the characteristics of the transmission path, so that the optical modulator performs optical intensity and optical phase modulation, Outputs an optical signal whose phase is compensated for the characteristics of the transmission line.
The optical transmission device according to claim 1, wherein the optical transmission device is an optical transmission device. The optical modulator includes a modulation unit that modulates an Ich optical signal and a modulation unit that modulates a Qch optical signal having a predetermined phase difference from the Ich, and the two or more modulation signal generation circuits include a first modulation signal The first modulation signal generation circuit includes a signal generation circuit and a second modulation signal generation circuit, the first modulation signal generation circuit outputs a modulation signal that modulates the optical signal of the Ich of the OFDM signal, and the second modulation signal generation circuit includes the OFDM By outputting a modulation signal that modulates the Qch optical signal of the signal, the optical modulator performs optical intensity and optical phase modulation, and outputs an optical OFDM signal.
The optical transmission device according to claim 1, wherein the optical transmission device is an optical transmission device. The optical modulator includes a modulation unit that modulates each of a plurality of optical subcarriers, and the two or more modulation signal generation circuits each output a modulation signal that modulates each optical subcarrier. Outputting an optical OFDM signal obtained by combining modulated optical subcarriers;
The optical transmission device according to claim 1, wherein the optical transmission device is an optical transmission device. The optical modulator includes: an electric modulation unit that modulates each of a plurality of electric subcarriers, combines and outputs the modulated electric signal; and an optical modulation unit that performs optical modulation according to an output of the electric modulation unit, Two or more modulation signal generation circuits output a modulation signal for modulating each electric subcarrier, so that the optical modulator outputs an optical OFDM signal.
The optical transmission device according to claim 1, wherein the optical transmission device is an optical transmission device. Based on an optical modulator that multiplexes and outputs optical signals that are respectively optically modulated by two or more modulation units with two or more modulation signals, and a main signal that is externally input and a main signal parallel clock, the 2 An optical transmission method using two or more modulation signal generation circuits for generating the above modulation signals,
A reference signal clock generation step of generating two or more reference signal clocks that have been subjected to phase delay adjustment with respect to an externally input reference reference clock, and outputting the reference signal clock to each of the two or more modulation signal generation circuits;
A clock generation step of generating a multiplied clock obtained by multiplying the reference signal clock and a divided clock obtained by dividing the multiplied clock in synchronization with the reference signal clock input to each of the two or more modulation signal generation circuits;
A data read step of writing the data of the main signal to the memory included in each of the two or more modulation signal generation circuits by the main signal parallel clock and reading the data written in the memory by the reference signal clock;
A modulation signal generation processing step for generating the modulation signal based on the data of the main signal read in the data read step using the reference signal clock, the multiplied clock, or the divided clock; ,
The reference signal clock generating step compares the divided clock of the phase generated in the clock generating step in each of the two or more modulation signal generating circuit, the two or more delayed adjusted to be in phase with each other Generate a reference signal clock,
An optical transmission method.

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