JP5901913B2 - Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device - Google Patents

Description

  The technical field relates to a method for manufacturing a semiconductor substrate and a method for manufacturing a semiconductor device using the semiconductor substrate.

  In recent years, an SOI (Silicon On Insulator) substrate in which an insulating layer and a single crystal silicon layer are provided over a supporting substrate (also referred to as a base substrate) has been widely used as a semiconductor substrate. A typical manufacturing process of an SOI substrate will be described below.

  First, hydrogen ions are implanted into a single crystal silicon substrate to form a damaged region (also referred to as an embrittlement layer) at a predetermined depth from the surface of the single crystal silicon substrate. Next, the single crystal silicon substrate is bonded to a supporting substrate through an insulating layer. After that, heat treatment is performed and the single crystal silicon substrate is divided (also referred to as separation) from the damaged region, whereby an insulating layer and a thin single crystal silicon layer can be formed over the supporting substrate. That is, an SOI substrate is manufactured by transferring a single crystal silicon layer formed of a part of a single crystal silicon substrate onto a support substrate.

Furthermore, a technique for increasing the thickness of the single crystal silicon layer has been studied from the viewpoint of improving the breakdown voltage.
(For example, refer to Patent Document 1).

  In Patent Document 1, a silane-based gas is supplied as a raw material to the surface of a formed single crystal silicon layer, and a single crystal silicon layer is formed by a CVD method. So-called vapor phase epitaxial growth is performed to thicken the single crystal silicon layer.

JP 2000-30995 A

  In the method described in Patent Document 1, since the crystallinity and flatness of the single crystal silicon substrate are impaired by the implantation of hydrogen ions, a defect occurs in the single crystal silicon layer after transfer.

  In addition, the method described in Patent Document 1 has a problem in that mass productivity is low because it is difficult to improve the deposition rate in vapor phase epitaxial growth.

  Thus, an object is to reduce defects in a single crystal semiconductor layer after transfer and to increase the thickness of a semiconductor substrate.

  Another object is to improve mass productivity of a semiconductor substrate or a semiconductor device.

  In the disclosed manufacturing method, after an amorphous semiconductor layer is formed over a single crystal semiconductor substrate, the single crystal semiconductor substrate and a supporting substrate are attached to each other with an insulating layer interposed therebetween, and a part of the single crystal semiconductor substrate is non-coated. Reprinted on the supporting substrate together with the crystalline semiconductor layer. Then, a thick single crystal semiconductor layer is formed over the supporting substrate by solid phase epitaxial growth (also referred to as solid phase growth) of the amorphous semiconductor layer.

  One embodiment of the present invention includes a step of forming an amorphous semiconductor layer over a single crystal semiconductor substrate, a step of irradiating the single crystal semiconductor substrate with ions to form a damaged region, A semiconductor having a step of bonding to a supporting substrate through a crystalline semiconductor layer and an insulating layer, a step of performing heat treatment, dividing a single crystal semiconductor substrate in a damaged region, and solid-phase-growing an amorphous semiconductor layer This is a method for manufacturing a substrate.

  Another embodiment of the present invention includes a step of forming an amorphous semiconductor layer over a single crystal semiconductor substrate, a step of irradiating the single crystal semiconductor substrate with ions to form a damaged region, and a single crystal semiconductor substrate. A step of attaching to the supporting substrate through the amorphous semiconductor layer and the insulating layer, a first heat treatment, a step of dividing the single crystal semiconductor substrate in the damaged region, a second heat treatment, And a step of solid-phase growth of a crystalline semiconductor layer.

  Another embodiment of the present invention includes a step of irradiating a single crystal semiconductor substrate with ions to form a damaged region, a step of forming an amorphous semiconductor layer over the single crystal semiconductor substrate, and a single crystal semiconductor substrate. Bonding the support substrate with the amorphous semiconductor layer and the insulating layer, performing a heat treatment, dividing the single crystal semiconductor substrate in the damaged region, and solid-phase growing the amorphous semiconductor layer. This is a method for manufacturing a semiconductor substrate.

  Another embodiment of the present invention includes a step of irradiating a single crystal semiconductor substrate with ions to form a damaged region, a step of forming an amorphous semiconductor layer over the single crystal semiconductor substrate, and a single crystal semiconductor substrate. A step of attaching to the supporting substrate through the amorphous semiconductor layer and the insulating layer, a first heat treatment, a step of dividing the single crystal semiconductor substrate in the damaged region, a second heat treatment, And a step of solid-phase growth of a crystalline semiconductor layer.

  In the above, the amorphous semiconductor layer may be formed by a plasma CVD method using an undiluted silane-based gas as a raw material.

  Note that in this specification, a single crystal refers to a crystal whose crystal structure is formed with a certain regularity and whose crystal axis is oriented in a certain direction in any part. However, it may have disorder of regularity such as defects and lattice distortion.

  In this specification, a semiconductor substrate refers to a substrate in which a semiconductor layer is provided over a supporting substrate with an insulating layer interposed therebetween, such as an SOI substrate.

  According to one embodiment of the present invention, thickening can be realized in a single crystal semiconductor layer formed over a supporting substrate.

  Further, according to one embodiment of the present invention, mass productivity of a semiconductor substrate or a semiconductor device can be improved.

  Further, according to one embodiment of the present invention, transfer defects of a single crystal semiconductor layer can be reduced.

8A and 8B illustrate an example of a structure and a manufacturing method of a semiconductor substrate. 8A and 8B illustrate an example of a structure and a manufacturing method of a semiconductor device. 8A and 8B illustrate an example of a structure and a manufacturing method of a semiconductor device. 8A and 8B illustrate an example of a structure and a manufacturing method of a semiconductor device. 8A and 8B illustrate an example of a structure and a manufacturing method of a semiconductor device. The figure which shows the result of a cross-sectional TEM image and a Raman spectroscopic measurement.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings.

(Embodiment 1)
In this embodiment, an example of a structure and a manufacturing method of a semiconductor substrate will be described.

  A method for manufacturing a semiconductor substrate will be described with reference to FIGS.

  First, a support substrate 101 (also referred to as a base substrate) is prepared (see FIG. 1A).

  As the supporting substrate 101, a substrate made of an insulator such as a glass substrate, a plastic substrate, a ceramic substrate, a quartz substrate, or a sapphire substrate, a substrate made of a semiconductor such as silicon, or a substrate made of a conductor such as metal or stainless steel can be used. .

  A glass substrate having a strain point of 580 ° C. or higher and 730 ° C. or lower is preferably used. The glass substrate is preferably an alkali-free glass substrate. For the alkali-free glass substrate, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used, for example. Cost can be reduced by using an inexpensive glass substrate or plastic substrate.

  Further, a single layer or a stacked insulating layer may be formed over the surface of the supporting substrate 101. By providing the insulating layer, when the support substrate 101 contains an impurity (an alkali metal, an alkaline earth metal, or the like), the impurity can be prevented from diffusing into the semiconductor layer. Examples of the material for the insulating layer include silicon oxide, silicon nitride, silicon oxynitride, and silicon nitride oxide.

  Note that silicon oxynitride has a higher oxygen content than nitrogen, and silicon nitride oxide has a higher nitrogen content than oxygen. Here, the content is compared based on the measurement results of the Rutherford backscattering method and the hydrogen forward scattering method.

  Next, a single crystal semiconductor substrate 103 is prepared (see FIG. 1B).

  As the single crystal semiconductor substrate 103, a substrate using a semiconductor material such as silicon, silicon germanium, gallium arsenide, or indium phosphide can be given. Here, a single crystal silicon substrate is used.

  Then, an amorphous semiconductor layer 105 is formed over the single crystal semiconductor substrate 103 (see FIG. 1B).

  The material of the amorphous semiconductor layer 105 is selected in accordance with the material of the single crystal semiconductor substrate 103. Here, the amorphous semiconductor layer 105 may be an amorphous silicon (also referred to as amorphous silicon) layer. In this case, a silane-based gas (for example, monosilane or disilane) is supplied as a source gas, and an amorphous silicon layer is formed by plasma CVD. The film formation temperature may be 200 ° C. or higher and 400 ° C. or lower.

  Here, the film formation rate of the amorphous silicon layer can be improved by reducing the dilution rate of the silane-based gas. For example, the dilution rate is greater than 0 and less than 2 times. Specifically, hydrogen gas (dilution gas) may be diluted with respect to silane at 200 sccm so as to be more than 0 sccm and not more than 200 sccm. Furthermore, the film formation rate can be further improved by using the silane-based gas without dilution. In addition, using without diluting means not deliberately diluting. Therefore, even when residual gas or the like is introduced unintentionally, it is not diluted.

  Next, a damaged region 107 (also referred to as an embrittlement layer) is formed in the single crystal semiconductor substrate 103 (see FIG. 1B).

  The damaged region 107 can be formed by irradiating the single crystal semiconductor substrate 103 with ions (ion beam) accelerated by an electric field and introducing ions from the surface of the single crystal semiconductor substrate 103 to a predetermined depth. . Here, ions are introduced from the side where the amorphous semiconductor layer 105 is formed in the single crystal semiconductor substrate 103.

  In addition, ions can be introduced by ion doping or ion implantation using hydrogen, an inert element, or halogen. An example of the inert element is helium, and an example of the halogen is fluorine.

  Next, the single crystal semiconductor substrate 103 is attached to the supporting substrate 101 with the insulating layer 109 interposed therebetween (see FIG. 1C).

  The insulating layer 109 functions as a bonding layer for bonding two substrates, and may be formed on one side of the single crystal semiconductor substrate 103 side or the support substrate 101 side.

  The insulating layer 109 may be formed by a single layer or a stack of oxides, nitrides, or the like by a CVD method. Specific examples of the material include silicon oxide, silicon nitride, silicon oxynitride, and silicon nitride oxide.

  Note that before the bonding, surface treatment is preferably performed on the bonding surfaces (also referred to as bonding surfaces) of the two substrates. By performing the surface treatment, hydrophilicity or cleanliness is improved, and bonding strength at the time of bonding can be improved. Note that the surface treatment may be performed on at least one of the two substrates. In the case where the insulating layer 109 is formed, the surface of the insulating layer 109 is formed.

  Examples of the surface treatment include wet treatment (ozone water cleaning, megasonic cleaning, two-fluid cleaning, etc.) or dry processing (ultraviolet treatment, ozone treatment, plasma treatment, radical treatment, etc.). Moreover, you may carry out combining these.

  Next, heat treatment is performed on the two bonded substrates, and the single crystal semiconductor substrate 103 is divided (also referred to as separation) in the damaged region 107. By this division, the single crystal semiconductor layer 111 including a part of the single crystal semiconductor substrate 103 can be transferred onto the supporting substrate 101 (see FIG. 1D).

  The heat treatment may be performed at a temperature of 500 ° C. or higher and lower than the strain point of the support substrate 101.

  Further, the amorphous semiconductor layer 105 is subjected to solid phase epitaxial growth (also referred to as solid phase growth) by the heat treatment here. By this solid phase growth, the single crystal semiconductor layer 113 in which the amorphous semiconductor layer 105 is crystallized can be formed over the supporting substrate 101.

  In other words, the single crystal semiconductor layer 113 and the single crystal semiconductor layer 111 are stacked over the supporting substrate 101 with the insulating layer 109 interposed therebetween. In this manner, the thickness can be increased by stacking two single crystal semiconductor layers.

  Note that the heat treatment here may be performed in two stages. Dividing as described above by the first heat treatment and solid phase growth as described above may be performed by the second heat treatment. The second heat treatment is preferably performed at a higher temperature than the first heat treatment.

  As described above, the semiconductor substrate 115 is manufactured.

  Since solid-phase growth has a higher film formation rate than vapor-phase growth, the throughput can be improved by using the manufacturing method of this embodiment mode. As a result, the mass productivity of the semiconductor substrate can be improved.

  In addition, since the amorphous semiconductor layer 105 does not break crystallinity due to ion irradiation when forming the damaged region 107, transfer defects of the single crystal semiconductor layer can be prevented.

  Further, when the dilution rate of the source gas is reduced when forming the amorphous semiconductor layer, the crystallinity of the single crystal semiconductor layer grown by solid phase can be improved. The reason will be described by taking the case of forming a silicon layer as an example.

  First, by reducing the dilution rate, the formed amorphous silicon layer contains a large amount of Si—H bonds caused by a silane-based gas (for example, monosilane). Then, during solid phase growth, hydrogen is released from the Si—H bond, so that silicon is rearranged and the crystallinity of the single crystal silicon layer is increased. As described above, the film formation step with a reduced dilution rate and the solid phase growth step combine to improve crystallinity.

  Furthermore, crystallinity can be further improved by using the silane-based gas without dilution.

  On the other hand, when increasing the dilution rate, hydrogen or argon contained in a dilution gas (for example, hydrogen gas or argon gas) decomposes Si—H bonds, thereby reducing hydrogen in the amorphous silicon layer. Therefore, the rearrangement of silicon is suppressed.

  For the above reasons, when improving the crystallinity of the single crystal semiconductor layer, it is preferable to use a silane-based gas with a low dilution rate or without dilution.

  This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 2)
In this embodiment, an example of the structure and manufacturing method of a semiconductor device, which is different from that in Embodiment 1, will be described.

  In Embodiment 1, the damaged region 107 is formed after the amorphous semiconductor layer 105 is formed in the step shown in FIG.

  On the other hand, this embodiment mode is characterized in that the amorphous semiconductor layer 105 is formed after the damaged region 107 is formed. Other configurations are the same as those in the first embodiment.

  Hereinafter, the semiconductor substrate manufactured by the method of Embodiment 1 (referred to as sample A) and the semiconductor substrate manufactured by the method of Embodiment 2 (sample B) are shown and compared.

  First, a specific manufacturing method of Sample A will be described. First, an amorphous silicon layer was formed on a single crystal silicon substrate by a plasma CVD method. Next, hydrogen ions were added to the single crystal silicon substrate by a doping method to form a damaged region. Then, the single crystal silicon substrate was bonded to the glass substrate on which the silicon nitride oxide layer was formed, and solid phase growth was performed along with the division, and the single crystal silicon layer was transferred onto the glass substrate.

  Here, the film formation conditions of the plasma CVD method were as follows. Monosilane was used without being diluted as a source gas, and the film formation temperature was 250 ° C. Further, the heating temperature at the time of splitting and solid phase growth was 600 ° C.

  The manufacturing method of Sample B is different from Sample A in that an amorphous silicon layer is formed after adding hydrogen ions to a single crystal silicon substrate. Others were produced in the same manner as Sample A.

  The structures of the sample A and the sample B thus manufactured are obtained by providing a single crystal silicon layer (c-Si) on a glass substrate (glass) through a silicon nitride oxide layer (SiNO).

  The measurement results of Sample A and Sample B are shown below.

  FIG. 6 shows a cross-sectional TEM image (left figure) of the single crystal silicon layer (c-Si) and the result of Raman spectroscopic measurement (right figure). 6A shows data of sample A, and FIG. 6B shows data of sample B.

  Note that the full width at half maximum was plotted at three locations in the plane of the single crystal silicon layer in the results of the Raman spectroscopic measurement. The average full width at half maximum at the three locations is also shown.

  From the cross-sectional TEM image, it was confirmed that the surface of the single crystal silicon layer (c-Si) was higher in the sample A (FIG. 6A) than in the sample B (FIG. 6B). .

  From the results of Raman spectroscopy, sample B (FIG. 6B) has a smaller average full width at half maximum and higher crystallinity of the single crystal silicon layer (c-Si) than sample A (FIG. 6A). It was recognized that

  As described above, a single crystal silicon layer with high flatness is obtained by the method of Embodiment 1 (Sample A), and a single crystal silicon layer with high crystallinity is obtained by the method of Embodiment 2 (Sample B). I was able to confirm.

  This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 3)
In this embodiment, an example of a method for manufacturing a semiconductor device will be described.

  A method for manufacturing a thin film transistor (also referred to as a TFT) using the semiconductor substrate manufactured in the above embodiment mode will be described with reference to FIGS.

  First, a semiconductor substrate manufactured by the method of Embodiment 1 is prepared as a semiconductor substrate (see FIG. 2A).

  In the semiconductor substrate, a single crystal semiconductor layer 201 is provided over a supporting substrate 101 with an insulating layer 109 interposed therebetween. The single crystal semiconductor layer 201 is formed by stacking a single crystal semiconductor layer 111 and a single crystal semiconductor layer 113 as illustrated in FIG.

  Note that the surface of the single crystal semiconductor layer 201 may be subjected to treatment for improving flatness such as etching treatment (for example, dry etching or wet etching) or polishing treatment (for example, CMP).

  A semiconductor substrate manufactured by the method of Embodiment Mode 2 may be used.

  Further, an impurity element for controlling the threshold voltage of the TFT may be added to the single crystal semiconductor layer 201. As the impurity element, for example, an acceptor imparting p-type conductivity such as boron, aluminum, or gallium is added to a region where a p-channel TFT is formed, and the n-channel TFT is formed in a region where the n-channel TFT is formed. A donor imparting n-type conductivity such as phosphorus or arsenic may be added.

  Next, the single crystal semiconductor layer 201 is etched to form island-shaped semiconductor layers 203 and 205 (FIG. 2B). Note that the semiconductor layer 203 functions as a semiconductor layer of an n-channel TFT, and the semiconductor layer 203 functions as a semiconductor layer of a p-channel TFT.

  Next, the insulating layer 207 is formed over the semiconductor layers 203 and 205. Then, a conductive layer 209 is formed over the semiconductor layer 203 with the insulating layer 207 interposed therebetween, and a conductive layer 211 is formed over the semiconductor layer 205 with the insulating layer 207 interposed therebetween (see FIG. 2C). Note that the insulating layer 207 functions as a gate insulating layer of the TFT, and the conductive layer 209 functions as a gate electrode of the TFT.

  The insulating layer 207 can be formed as a single layer or a stacked layer using silicon oxide, silicon nitride, or the like.

  The conductive layers 209 and 211 can be formed as a single layer or stacked layers using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing these as a main component.

  Next, an n-type low concentration impurity region 213 is formed in the semiconductor layer 203, and a p-type high concentration impurity region 217 is formed in the semiconductor layer 205 (see FIG. 2D).

  Specifically, the semiconductor layer 205 is covered with a resist, and an impurity element serving as a donor is added to the semiconductor layer 203. After the resist is removed, the semiconductor layer 203 is similarly covered with the resist, and an impurity element serving as an acceptor is added to the semiconductor layer 205. Note that the high-concentration impurity region 217 functions as a source region or a drain region.

  Here, by adding an impurity element using the conductive layers 209 and 211 as a mask, the low concentration impurity region 213 and the high concentration impurity region 217 can be formed in a self-aligning manner. Note that the impurity element may be added by an ion doping method, an ion implantation method, or the like.

  A region of the semiconductor layer 203 that overlaps with the conductive layer 209 is a channel formation region 215. A region of the semiconductor layer 205 that overlaps with the conductive layer 211 is a channel formation region 219.

  Note that the order of the steps described above may be reversed, and the high concentration impurity region 217 may be formed in the semiconductor layer 205 and then the low concentration impurity region 213 may be formed in the semiconductor layer 203.

  Next, after removing the resist covering the semiconductor layer 203, an insulating layer is formed by a plasma CVD method or the like. Then, by performing anisotropic etching in the vertical direction on the insulating layer, insulating layers (also referred to as sidewalls) 221 and 223 that are in contact with the side surfaces of the conductive layers 209 and 211 are formed (see FIG. 3A).

  Note that the insulating layer 207 is also etched by the anisotropic etching here.

  Next, the semiconductor layer 205 is covered with a resist 225, and an impurity element serving as a donor is added to the semiconductor layer 205 to form an n-type high concentration impurity region 227 (see FIG. 3B).

  Here, by adding an impurity element using the conductive layer 209 and the insulating layer 221 as a mask, the high-concentration impurity region 227 can be formed in a self-aligning manner.

  Note that the high concentration impurity region 227 has a higher impurity concentration than the low concentration impurity region 213. Further, the high concentration impurity region 227 and the high concentration impurity region 217 have substantially the same impurity concentration. The impurity concentration may be adjusted by the dose amount when the impurity element is added. Note that the high-concentration impurity region 227 functions as a source region or a drain region. Further, the breakdown voltage can be increased by the low concentration impurity region 213.

  Next, heat treatment for activating donors and acceptors is performed. Thereafter, the resist 225 is removed.

  Next, an insulating layer 229, an insulating layer 231, and a conductive layer 233 are formed (FIG. 3C).

  The insulating layer 229 can be formed using silicon nitride or silicon nitride oxide.

  The insulating layer 231 can be formed using an inorganic material such as silicon oxide or BPSG (Boron Phosphorus Silicon Glass), or an organic material such as polyimide or acrylic.

  The conductive layer 233 is formed so as to be electrically connected to the thin film transistor after a contact hole is formed in the insulating layer 229 and the insulating layer 231. The conductive layer 233 can be formed by a single layer or a stacked layer using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing any of these materials as its main component. Note that the conductive layer 233 functions as a source electrode or a drain electrode.

  Through the above steps, a semiconductor device including an n-channel TFT and a p-channel TFT can be manufactured.

  Although this embodiment mode describes a method for manufacturing a TFT, various semiconductor elements such as a capacitor and a resistor can be formed in addition to the TFT.

  In addition, various electronic devices can be manufactured using the semiconductor element. Examples of the electronic device include a display device such as a television, a personal computer, a video camera, a digital camera, a navigation system, or a portable information terminal (such as a mobile phone, an electronic book, or a portable game machine). A circuit using the semiconductor element can be provided in a display portion or a peripheral portion of these display devices.

  Further, as another example of the electronic apparatus, a display unit may not be essential, and examples thereof include various devices such as a wireless tag, an authentication device, a lighting device, and an air conditioner. A circuit using the semiconductor element can be provided in these devices.

  Examples of the circuit include a circuit that can use the semiconductor element, such as a pixel circuit, a driver circuit, an arithmetic circuit, a sensor circuit, a power supply circuit, or a memory circuit.

This embodiment can be implemented in appropriate combination with any of the other embodiments.
(Embodiment 4)

  In this embodiment, an example of a structure and a manufacturing method of a photoelectric conversion device will be described.

  First, the support substrate 101 is prepared (see FIG. 4A). The materials and the like are the same as those in the first embodiment.

  Next, a single crystal semiconductor substrate 103 is prepared (see FIG. 4B). As the single crystal semiconductor substrate 103, a substrate having one conductivity type can be used. Here, p-type is used.

  An i-type amorphous semiconductor layer 301 and an n-type amorphous semiconductor layer 303 are sequentially formed over the single crystal semiconductor substrate 103.

  In the case of forming a silicon layer as the i-type amorphous semiconductor layer 301, a silane-based gas can be used as a raw material by a plasma CVD method or the like.

  Note that the i-type semiconductor is preferably a so-called intrinsic semiconductor formed without adding an impurity element imparting p-type or n-type conductivity. However, it is difficult to make a strictly intrinsic semiconductor, and slightly p-type or n-type is exhibited. For this reason, the i-type semiconductor includes such a substantially intrinsic semiconductor.

  In the case of forming a silicon layer as the n-type amorphous semiconductor layer 303, a plasma CVD method using a silane-based gas and a gas containing an impurity element imparting n-type (for example, phosphorus) (for example, phosphine) as a raw material. Or the like. Further, after the amorphous semiconductor layer is formed, an impurity element imparting n-type conductivity may be doped.

  Here, the film formation rate of the amorphous silicon layer can be improved by reducing the dilution rate of the silane-based gas. For example, the dilution rate is greater than 0 and less than 2 times. Specifically, hydrogen gas (dilution gas) may be diluted with respect to silane at 200 sccm so as to be more than 0 sccm and not more than 200 sccm. Furthermore, the film formation rate can be further improved by using the silane-based gas without dilution.

  Next, a damaged region 107 is formed in the single crystal semiconductor substrate 103. The method for forming the damaged region 107 is the same as that in the first embodiment. Note that the amorphous semiconductor layers 301 and 303 may be formed after the damaged region 107 is formed as in Embodiment Mode 2.

  Next, a conductive layer 305 is formed over the amorphous semiconductor layer 303. Note that the damaged region 107 may be formed after the conductive layer 305 is formed.

  The conductive layer 305 functions as an electrode on a surface facing the light receiving surface of the photoelectric conversion device, and is formed using a reflective material. As the material having reflectivity, a metal selected from aluminum, silver, titanium, tantalum, tungsten, molybdenum, and copper, or an alloy material or a compound material containing the metal as a main component is used. The conductive layer 305 can be formed using a single layer or a stacked layer using any of these materials by an evaporation method, a sputtering method, or the like.

  Next, the single crystal semiconductor substrate 103 is attached to the supporting substrate 101 with the insulating layer 109 interposed therebetween (see FIG. 4C). After that, the single crystal semiconductor substrate 103 and the supporting substrate 101 are separated in the damaged region 107, and amorphous semiconductor layers 301 and 303 are grown in a solid phase (see FIG. 4D). Bonding, splitting, and solid phase growth may be performed in the same manner as in the first embodiment.

  Through the above steps, the conductive layer 305, the n-type single crystal semiconductor layer 313, the i-type single crystal semiconductor layer 311, and the p-type single crystal semiconductor layer 309 are formed over the supporting substrate 101 with the insulating layer 109 interposed therebetween. Laminated.

  Note that the n-type single crystal semiconductor layer 313 is obtained by solid-phase growth of an n-type amorphous semiconductor layer 303. Similarly, the i-type single crystal semiconductor layer 311 is obtained by solid-phase growth of the i-type amorphous semiconductor layer 301. The p-type single crystal semiconductor layer 309 is a part of the p-type single crystal semiconductor substrate 103 and is transferred onto the support substrate 101 by the above-described division.

  The n-type single crystal semiconductor layer 313, the i-type single crystal semiconductor layer 311, and the p-type single crystal semiconductor layer 309 function as the photoelectric conversion layer 315 in the photoelectric conversion device.

  Next, a conductive layer 317 is formed over the photoelectric conversion layer 315 (see FIG. 4E).

  The conductive layer 317 functions as an electrode on the light-receiving surface side of the photoelectric conversion device and is formed using a light-transmitting material. As the light-transmitting material, indium oxide, indium oxide tin oxide alloy (also referred to as ITO), indium zinc oxide oxide alloy (also referred to as IZO), zinc oxide, zinc oxide to which gallium is added, or the like can be used. Note that the conductive layer 317 is not necessarily provided.

  Note that as illustrated in FIG. 4E, a conductive layer 319 functioning as a grid electrode may be provided over the conductive layer 317. By providing the conductive layer 319 in contact with the conductive layer 317, resistance loss of the conductive layer 317 can be reduced. In particular, electrical characteristics under high illuminance can be improved. Note that in the case where the conductive layer 317 is not provided, the conductive layer 319 is formed over the photoelectric conversion layer 315.

  The conductive layer 319 can be formed as a single layer or stacked layers using a metal element such as silver, copper, aluminum, or palladium as a material by a printing method or the like. Note that the light receiving area can be improved by forming the planar shape of the conductive layer 319 in a grid shape.

  As described above, a photoelectric conversion device can be manufactured. The photoelectric conversion device can be applied to a solar cell, an optical sensor, or the like.

  Note that although a pin structure photoelectric conversion device is described in this embodiment mode, a pn structure may be employed. In the case of the pn structure, the i-type single crystal semiconductor layer 313 is not formed.

  Alternatively, light reception may be performed from the conductive layer 305 side (the support substrate 101 side), or light reception may be performed from both the conductive layer 317 side and the conductive layer 305 side. In the case where light is received from the conductive layer 305 side as in these structures, the conductive layer 305 is preferably formed using a light-transmitting material.

  The single crystal semiconductor substrate 103 may be an n-type substrate. In that case, the amorphous semiconductor layer 303 may be p-type. Therefore, the single crystal semiconductor layer 313 after the solid phase growth is also p-type. That is, the amorphous semiconductor layer 303 and the single crystal semiconductor layer 313 may have a conductivity type opposite to that of the single crystal semiconductor substrate 103.

  Note that in the case where a silicon layer is formed as the p-type amorphous semiconductor layer 303, a plasma containing a silane-based gas and a gas containing an impurity element imparting p-type (eg, boron) (eg, diborane) is used. It can be formed by a CVD method or the like. Further, after forming the amorphous semiconductor layer, an impurity element imparting p-type conductivity may be doped.

This embodiment can be implemented in appropriate combination with any of the other embodiments.
(Embodiment 5)

  In this embodiment, an example of a structure and a manufacturing method of a photoelectric conversion device, which is different from that in Embodiment 4, will be described.

  First, the support substrate 101 is prepared (see FIG. 5A). The materials and the like are the same as those in the first embodiment.

  Next, a single crystal semiconductor substrate 103 is prepared (see FIG. 5B). As the single crystal semiconductor substrate 103, a substrate having one conductivity type can be used. Here, p-type is used.

  A p-type amorphous semiconductor layer 401, an i-type amorphous semiconductor layer 301, and an n-type amorphous semiconductor layer 303 are sequentially formed over the single crystal semiconductor substrate 103. The n-type, i-type, and p-type may be formed in this order. The formation process of the amorphous semiconductor layer and the like are the same as those in the fourth embodiment.

  Next, a damaged region 107 formation step and a conductive layer 305 formation step are performed. Then, a bonding process, a dividing process, and a solid phase growth process between the single crystal semiconductor substrate 103 and the supporting substrate 101 are performed (see FIGS. 5C and 5D). These steps are performed in the same manner as in the fourth embodiment.

  Through the above steps, the conductive layer 305, the n-type single crystal semiconductor layer 313, the i-type single crystal semiconductor layer 311, the p-type single crystal semiconductor layer 411, and the insulating layer 109 are provided over the supporting substrate 101. A single crystal semiconductor layer 309 including a part of the single crystal semiconductor substrate 103 is stacked.

  After that, the single crystal semiconductor layer 309 is subjected to an etching process (for example, dry etching or wet etching) or a polishing process (for example, CMP). Through these treatments, the single crystal semiconductor layer 309 can be removed and the flatness of the exposed single crystal semiconductor layer 411 can be improved. Note that the planarity of the surface may be improved without removing the single crystal semiconductor layer 309. In that case, the conductivity type of the single crystal semiconductor layer 309 (the conductivity type of the single crystal semiconductor substrate 103) is p-type.

  The obtained n-type single crystal semiconductor layer 313, i-type single crystal semiconductor layer 311 and p-type single crystal semiconductor layer 411 function as the photoelectric conversion layer 315 in the photoelectric conversion device. In the case where the single crystal semiconductor layer 309 is not removed, the single crystal semiconductor layer 309 also functions as part of the photoelectric conversion layer 315.

  After that, a conductive layer 317 and a conductive layer 319 are formed in a manner similar to that in Embodiment 4 (see FIG. 5E).

  As described above, a photoelectric conversion device can be manufactured.

  This embodiment can be implemented in appropriate combination with any of the other embodiments.

101 support substrate 103 single crystal semiconductor substrate 105 amorphous semiconductor layer 107 damaged region 109 insulating layer 111 single crystal semiconductor layer 113 single crystal semiconductor layer 201 single crystal semiconductor layer 203 semiconductor layer 205 semiconductor layer 207 insulating layer 209 conductive layer 211 conductive layer 213 Low concentration impurity region 215 Channel formation region 217 High concentration impurity region 219 Channel formation region 221 Insulating layer 223 Insulating layer 225 Resist 227 High concentration impurity region 229 Insulating layer 231 Insulating layer 233 Conductive layer 301 Amorphous semiconductor layer 303 Amorphous Semiconductor layer 305 Conductive layer 309 Single crystal semiconductor layer 311 Single crystal semiconductor layer 313 Single crystal semiconductor layer 315 Photoelectric conversion layer 317 Conductive layer 319 Conductive layer 401 Amorphous semiconductor layer 411 Single crystal semiconductor layer

Claims (3)

Forming an amorphous semiconductor layer over a single crystal semiconductor substrate;
A step of the said single crystal semiconductor substrate through the amorphous semiconductor layer is irradiated with ion-to form a damaged region in the single crystal semiconductor substrate,
Bonding the single crystal semiconductor substrate to a supporting substrate through the amorphous semiconductor layer and the insulating layer;
Performing a first heat treatment and dividing the single crystal semiconductor substrate in the damaged region;
Performing a second heat treatment, a method for manufacturing a semiconductor substrate according to claim Rukoto to have a, a step of the amorphous semiconductor layer a solid phase growth. Forming an i-type amorphous semiconductor layer over a single crystal semiconductor substrate;
Forming an n-type amorphous semiconductor layer on the i-type amorphous semiconductor layer;
Irradiating the single crystal semiconductor substrate with ions through the i-type amorphous semiconductor layer and the n-type amorphous semiconductor layer to form a damaged region in the single crystal semiconductor substrate;
Forming a conductive layer on the n-type amorphous semiconductor layer after forming the damaged region;
Bonding the single crystal semiconductor substrate to a supporting substrate through the conductive layer and the insulating layer;
Performing a first heat treatment and dividing the single crystal semiconductor substrate in the damaged region;
Performing a second heat treatment to solid-phase grow the i-type amorphous semiconductor layer and the n-type amorphous semiconductor layer. forming a p-type amorphous semiconductor layer on a p-type single crystal semiconductor substrate;
Forming an i-type amorphous semiconductor layer on the p-type amorphous semiconductor layer;
Forming an n-type amorphous semiconductor layer on the i-type amorphous semiconductor layer;
Irradiating the single crystal semiconductor substrate with ions through the p-type amorphous semiconductor layer, the i-type amorphous semiconductor layer, and the n-type amorphous semiconductor layer, the single crystal semiconductor substrate Forming a damaged region on the substrate,
Forming a conductive layer on the n-type amorphous semiconductor layer after forming the damaged region;
Bonding the single crystal semiconductor substrate to a supporting substrate through the conductive layer and the insulating layer;
Performing a first heat treatment and dividing the single crystal semiconductor substrate in the damaged region;
Performing a second heat treatment to solid-phase grow the p-type amorphous semiconductor layer, the i-type amorphous semiconductor layer, and the n-type amorphous semiconductor layer. A method for manufacturing a semiconductor device.