JP5904005B2 - Capacitor placement support method and capacitor placement support device - Google Patents

Description

  The present invention relates to a capacitor arrangement support method and a capacitor arrangement support apparatus.

  In a digital circuit, a decoupling capacitor (hereinafter also simply referred to as “capacitor”) is used around the power supply terminal of the IC in order to lower the power supply impedance of the IC and remove noise. By the way, in order to design the power supply impedance to be equal to or less than the target value (hereinafter referred to as “target impedance”), the arrangement of the capacitors becomes a problem. This is because the inductance of the wiring connecting the IC and the capacitor changes depending on the arrangement of the capacitor.

  Therefore, in the conventional method, after determining the capacitor arrangement, calculate the power supply impedance.If the power supply impedance does not meet the target impedance, change the capacitor arrangement and calculate the power supply impedance again. Was necessary. In addition, skilled techniques are required to appropriately change the arrangement of the capacitors. Therefore, these factors hindered shortening the development period and cost reduction of the electronic circuit board.

  As a technology that can solve such problems, a capacitor is arranged so as to satisfy the target impedance based on predetermined data such as the width of the power supply wiring and the thickness of the dielectric between the power supply wiring and the ground plane. Japanese Patent Application Laid-Open No. H10-228707 discloses a capacitor arrangement support device that provides and presents a power supply wiring length that can be used.

  More specifically, according to this capacitor arrangement support device, the width of the power supply wiring, the thickness of the dielectric provided between the power supply wiring and the ground plane, the impedance of the capacitor, the target frequency, and the IC at the target frequency When the target impedance is input, the maximum allowable wiring length of the power supply wiring, that is, the range in which the capacitor can be arranged is calculated and displayed using an arithmetic expression.

International Publication No. 2011/151992 Pamphlet

  According to the capacitor arrangement support device described in Patent Document 1, it is possible to easily set an appropriate arrangement of capacitors without trial and error. However, this capacitor arrangement assisting device is intended for a substrate in which the power supply wiring for connecting the IC and the capacitor is formed only on the mounting surface on which the IC and the capacitor are mounted, and the back surface is the entire ground. Therefore, for example, there is a problem that it cannot be applied to a multilayer substrate in which the power supply wiring is wired over a plurality of layers (inner layers) through the interlayer through via.

  The present invention has been made to solve the above-mentioned problems, and trial and error are repeated in a multilayer substrate in which power supply wirings connecting IC power supply terminals and capacitors are wired over a plurality of layers through vias. It is an object of the present invention to provide a capacitor arrangement support method and a capacitor arrangement support apparatus that can set an appropriate arrangement of capacitors more easily.

ただし、Ｚ_ａｌｌは、次式（２）で表される。

According to the capacitor placement support method of the present invention, the first wiring layer, the first dielectric layer, the second wiring layer, the second dielectric layer, and the third wiring layer on which the IC and the capacitor are mounted are stacked in this order. Capacitor for supporting placement of a capacitor in a multilayer substrate having one dielectric layer, a second wiring layer, a plurality of power supply vias penetrating the second dielectric layer, and a plurality of ground vias penetrating the first dielectric layer A placement support method, comprising: a ground wiring formed in a first wiring layer for connecting an IC ground terminal and a ground via near the ground terminal; and a capacitor ground terminal and a ground via near the ground terminal. The width X and length Y of the ground wiring to be connected are formed in the first wiring layer and connect the power supply terminal of the IC and the power supply via near the power supply terminal, and the power supply terminal of the capacitor and the power supply. The width x and length y of the power supply wiring for connecting the power supply via near the terminal, the power supply via formed in the third layer wiring layer and connected to the power supply terminal of the IC, and the power supply via connected to the power supply terminal of the capacitor Are connected to the power terminal of the IC, the width W of the first dielectric layer, the thickness H of the second dielectric layer, the number of ground vias connected to the ground terminal of the IC, and the power terminal of the IC. the number of power supply via M, the number n of ground vias connected to the ground terminal of the capacitor, the number n of the power supply via connected to the power supply terminal of the capacitor, the power supply via the diameter R of the ground vias, impedance of the capacitor Z _c, the target frequency f _T, and the input step of accepting an input of a plurality of parameter values including a target impedance Z _T of the IC in the target frequency f _T, the input in the input step A plurality of parameter values, on the basis of the following equation (1), the maximum distance for calculating a power via connected to the power supply terminal of the IC, and the maximum distance L _max of a power via connected to the power supply terminal of the capacitor And a calculation step.

However, Z _all is expressed by the following equation (2).

ただし、Ｚ_ａｌｌは、次式（２）で表される。

The capacitor placement support apparatus according to the present invention is laminated in the order of the first wiring layer, the first dielectric layer, the second wiring layer, the second dielectric layer, and the third wiring layer on which the IC and the capacitor are mounted. Supporting placement of capacitors in a multilayer substrate having a plurality of power supply vias penetrating the first dielectric layer, the second wiring layer, and the second dielectric layer, and a plurality of ground vias penetrating the first dielectric layer A capacitor placement support apparatus that is formed in a first wiring layer and connects an IC ground terminal and a ground via near the ground terminal, and a capacitor ground terminal and a ground via near the ground terminal. The width X and the length Y of the ground wiring for connecting the power supply line, the power supply wiring formed in the first wiring layer for connecting the power supply terminal of the IC and the power supply via near the power supply terminal, and the power supply terminal of the capacitor A power supply line connected to the power supply vias connected to the power supply terminals of the IC and the power supply vias connected to the power supply terminals of the IC, formed in the third layer wiring layer. The width W of the power supply wiring connecting the vias, the thickness h of the first dielectric layer, the thickness H of the second dielectric layer, the number m of ground vias connected to the ground terminal of the IC, and connected to the power supply terminal of the IC The number M of power supply vias, the number n of ground vias connected to the ground terminal of the capacitor, the number N of power supply vias connected to the power supply terminal of the capacitor, the diameter R of the power supply via and the ground via, the impedance Z _{c of} the capacitor, target frequency f _T, and an input means for receiving input of a plurality of parameter values including a target impedance Z _T of the IC in the target frequency f _T, is input by the input means From the number of parameter values, based on the following equation (1), the maximum distance calculating means for calculating a power via connected to the power supply terminal of the IC, and the maximum distance L _max of a power via connected to the power supply terminal of the capacitor It is characterized by providing.

However, Z _all is expressed by the following equation (2).

According to the capacitor arrangement supporting method or the capacitor arrangement supporting apparatus according to the present invention, the ground wiring formed in the first wiring layer and connecting the ground terminal of the IC and the ground via near the ground terminal, and the capacitor ground A width X and a length Y of a ground wiring connecting the terminal and the ground via in the vicinity of the ground terminal; a power wiring formed in the first wiring layer for connecting the power terminal of the IC and the power via in the vicinity of the power terminal; And the width x and length y of the power supply wiring connecting the power supply terminal of the capacitor and the power supply via in the vicinity of the power supply terminal, the thickness h of the first dielectric layer, the impedance Z _{c of} the capacitor, the target frequency f _T , in addition to the target impedance Z _T of the IC in the target frequency f _T, it is formed on the third wiring layer, a power supply connected to the power supply terminal of the IC The width W of the power supply wiring connecting the power supply via connected to the power supply terminal of the capacitor, the thickness H of the second dielectric layer, the number m of ground vias connected to the ground terminal of the IC, and the power supply terminal of the IC A plurality of parameters including the number M of power supply vias connected, the number n of ground vias connected to the ground terminal of the capacitor, the number N of power supply vias connected to the power supply terminal of the capacitor, and the diameter R of the power supply via and the ground via When a value is input, the maximum distance L _max between the power supply via connected to the power supply terminal of the IC and the power supply via connected to the power supply terminal of the capacitor, that is, the capacitor is arranged from the above equation (1). The possible disposition possible distance / range is directly calculated. Therefore, in the multilayer substrate where the power supply wiring that connects the power supply terminal of the IC and the capacitor is wired over a plurality of layers through vias, the proper arrangement of the capacitor can be set more easily without trial and error. Is possible.

The capacitor placement support method according to the present invention preferably includes a display step for displaying the maximum distance _Lmax calculated in the maximum distance calculation step.

In addition, the capacitor arrangement assisting device according to the present invention preferably includes a display unit that displays the maximum distance L _max calculated by the maximum distance calculating unit.

In this case, the calculated maximum distance L _max between the power supply via connected to the power supply terminal of the IC and the power supply via connected to the power supply terminal of the capacitor, that is, the arrangementable distance / range in which the capacitor can be arranged is Is displayed. Therefore, it is possible to visually recognize the disposition possible distance / range in which the capacitor can be disposed and determine the placement of the capacitor.

  According to the present invention, in a multilayer substrate in which power supply wiring connecting an IC power supply terminal and a capacitor is wired over a plurality of layers through vias, proper arrangement of capacitors can be performed more easily and without trial and error. Can be set.

It is a block diagram which shows the structure of the capacitor | condenser arrangement | positioning assistance apparatus which concerns on embodiment. It is a longitudinal cross-sectional view which shows the structure of the multilayer board | substrate with which a capacitor | condenser is arrange | positioned. It is a top view which shows an example of the wiring pattern of the 1st wiring layer which comprises a multilayer board | substrate. It is a top view which shows an example of the wiring pattern of the 3rd wiring layer which comprises a multilayer substrate. It is a figure which shows the example of a display of the maximum distance of the power supply via connected to the power supply terminal of IC, and the power supply via connected to a capacitor | condenser. It is a flowchart which shows the process sequence of the maximum distance calculation process by the capacitor | condenser arrangement | positioning assistance apparatus which concerns on embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

  First, the configuration of the capacitor arrangement support device 1 according to the first embodiment will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the capacitor arrangement support device 1.

  Capacitor placement support apparatus 1 is a range in which a decoupling capacitor can be placed based on a plurality of parameter values (input data) input from a user so that the power supply impedance viewed from IC 210 is equal to or less than the target impedance ( By presenting the maximum distance, the substrate design of the multilayer substrate is supported. For this purpose, the capacitor arrangement support device 1 includes an input unit 10, an information processing unit 20, and a display unit 30. Further, the information processing unit 20 has a maximum distance calculation unit 21. The power supply impedance viewed from the IC 210 is the impedance at the power supply terminal 210a of the IC 210, that is, from the conductor pad to which the power supply terminal 210a is connected until returning to the conductor pad to which the ground terminal 210b is connected. It is the impedance of the path.

  Here, the case where the capacitor 220 is arranged on the multilayer substrate 100 shown in FIGS. 2 to 4 will be described as an example. First, the configuration of the multilayer substrate 100 will be described with reference to FIGS. Here, FIG. 2 is a longitudinal sectional view showing the configuration of the multilayer substrate 100. 3 is a plan view showing an example of the wiring pattern of the first wiring layer 101 constituting the multilayer substrate 100, and FIG. 4 is an example of the wiring pattern of the third wiring layer 103 constituting the multilayer substrate 100. FIG.

  The multilayer substrate 100 has a multilayer structure, and from the upper side in FIG. 2, the first wiring layer 101, the first dielectric layer 105, the second wiring layer 102, the second dielectric layer 106, the third wiring layer 103, the third wiring layer The dielectric layer 107 and the fourth wiring layer 104 are laminated in order. Inside the multilayer substrate 100, a plurality of (three in this embodiment) grounds penetrate the first dielectric layer 105 in the thickness direction and electrically connect the first wiring layer 101 and the second wiring layer 102. Vias 122, 143, and 144 are formed. Further, inside the multilayer substrate 100, the first dielectric layer 105, the second wiring layer 102, and the second dielectric layer 106 are penetrated in the thickness direction, and the first wiring layer 101 and the third wiring layer 103 are connected. A plurality (three in this embodiment) of power supply vias 121, 141, and 142 that are electrically connected are formed.

  A printed wiring made of, for example, copper foil is formed on the first wiring layer 101, and electronic components such as the IC 210 and the capacitor 220 are mounted by soldering or the like. Here, examples of the IC 210 include a power management IC (power management IC) that is driven with a relatively large current. The IC 210 is, for example, an IC in a BGA (Ball Grid Array) package, and is mounted on the first wiring layer 101 by face-down mounting using ball-shaped electrodes (bumps). In this embodiment, a chip-type three-terminal capacitor is used as the capacitor 220. The three-terminal capacitor 220 supplies electricity necessary for the operation of the IC 210, and removes noise entering through the power supply wiring and noise generated by the operation of the IC 210.

  The first wiring layer 101 is made of copper foil or the like, the power supply wiring 111 connecting the power supply terminal 210a of the IC 210 and the power supply via 121 formed in the vicinity of the power supply terminal 210a, and the ground terminal 210b of the IC 210, A ground wiring 112 is formed to connect the ground via 122 formed in the vicinity of the ground terminal 210b. The first wiring layer 101 is also formed with two conductive pads 131 and 132 to which the two through terminals (power supply terminals) 220a and 220b of the three-terminal capacitor 220 are connected. A power supply via 141 is connected to the conductive pad 131, and a power supply via 142 is connected to the conductive pad 132. Furthermore, two conductive pads 133 and 134 to which the two ground terminals 220c and 220d of the three-terminal capacitor 220 are connected are formed on the first wiring layer 101. The conductive pads 133 and 134 are connected to the ground vias 143 and 144 through the surface ground 108. In the present embodiment, the ground wiring for connecting the ground terminals 220c and 220d of the three-terminal capacitor 220 and the ground vias 143 and 144, and the through terminals (power supply terminals) 220a and 220b of the three-terminal capacitor 220 and the power via 141 are provided. , 142 can be ignored.

  Each of the first dielectric layer 105, the second dielectric layer 106, and the third dielectric layer 107 is an insulating layer formed of a dielectric such as insulating resin or ceramics.

  The second wiring layer 102 is a so-called solid ground layer in which a ground pattern made of copper foil or the like is formed on substantially the entire surface. Note that the above-described ground vias 122, 143, and 144 are connected to the second wiring layer 102.

  The third wiring layer 103 is made of copper foil or the like, and includes a power supply via 121 connected to the power supply terminal 210a of the IC 210 and power supply vias 141 connected to the through terminals (power supply terminals) 220a and 220b of the three-terminal capacitor 220. A power supply wiring 110 is formed to connect 142. A surface ground 109 is formed in a region other than the power supply wiring 110.

  By forming the multilayer substrate 100 as described above, the power supply terminal 210a of the IC 210 is connected to the through terminal of the three-terminal capacitor 220 via the power supply wiring 111, the power supply via 121, the power supply wiring 110, and the power supply vias 141 and 142. (Power supply terminals) 220a and 220b are connected. That is, a three-terminal capacitor 220 is inserted between the power source and ground of the IC 210. In the fourth wiring layer 104, for example, signal wiring of an electronic component such as the IC 210 is formed.

Returning to FIG. The input unit 10 includes, for example, a keyboard and a touch panel, and receives a plurality of parameter values (data) input from the user. More specifically, the input unit 10 includes the width X (mm) and the length Y (mm) of the ground wiring 112 formed in the first wiring layer 101, and the power wiring 111 formed in the first wiring layer 101. Width x (mm) and length y (mm), width W (mm) of the power supply wiring 110 formed in the third wiring layer 103, thickness h (mm) of the first dielectric layer 105, second dielectric layer The thickness H (mm) of 106, the number n of ground vias 143 and 144 connected to the ground terminals 220c and 220d of the three-terminal capacitor 220, and the power supply vias connected to the power terminals 220a and 220b of the three-terminal capacitor 220 The number N (pieces) of 141 and 142, the number m (pieces) of the ground vias 122 connected to the ground terminal 210b of the IC 210, the number M (pieces) of the power supply vias 121 connected to the power supply terminal 210a of the IC 210, 121,141,142, the diameter R of the ground vias 122,143,144 (mm), 3 impedance terminal capacitor 220 _{Z c} (Ω), the target frequency _f T (MHz), and, of IC210 in the target frequency _{f T} A target impedance Z _T (Ω) is received. That is, the input unit 10 functions as input means described in the claims. These parameter values (input data) may be input in advance and stored in the memory. Further, it is assumed that the target impedance Z _T required for the power source of the IC 210 and the upper limit (target frequency f _T ) of the frequency that satisfies the target impedance Z _T are disclosed in advance.

  The information processing unit 20 arranges the maximum distance between the power supply via 121 and the power supply via 141 from the plurality of parameter values (input data) received by the input unit 10, that is, the three-terminal capacitor 220. The distance from the IC 210 that can be calculated is calculated. The information processing unit 20 includes a microprocessor that performs arithmetic processing on the received parameter values (input data), a ROM that stores programs (including arithmetic expressions) and data for causing the microprocessor to execute each processing, It is composed of a RAM or the like that temporarily stores various data such as calculation results. In the information processing unit 20, the program stored in the ROM is executed by the microprocessor, thereby realizing the function of the maximum distance calculation unit 21.

ただし、Ｚ_ａｌｌは、次式（２）で表される。

The maximum distance calculation unit 21 receives the width X (mm) and the length Y (mm) of the ground wiring 112, the width x (mm) and the length y (mm) of the power wiring 111, which are input from the input unit 10. The width W (mm) of the wiring 110, the thickness h (mm) of the first dielectric layer 105, the thickness H (mm) of the second dielectric layer 106, and the ground connected to the ground terminals 220c and 220d of the three-terminal capacitor 220 The number n (number) of vias 143 and 144, the number N (number) of power supply vias 141 and 142 connected to the power supply terminals 220a and 220b of the three-terminal capacitor 220, and the number of ground vias 122 connected to the ground terminal 210b of the IC 210. Number m (pieces), number M (pieces) of power supply vias 121 connected to power supply terminal 210a of IC 210, power supply vias 121, 141, 142, and ground vias 122, 143, 144 R (mm), 3 impedance terminal capacitor 220 _{Z c} (Omega), the target frequency _f T (MHz), and, from the target impedance _{Z T} (Omega), based on the following equation (1), power supply via 121 and a power supply The maximum distance L _max with the via 141 is calculated.

However, Z _all is expressed by the following equation (2).

That is, the maximum distance calculation unit 21 functions as the maximum distance calculation means described in the claims. Calculation results such as the calculated maximum distance L _max are output to the display unit 30.

The display unit 30 includes, for example, an LCD display and displays a plurality of parameter values (input data) received by the input unit 10 and calculation results such as the maximum distance _Lmax . That is, the display unit 30 functions as display means described in the claims. Here, a display example of the maximum distance L _max between the power supply via 121 connected to the power supply terminal 210a of the IC 210 and the power supply via 141 connected to the through terminal (power supply terminal) 220a of the three-terminal capacitor 220 is shown in FIG. .

As shown in FIG. 5, the distance between the power supply via 121 connected to the power supply terminal 210a of the IC 210 and the power supply via 141 connected to the through terminal (power supply terminal) 220a of the three-terminal capacitor 220 is the maximum distance L _max. by arranging the three-terminal capacitor 220 so that less can supply impedance is designed to be equal to or less than the target impedance Z _T. In other words, the power supply via 141 is arranged in a circle (arrangeable range) centered on the power supply via 121 and having a maximum distance (arrangeable distance) _Lmax as a radius, as shown in FIG. it can be below the impedance Z _T.

  Although there are two through terminals (power supply terminals) 220a and 220b of the three-terminal capacitor 220, a power supply via (power supply via 121 in this embodiment) connected to at least one of them is in the circle of FIG. It only has to be. When a two-terminal capacitor is used instead of the three-terminal capacitor, a power supply via to which a power supply side terminal is connected may be included in the circle.

  Next, the operation of the capacitor arrangement support device 1 and the capacitor arrangement support method will be described with reference to FIG. FIG. 6 is a flowchart showing the processing procedure of the maximum distance calculation processing by the capacitor arrangement support device 1. Here, the case where the three-terminal capacitor 220 is arranged on the multilayer substrate 100 shown in FIGS. 2 to 4 will be described as an example.

In step S100, a plurality of parameter values (data) input from the user are accepted. More specifically, the width X (mm) and length Y (mm) of the ground wiring 112 formed in the first wiring layer 101, and the width x (mm) of the power supply wiring 111 formed in the first wiring layer 101. And the length y (mm), the width W (mm) of the power supply wiring 110 formed in the third wiring layer 103, the thickness h (mm) of the first dielectric layer 105, and the thickness H of the second dielectric layer 106 ( mm) Number n of ground vias 143 and 144 connected to the ground terminals 220c and 220d of the three-terminal capacitor 220. Number of power vias 141 and 142 connected to the power terminals 220a and 220b of the three-terminal capacitor 220. N (number), number m (number) of ground vias 122 connected to ground terminal 210b of IC 210, number M (number) of power supply vias 121 connected to power supply terminal 210a of IC 210, power supply vias 121, 14 , 142, the diameter R of the ground vias 122,143,144 (mm), 3 impedance terminal capacitor 220 _{Z c} (Omega), the target frequency _f T (MHz), and target impedance Z of IC210 in the target frequency _{f T T} (Ω) is accepted.

ただし、Ｚ_ａｌｌは、次式（２）で表される。

In step S102, the width X (mm) and length Y (mm) of the ground wiring 112, the width x (mm) and length y (mm) of the power wiring 111, and the width of the power wiring 110 received in step S100. W (mm), thickness h (mm) of the first dielectric layer 105, thickness H (mm) of the second dielectric layer 106, ground vias 143 and 144 connected to the ground terminals 220c and 220d of the three-terminal capacitor 220 The number n of power supply vias 141 and 142 connected to the power supply terminals 220a and 220b of the three-terminal capacitor 220, and the number m (number of ground vias 122 connected to the ground terminal 210b of the IC 210). ), The number M of power supply vias 121 connected to the power supply terminal 210a of the IC 210, power supply vias 121, 141, 142, and ground vias 122, 143, 14 Diameter R (mm), the impedance of the three-terminal capacitor 220 _{Z c (Ω),} the target frequency _f T (MHz), and, from the target impedance _{Z T} (Omega), based on the following equation (1), IC 210 power The maximum distance L _max between the power supply via 121 connected to the terminal 210a and the power supply via 141 connected to the through terminal (power supply terminal) 220a of the three-terminal capacitor 220 is calculated.

However, Z _all is expressed by the following equation (2).

In step S104, the results such as the maximum distance _{L max} calculated in step S102 is displayed (see Figure 5). Therefore, the designer can determine that the distance between the power supply via 121 connected to the power supply terminal 210a of the IC 210 and the power supply via 141 connected to the through terminal (power supply terminal) 220a of the three-terminal capacitor 220 is equal to or less than the maximum distance _Lmax. by disposing the three-terminal capacitor 220 so can power impedance is designed to be equal to or less than the target impedance Z _T.

Next, in order to confirm the effect of the capacitor placement support apparatus 1 or the capacitor placement support method according to the present embodiment, the values (input data) of each parameter are changed in the wiring patterns shown in FIGS. The distance _Lmax was calculated, and the power supply impedance when the three-terminal capacitor 220 was arranged according to the calculation result was obtained by simulation (Examples 1 and 2). The results will be described below.

(Example 1)
First, the target impedance Z _T = 0.97 (Ω), the target frequency f _T = 100 (MHz), the width W of the power supply wiring 110 = 3 (mm), and the thickness h of the first dielectric layer 105 = 0.1 ( mm), thickness H of the second dielectric layer 106 = 0.9 (mm), width X of the ground wiring 112 = 0.15 (mm), length Y of the ground wiring 112 = 0.7 (mm), power supply The width x = 0.15 (mm) of the wiring 111, the length y = 1.67 (mm) of the power supply wiring 111, and the number n of the ground vias 143, 144 connected to the ground terminals 220c, 220d of the three-terminal capacitor 220 = 2 (pieces) Number of power supply vias 141 and 142 connected to power supply terminals 220a and 220b of three-terminal capacitor 220 N = 2 (pieces), number m of ground vias 122 connected to ground terminal 210b of IC 210 1 (number), number M of power supply vias 121 connected to power supply terminal 210a of IC 210 = 1 (number), diameter R of power supply vias 121, 141, 142, and ground vias 122, 143, 144 = 0.3 (mm) ) When the impedance Z _c of the three-terminal capacitor 220 is 0.005 (Ω), the calculation result using the above equation (1) is the maximum distance Lmax = 3.38 (mm).

According to this calculation result, the result of the impedance simulation by the electromagnetic field simulator when the three-terminal capacitor 220 (more precisely, the power supply via 141) is arranged at the position 3.38 (mm) from the power supply via 121 is the power supply impedance Z. = 0.97 (Ω), which is consistent with the target impedance Z _T. Therefore, the validity of the above formula (1) was confirmed.

(Example 2)
Next, target impedance Z _T = 0.67 (Ω), target frequency f _T = 100 (MHz), width W of power supply wiring 110 = 20 (mm), thickness h of first dielectric layer 105 h = 0.1 (Mm), thickness H of the second dielectric layer 106 = 1.2 (mm), X of the ground wiring 112 = 0.2 (mm), length Y of the ground wiring 112 = 0.6 (mm), power supply The width x of the wiring 111 = 0.2 (mm), the length y of the power supply wiring 111 = 0.57 (mm), the number n of ground vias 143 and 144 connected to the ground terminals 220c and 220d of the three-terminal capacitor 220 = 2 (pieces) Number of power supply vias 141 and 142 connected to power supply terminals 220a and 220b of three-terminal capacitor 220 N = 2 (pieces), number of ground vias 122 connected to ground terminal 210b of IC 210 m = 1 ), The number M of the power supply vias 121 connected to the power supply terminal 210a of the IC 210 = 1 (number), the diameter R of the power supply vias 121, 141, 142, and the ground vias 122, 143, 144 = 0.3 (mm), When the impedance Z _c of the three-terminal capacitor 220 is 0.005 (Ω), the calculation result using the above equation (1) is the maximum distance Lmax = 4.24 (mm).

According to this calculation result, the result of the impedance simulation by the electromagnetic simulator when the three-terminal capacitor 220 (more precisely, the power supply via 141) is arranged at a position 4.24 (mm) from the power supply via 121 is the power supply impedance Z = 0.67 (Ω), and the matched target impedance _{Z T.} Therefore, the validity of the above formula (1) was confirmed.

As described above in detail, according to the present embodiment, the width X and length Y of the ground wiring 112 formed in the first wiring layer 101 and connecting the ground terminal 210b of the IC 210 and the ground via 122, the first is formed on the first wiring layer 101, the width x and length y of the power wiring 111 for connecting the power supply terminal 210a and the power supply via 121 of IC 210, the impedance of the thickness h, 3-terminal capacitor 220 of the first dielectric layer 105 _{Z c} In addition to the target frequency f _T and the target impedance Z _T , the power supply via 121 formed in the third wiring layer 103 and connected to the power supply terminal 210a of the IC 210 and the through terminal (power supply terminal) of the three-terminal capacitor 220 The width W of the power supply wiring 110 connecting the power supply via 141 connected to 220a, the thickness H of the second dielectric layer 106, and the IC 210 The number m of ground vias 122 connected to the ground terminal 210b, the number M of power supply vias 121 connected to the power supply terminal 210a of the IC 210, and the number n of ground vias 143 and 144 connected to the ground terminal 220b of the three-terminal capacitor 220. When the number N of the power supply vias 141 and 142 connected to the power supply terminal 220a of the three-terminal capacitor 220, the diameter R of the power supply vias 121, 141, and 142, and the ground vias 122, 143, and 144 are input, the above formula (1 ), The maximum distance L _max between the power supply via 121 connected to the power supply terminal 210a of the IC 210 and the power supply via 141 connected to the power supply terminal 220a of the three-terminal capacitor 220, that is, the three-terminal capacitor 220 can be arranged. The possible disposition possible distance / range is directly calculated. Therefore, the power supply wirings 111 and 110 that connect the power supply terminal 220a of the IC 210 and the three-terminal capacitor 220 are wired over a plurality of layers (the first wiring layer 101 and the third wiring layer 103) via the power supply vias 121 and 141. In the multilayer substrate 100, it is possible to set an appropriate arrangement of the three-terminal capacitor 220 more easily without trial and error. As a result, the development period of the multilayer substrate 100 on which the three-terminal capacitor 220 is mounted can be further shortened, and the development cost can be further reduced.

Further, according to the present embodiment, the calculated maximum distance L _max between the power supply via 121 connected to the power supply terminal 210a of the IC 210 and the power supply via 141 connected to the three-terminal capacitor 220, that is, the three-terminal capacitor. The possible disposition distance / range in which 220 can be disposed is displayed. Therefore, it is possible to visually recognize the disposition possible distance / range in which the three-terminal capacitor 220 can be disposed and determine the arrangement of the three-terminal capacitor 220.

Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above embodiment, a three-terminal capacitor is used as the capacitor 220, but a two-terminal capacitor may be used. Even when a two-terminal capacitor is used, the maximum distance L _max can be obtained in the same manner.

  In the above embodiment, a four-layer substrate is used as the multilayer substrate 100, but a three-layer substrate or a multilayer substrate having five or more layers can also be used. Further, the shape and the like of the power supply wiring 111 and the ground wiring 112 are not limited to the above embodiment, and can be arbitrarily set.

DESCRIPTION OF SYMBOLS 1 Capacitor arrangement assistance apparatus 10 Input part 20 Information processing unit 21 Maximum distance calculating part 30 Display part 100 Multilayer substrate 101 1st wiring layer 102 2nd wiring layer 103 3rd wiring layer 104 4th wiring layer 105 1st dielectric layer 106 Second dielectric layer 107 Third dielectric layer 108, 109 Plane ground 110, 111 Power wiring 112 Ground wiring 121, 141, 142 Power via 122, 143, 144 Ground via 131, 132 Conductive pad 210 IC
210a power terminal 210b ground terminal 220 capacitor (3-terminal capacitor)
220a, 220b Through terminal (power supply terminal)
220c, 220d Ground terminal

Claims (4)

A first wiring layer, a first dielectric layer, a second wiring layer, a second dielectric layer, and a third wiring layer on which an IC and a capacitor are mounted are stacked in this order, and the first dielectric layer and the second wiring are stacked. A capacitor placement support method for supporting placement of the capacitor in a multilayer substrate having a plurality of power supply vias penetrating through the second dielectric layer and a plurality of ground vias penetrating through the first dielectric layer. And
A ground wiring that is formed in the first wiring layer and connects a ground terminal of the IC and a ground via near the ground terminal, and a ground wiring that connects the ground terminal of the capacitor and a ground via near the ground terminal. The width X and length Y of the capacitor are formed in the first wiring layer and connect the power supply terminal of the IC and the power supply via near the power supply terminal, and the power supply terminal of the capacitor and the vicinity of the power supply terminal. The power supply wiring width x and length y connecting the power supply via, formed in the third layer wiring layer and connected to the power supply terminal of the IC, and the power supply via connected to the power supply terminal of the capacitor , W of the first dielectric layer, thickness H of the second dielectric layer, number m of ground vias connected to the ground terminal of the IC, power supply end of the IC The number M of power vias connected to the capacitor, the number n of ground vias connected to the ground terminal of the capacitor, the number N of power vias connected to the power terminal of the capacitor, the power via, and the diameter R of the ground via. Receiving an input of a plurality of parameter values including the capacitor impedance Z _c , the target frequency f _T , and the target impedance Z _{T of the} IC at the target frequency f _T ;
From the plurality of parameter values input in the input step, based on the following equation (1), the power supply via connected to the power supply terminal of the IC, and the power supply via connected to the power supply terminal of the capacitor And a maximum distance calculating step for calculating the maximum distance L _max of the capacitor.

However, Z _all is expressed by the following equation (2).

The capacitor placement support method according to claim 1, further comprising a display step of displaying the maximum distance L _max calculated in the maximum distance calculation step. A first wiring layer, a first dielectric layer, a second wiring layer, a second dielectric layer, and a third wiring layer on which an IC and a capacitor are mounted are stacked in this order, and the first dielectric layer and the second wiring are stacked. And a plurality of power supply vias penetrating the second dielectric layer and a plurality of ground vias penetrating the first dielectric layer. And
A ground wiring that is formed in the first wiring layer and connects a ground terminal of the IC and a ground via near the ground terminal, and a ground wiring that connects the ground terminal of the capacitor and a ground via near the ground terminal. The width X and length Y of the capacitor are formed in the first wiring layer and connect the power supply terminal of the IC and the power supply via near the power supply terminal, and the power supply terminal of the capacitor and the vicinity of the power supply terminal. The power supply wiring width x and length y connecting the power supply via, formed in the third layer wiring layer and connected to the power supply terminal of the IC, and the power supply via connected to the power supply terminal of the capacitor , W of the first dielectric layer, thickness H of the second dielectric layer, number m of ground vias connected to the ground terminal of the IC, power supply end of the IC The number M of power vias connected to the capacitor, the number n of ground vias connected to the ground terminal of the capacitor, the number N of power vias connected to the power terminal of the capacitor, the power via, and the diameter R of the ground via. Input means for receiving input of a plurality of parameter values including the impedance Z _{c of} the capacitor, the target frequency f _T , and the target impedance Z _{T of the} IC at the target frequency f _T ;
Based on the following equation (1), the power supply via connected to the power supply terminal of the IC and the power supply via connected to the power supply terminal of the capacitor from the plurality of parameter values input by the input means And a maximum distance calculating means for calculating the maximum distance L _max of the capacitor.

However, Z _all is expressed by the following equation (2).

4. The capacitor placement support apparatus according to claim 3, further comprising display means for displaying the maximum distance _Lmax calculated by the maximum distance calculation means.

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