JP5941335B2 - Switching element and method of manufacturing switching element - Google Patents

Description

  The present invention relates to a switching element typified by HEMT (High Electron Mobility Transistor) and a manufacturing method thereof.

  In recent years, nitride semiconductors, which are III-V group compound semiconductors typified by gallium nitride (GaN), are expected to be applied to switching elements. A nitride semiconductor has a band gap as large as about 3.4 eV, a dielectric breakdown electric field 10 times higher, and an electron saturation speed 2.5 times higher than a conventional semiconductor using silicon (Si). This is because it has optimum characteristics.

For example, a switching element in which a GaN / AlGaN heterostructure is provided on a substrate such as silicon carbide (SiC) or sapphire has been proposed. In the switching element, in addition to the spontaneous polarization due to the asymmetric structure in the C-axis direction of the GaN crystal structure (wurtzite type), polarization due to the piezoelectric effect due to lattice mismatch of AlGaN and GaN results in 1 × 10 ^13. A two-dimensional electron gas layer having a high concentration of about cm ⁻² is generated. In the switching element, by controlling the electron density of the two-dimensional electron gas layer, a state in which predetermined electrodes are electrically connected (on state) and a state in which predetermined electrodes are not electrically connected ( (Off state).

  An example of such a switching element will be described with reference to FIGS. 20 to 22 are cross-sectional views showing examples of conventional switching elements. FIG. 20 shows the switching element in the on state, and FIG. 21 shows the switching element in the off state. FIG. 22 shows the switching element in a state immediately after the transition from the off state to the on state.

  As shown in FIGS. 20 to 22, the switching element 100 includes a substrate 21, a buffer layer 102 formed on the upper surface of the substrate 21, and an electron transit layer 103 made of undoped GaN formed on the upper surface of the buffer layer 102. An electron supply layer 104 made of AlGaN formed on the upper surface of the electron transit layer 103, a source electrode 105 formed on the upper surface of the electron supply layer 104, and a drain electrode 106 formed on the upper surface of the electron supply layer 104 A gate insulating film 107 formed on the upper surface of the electron supply layer 104 and between the source electrode 105 and the drain electrode 106, and a gate electrode 108 formed on the upper surface of the gate insulating film 107.

  The switching element 100 is a normally-on type. Therefore, as shown in FIG. 20, even when the potential of the gate electrode 108 is the same potential (0 V) as that of the source electrode 105 or the gate electrode 108 is open, the electron transit layer 103 and the electron supply layer 104 are used. The two-dimensional electron gas layer 109 is generated in the vicinity of the interface where the two are bonded, and is turned on. In the on state, if the potential of the drain electrode 106 is higher than the potential of the source electrode 105, a current flows between the source electrode 105 and the drain electrode 106.

  On the other hand, as shown in FIG. 21, when the potential of the gate electrode 108 is lower than the threshold voltage with reference to the potential (0 V) of the source electrode 105, the electron transit layer 103 and the electron supply layer 104 are provided below the gate electrode 108. The two-dimensional electron gas layer 109 does not occur in the vicinity of the interface where the two are bonded, and the device is turned off. In the off state, no current flows between the source electrode 105 and the drain electrode 106.

  In the off state as shown in FIG. 21, the depletion region 110 is formed below the gate electrode 108 and becomes high resistance. Then, a high potential difference of about several hundred volts corresponding to the power supply voltage is generated between the source electrode 105 and the drain electrode 106, and a high electric field (in the drawing) from the end of the depletion region 110 (particularly, the drain electrode 106 side) to the gate electrode 108. Black arrow) occurs.

  Such a high electric field may cause dielectric breakdown and leakage current around the gate electrode 108. In addition, electrons generated by the high electric field may be trapped in a level caused by a nitrogen defect on the surface (upper surface) of the electron supply layer 104, thereby causing a “collapse phenomenon”.

  The collapse phenomenon occurs when the switching element 100 transitions from the off state to the on state, as shown in FIG. As described above, the collapse phenomenon occurs when the electrons 111 trapped on the surface of the electron supply layer 104 when the switching element 100 is in the off state transition to the on state for a predetermined time (for example, several seconds to several minutes). This is a phenomenon in which by continuing to be trapped for a long time, a repulsive force (Coulomb force) is exerted on the electrons in the two-dimensional electron gas layer 109 and the current flowing between the source electrode 105 and the drain electrode 106 is hindered. If the on-resistance of the switching element 100 increases due to this collapse phenomenon, it becomes difficult because high-speed switching becomes difficult.

  In order to suppress the collapse phenomenon, nitrogen defects on the surface of the electron supply layer 104 are reduced by covering the surface of the electron supply layer 104 with a film made of nitride or the like. In particular, an aluminum nitride (AlN) film having a band gap of about 6 eV and a band gap larger than other nitrides (for example, silicon nitride: band gap 5 eV) is used from the viewpoint of reducing leakage current. is there.

Patent Documents 1 to 3 propose switching elements in which an aluminum oxide film (AlO _X , X is an arbitrary positive number, the same applies hereinafter) having a larger band gap is formed on the upper surface of the AlN film. . Since AlO _X has a large band gap of about 8 eV to 9 eV, the leakage current can be further reduced.

JP 2004-273630 A JP 2011-258781 A JP 2010-45343 A

However, the switching elements proposed in Patent Documents 1 and 2 have a structure in which the surface of the switching element is entirely covered with the AlO _X film except for the portion where the electrodes are formed, and thus the heat dissipation is poor. The point becomes a problem. AlN has a thermal conductivity of about 200 W / m · K and excellent heat dissipation, but AlO _X has a thermal conductivity of only 10 W / m · K to 20 W / m · K and has poor heat dissipation. . Therefore, the switching elements proposed in Patent Documents 1 and 2 cannot efficiently dissipate the heat generated when a large current flows in the on state, so that the temperature easily rises, and the current due to the increase in on-resistance This leads to a decrease in driving force, an increase in leakage current, and a decrease in reliability.

On the other hand, in the switching element proposed in Patent Document 3, since the AlO _X layer is formed only in the connection portion between the gate electrode and the electron supply layer (InAlN), the switching element proposed in Patent Documents 1 and 2 is used. It is considered that heat dissipation is better than the element. However, in the switching element proposed in Patent Document 3, the AlO _X layer is not formed below the ends of the gate electrode that protrude to the source electrode side and the drain electrode side, and the gate electrode that has a high electric field is formed. This is a problem because the breakdown voltage may be insufficient and dielectric breakdown and leakage current may occur below the end portion.

  In view of the above problems, an object of the present invention is to provide a switching element that has a high breakdown voltage and good heat dissipation and a method for manufacturing the same.

  To achieve the above object, the present invention provides a first semiconductor layer and a second semiconductor formed on an upper surface of the first semiconductor layer and having a band gap larger than that of the first semiconductor layer and heterojunction with the first semiconductor layer. A layer, a third semiconductor layer formed on an upper surface of the second semiconductor layer, a first electrode electrically connected to the first semiconductor layer, and electrically connected to the first semiconductor layer in plan view A second electrode formed apart from the first electrode, and a control electrode positioned between the first electrode and the second electrode in plan view, the upper surface of the third semiconductor layer Part of the oxide region is oxidized to be an oxide region having higher withstand voltage and lower thermal conductivity than the surroundings, and the control electrode is electrically connected to the third semiconductor layer through the oxide region, and is seen in a plan view. The end of the oxide region on the first electrode side is the first electrode of the control electrode. Between the end of the oxide region and the end of the first electrode on the control electrode side, and in plan view, the end of the oxide region on the second electrode side of the control electrode A switching element is provided between an end portion on the second electrode side and an end portion on the control electrode side of the second electrode.

  According to this switching element, the oxide region is formed at a position including the projection of the control electrode with respect to the third semiconductor layer, and is not formed on the entire upper surface of the third semiconductor layer. That is, the oxide region is formed only at a position where the dielectric breakdown and the leakage current are effectively suppressed, but is not formed on the entire upper surface of the third semiconductor layer.

  In the switching element having the above characteristics, a lower portion of the control electrode is in contact with a contact region in the oxide region, and the thickness of the contact region is locally increased in the oxide region. It is preferable.

  According to this switching element, since the contact region where high breakdown voltage is particularly required is locally thickened, it is possible to effectively suppress dielectric breakdown and leakage current. Furthermore, since it can suppress that an oxide area | region becomes thick unnecessarily, it becomes possible to suppress that heat dissipation becomes worse.

  In the switching element having the above characteristics, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are each made of a nitride semiconductor, and the third semiconductor layer does not contain indium and gallium, preferable.

According to this switching element, it is possible to prevent indium oxide (InO _x ) or gallium oxide (GaO _x ) having a relatively small band gap and poor insulation from being included in the third semiconductor layer. . Therefore, it is possible to increase the breakdown voltage of the switching element.

In the switching element having the above characteristics, the first semiconductor layer is made of In _x Ga _1-x N (0 ≦ x <1), and the second semiconductor layer is made of In _y Ga _z Al _1-yz. N (0 ≦ y <1, 0 ≦ z <1, 0 <y + z), and the third semiconductor layer may be made of AlN.

  Further, in the switching element having the above characteristics, the second semiconductor layer and the third semiconductor layer are formed of an integral layer whose composition changes continuously, and from the second semiconductor layer toward the third semiconductor layer, It is preferable that the composition ratio of indium and gallium is reduced to 0 on the upper surface of the third semiconductor layer.

  According to this switching element, since the interface between the second semiconductor layer and the third semiconductor layer is eliminated, generation of defects at the interface is prevented. Therefore, it is possible to suppress the collapse phenomenon.

  In the switching element having the above characteristics, it is preferable that the oxide region is formed by partially thermally oxidizing the third semiconductor layer.

  According to this switching element, the generation of defects at the interface of the oxide region is suppressed. Therefore, it is possible to suppress the collapse phenomenon.

  The present invention also includes a first semiconductor layer, a second semiconductor layer formed on an upper surface of the first semiconductor layer and having a band gap larger than that of the first semiconductor layer and heterojunction with the first semiconductor layer, A laminated structure forming step of forming a laminated structure including a third semiconductor layer formed on an upper surface of the second semiconductor layer; forming a mask partially opened on the upper surface of the laminated structure; and opening the mask Oxidizing the third semiconductor layer from a portion to form an oxide region in a part of the upper surface of the third semiconductor layer; a first electrode electrically connected to the first semiconductor layer; A second electrode electrically connected to the first semiconductor layer and spaced apart from the first electrode in plan view; and positioned between the first electrode and the second electrode in plan view and The third semiconductor layer through an oxide region; An electrode forming step of forming a control electrode that is electrically connected, and in plan view, an end of the oxide region on the first electrode side is an end of the control electrode on the first electrode side And the end of the first electrode on the side of the control electrode in plan view, the end of the oxide region on the side of the second electrode is the second electrode of the control electrode. A switching element manufacturing method is provided, wherein the switching element is positioned between a side end portion and an end portion of the second electrode on the control electrode side.

  According to this method for manufacturing a switching element, the oxide region is formed at a position including the projection of the control electrode with respect to the third semiconductor layer, and is not formed on the entire upper surface of the third semiconductor layer. Can be manufactured. That is, a switching element having a structure in which an oxide region is formed only at a position where dielectric breakdown and leakage current are effectively suppressed, but not formed on the entire upper surface of the third semiconductor layer is manufactured. Is possible.

  Further, in the method for manufacturing a switching element having the above characteristics, the oxidation step includes a first oxidation step of forming a first mask partially opened and oxidizing the third semiconductor layer from the opening of the first mask. Forming a second mask having an opening including a region oxidized in the first oxidation step, and oxidizing the third semiconductor layer from the opening of the second mask; And forming the oxide region having a contact region whose thickness is locally increased by the oxidation step, and forming the control electrode whose lower portion is in contact with the contact region in the electrode formation step. Also good.

  Further, in the method for manufacturing a switching element having the above characteristics, the oxidation step includes a first oxidation step of forming a first mask partially opened and oxidizing the third semiconductor layer from the opening of the first mask. Forming a second mask in which a portion included in the region oxidized in the first oxidation step is opened, and oxidizing the third semiconductor layer from the opening of the second mask; The oxide region having a contact region whose thickness is locally increased is formed by the oxidation step, and the control electrode whose lower portion is in contact with the contact region is formed in the electrode formation step. May be.

  According to these switching element manufacturing methods, the contact region where high breakdown voltage is particularly required is locally thickened to effectively suppress dielectric breakdown and leakage current, and the oxide region is unnecessarily thickened. It is possible to manufacture a switching element having a structure that suppresses deterioration of heat dissipation by suppressing the above.

  According to the switching element having the above characteristics and the method for manufacturing the switching element having the above characteristics, the oxide region is formed only at a position where dielectric breakdown and leakage current are effectively suppressed. A switching element having a structure not formed on the entire upper surface is obtained. Therefore, it is possible to obtain a switching element having a high breakdown voltage and good heat dissipation.

Sectional drawing which shows the structural example of the switching element which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method example of the switching element which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method example of the switching element which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method example of the switching element which concerns on 1st Embodiment of this invention. Sectional drawing which shows the manufacturing method example of the switching element which concerns on 1st Embodiment of this invention. Sectional drawing which shows the structural example of the switching element which concerns on 2nd Embodiment of this invention. Sectional drawing which shows the example of a manufacturing method of the switching element which concerns on 2nd Embodiment of this invention. Sectional drawing which shows the example of a manufacturing method of the switching element which concerns on 2nd Embodiment of this invention. Sectional drawing which shows the example of a manufacturing method of the switching element which concerns on 2nd Embodiment of this invention. Sectional drawing which shows the example of a manufacturing method of the switching element which concerns on 2nd Embodiment of this invention. Sectional drawing which shows the example of a manufacturing method of the switching element which concerns on 2nd Embodiment of this invention. Sectional drawing which shows the example of a manufacturing method of the switching element which concerns on 2nd Embodiment of this invention. Sectional drawing which shows another example of the manufacturing method of the switching element which concerns on 2nd Embodiment of this invention. Sectional drawing which shows another example of the manufacturing method of the switching element which concerns on 2nd Embodiment of this invention. Sectional drawing which shows another example of the manufacturing method of the switching element which concerns on 2nd Embodiment of this invention. Sectional drawing which shows another example of the manufacturing method of the switching element which concerns on 2nd Embodiment of this invention. Sectional drawing which shows another example of the manufacturing method of the switching element which concerns on 2nd Embodiment of this invention. Sectional drawing which shows another example of the manufacturing method of the switching element which concerns on 2nd Embodiment of this invention. Sectional drawing which shows another example of the manufacturing method of the switching element which concerns on 3rd Embodiment of this invention. Sectional drawing which shows an example (on state) of the conventional switching element. Sectional drawing which shows an example (off state) of the conventional switching element. Sectional drawing which shows an example (state immediately after changing from an OFF state to an ON state) of the conventional switching element.

  Hereinafter, switching elements according to first to third embodiments of the present invention will be described with reference to FIGS. In addition, each of the switching element which concerns on 1st-3rd embodiment demonstrated below is only one embodiment of this invention, and this invention is not limited to these. In addition, the switching elements according to the first to third embodiments can be implemented by combining a part or all of them as long as there is no contradiction. In addition, FIGS. 1 to 19 referred to in the following description are emphasized as appropriate for convenience of explanation, and the dimensional ratio of each component on the drawing and the actual dimensional ratio are not necessarily the same. Shall not.

<First Embodiment>
First, a structural example of the switching element according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view showing a structural example of a switching element according to the first embodiment of the present invention.

  As shown in FIG. 1, the switching element 1 includes a substrate 2, a buffer layer 3 formed on the upper surface of the substrate 2, an electron transit layer (first semiconductor layer) 4 formed on the upper surface of the buffer layer 3, An electron supply layer (second semiconductor layer) 5 formed on the upper surface of the electron transit layer 4 and having a band gap larger than that of the electron transit layer 4 and heterojunction with the electron transit layer 4, and an upper surface of the electron supply layer 5 A barrier layer (third semiconductor conductor) 6, a passivation layer 7 formed on the upper surface of the barrier layer 6, a source electrode (first electrode) 8 electrically connected to the electron transit layer 4, and an electron transit layer 4 A drain electrode (second electrode) which is electrically connected and formed apart from the source electrode 8 in a plan view (a plane perpendicular to the vertical direction in the drawing, and the same applies to the description of FIGS. 2 to 19 hereinafter). Electrode) 9 and source electrode 8 and drain in plan view. Comprises a gate electrode (control electrode) 10 which is located between the in-electrode 9, a. The switching element 1 is a normally-on type.

  A part of the upper surface of the barrier layer 6 is oxidized to be an oxide region 61 having a higher withstand voltage and lower thermal conductivity than the surroundings. The gate electrode 10 is electrically connected to the barrier layer 6 through the oxide region 61.

The substrate 2 is made of, for example, silicon (Si), silicon carbide (SiC), sapphire, gallium nitride (GaN), zinc oxide (ZnO), gallium arsenide (GaAs), or the like. The buffer layer 3 is made of, for example, Al _a Ga _1-a N (0 ≦ a ≦ 1, that is, AlN when a = 1, or GaN when a = 0). Any substrate 2 and buffer layer 3 may be used as long as the switching element 1 operates suitably.

The electron transit layer 4 is made of, for example, In _x Ga _1-x N (0 ≦ x <1) having a thickness of 1 μm to 5 μm. The electron supply layer 5 is made of, for example, In _y Ga _z Al _1-yz N (0 ≦ y <1, 0 ≦ z <1, 0 <y + z) having a thickness of 10 nm to 100 nm. The band gap of the electron supply layer 5 is larger than the band gap of the electron transit layer 4, and the electron transit layer 4 and the electron supply layer 5 are heterojunction. Furthermore, the lattice constant of the electron supply layer 5 is smaller than the lattice constant of the electron transit layer 4, and lattice mismatch occurs at the interface where these layers are joined. Therefore, a two-dimensional electron gas layer 11 is generated near the interface where the electron transit layer 4 and the electron supply layer 5 are joined. In the switching element 1, the two-dimensional electron gas layer 11 corresponds to a channel.

  Each of the source electrode 8, the drain electrode 9, and the gate electrode 10 includes a metal element such as Ti, Al, Cu, Au, Pt, W, Ta, Ru, Ir, Pd, and Hf, or at least two of these metal elements. Or an alloy containing at least one of these metal elements. Each of the source electrode 8, the drain electrode 9, and the gate electrode 10 may be composed of a single layer or may be composed of a plurality of layers having different compositions. However, the source electrode 8 and the drain electrode 9 are in ohmic contact with the electron transit layer 4.

The passivation layer 7 is made of, for example, SiO _X , SiN, AlN or the like having a thickness of 100 nm to 3 μm. Each of the source electrode 8, the drain electrode 9, and the gate electrode 10 has a field plate structure in which the upper portion extends over the passivation layer 7. The upper part of the source electrode 8 projects to the gate electrode 10 side and the opposite side, the upper part of the drain electrode 9 projects to the gate electrode 10 side and the opposite side, and the upper part of the gate electrode 10 extends to the source electrode 8. And the drain electrode 9 side.

The barrier layer 6 is made of, for example, AlN having a thickness of 5 nm to 50 nm, and a part of the upper surface thereof is oxidized to form an oxide region 61. The oxide region 61 is made of, for example, AlO _X having a thickness of 1 nm to 40 nm. As described above, an oxide such as AlO _X has a larger band gap than AlN and is suitable for suppressing dielectric breakdown and leakage current, but has a lower thermal conductivity and lower heat dissipation than AlN. .

  In plan view, the end 61D1 of the oxide region 61 on the source electrode 8 side is composed of an end 10E1 of the gate electrode 10 on the source electrode 8 side and an end 8E of the source electrode 8 on the gate electrode 10 side. Located between. Furthermore, in plan view, an end 61D2 of the oxide region 61 on the drain electrode 9 side is formed by an end 10E2 of the gate electrode 10 on the drain electrode 9 side and an end 9E of the drain electrode 9 on the gate electrode 10 side. Located between.

  The switching element 1 is switched between an on state and an off state in accordance with the potential application state of the gate electrode 10. For example, when the potential of the gate electrode 10 becomes equal to the potential (0 V) of the source electrode 8, the switching element 1 is turned on, and the two-dimensional electron gas generated in the vicinity of the interface where the electron transit layer 4 and the electron supply layer 5 are joined. The layer 11 electrically connects the source electrode 8 and the drain electrode 9. On the other hand, when the potential of the gate electrode 10 becomes lower than the threshold voltage (about −10 V) with respect to the potential (0 V) of the source electrode 8, the switching element 1 is turned off, and the electron transit layer 4 and the electron Since the two-dimensional electron gas layer 11 is not generated near the interface where the supply layer 5 is joined, the source electrode 8 and the drain electrode 9 are not electrically connected.

  When the switching element 1 is in the on state, a large current flows between the source electrode 8 and the drain electrode 9, so that the switching element 1 generates heat. However, the switching element 1 covers only a part of the upper surface of the barrier layer 6 with the oxide region 61 with poor heat dissipation, and the other is not covered with the oxide region 61 with a material with good heat dissipation (for example, AlN). Because of the structure, heat dissipation is good and the temperature does not rise easily. Therefore, it is possible to suppress a decrease in current driving force, an increase in leakage current, a decrease in reliability, and the like associated with an increase in on-resistance due to a rise in temperature.

  On the other hand, when the switching element 1 is in the off state, a high voltage of about several hundred volts (for example, 600 volts) can be applied between the source electrode 8 and the drain electrode 9. At this time, particularly on the drain electrode 9 side of the gate electrode 10, a high electric field is generated from the lower electron transit layer 4 to the gate electrode 10 (see FIG. 21). However, in the switching element 1, since the oxide region 61 having a large band gap and a high breakdown voltage is formed in a place where such a high electric field is generated, dielectric breakdown and leakage current due to insufficient breakdown voltage can be suppressed. become.

  As described above, the switching element 1 has a structure in which the oxide region 61 is formed at a position including the projection of the gate electrode 10 on the barrier layer 6 and is not formed on the entire upper surface of the barrier layer 6. That is, the oxide region 61 is formed only at a position where the dielectric breakdown and the leakage current are effectively suppressed, but is not formed on the entire upper surface of the barrier layer 6. Therefore, it is possible to obtain the switching element 1 having a high breakdown voltage and good heat dissipation.

Further, by preventing the barrier layer 6 from containing indium and gallium, the barrier layer 6 contains indium oxide (InO _x ) and gallium oxide (GaO _x ) whose band gap is relatively small and insulation is not good. It becomes possible not to be. Therefore, it is possible to increase the breakdown voltage of the switching element 1.

  An example of a method for manufacturing the switching element 1 according to the first embodiment of the present invention will be described with reference to FIGS. 2-5 is sectional drawing which shows the example of the manufacturing method of the switching element which concerns on 1st Embodiment of this invention.

In the manufacturing method of the switching element 1 of this example, first, as shown in FIG. 2, the buffer layer 3 is formed on the upper surface of the substrate 2, the electron transit layer 4 is further formed on the upper surface of the buffer layer 3, and An electron supply layer 5 is formed on the upper surface of the electron transit layer 4, and a barrier layer 6 is further formed on the upper surface of the electron supply layer 5. Then, a mask 20 is formed on the upper surface of the laminated structure composed of these layers. The mask 20 is made of, for example, SiO _X or SiN having a thickness of 50 nm to 1 μm.

  Next, as shown in FIG. 3, an opening 21 is formed in a part of the mask 20. The opening 21 can be formed by, for example, photolithography and etching. Further, the position where the opening 21 is formed is a position where the oxide region 61 is to be formed. Note that the size of the opening 21 may be equal to the size of the upper portion of the gate electrode 10 in plan view.

  Next, as shown in FIG. 4, the oxide region 61 is formed by oxidizing the barrier layer 6 from the opening 21 of the mask 20. At this time, for example, the oxide region 61 can be formed by performing heat treatment at 900 ° C. or higher for several tens of minutes in an oxygen atmosphere. Thus, when the oxide region 61 is formed by thermal oxidation, generation of defects at the interface of the oxide region 61 is suppressed. Therefore, it is possible to suppress the collapse phenomenon.

  Next, as shown in FIG. 5, the mask 20 is removed (or the mask 20 is formed), and the passivation layer 7 is formed on the entire upper surface of the stacked structure. Thereafter, for example, by performing photolithography and etching, the source electrode 8, the drain electrode 9, and the gate electrode 10 are electrically connected to a part of the passivation layer 7, the barrier layer 6, the electron supply layer 5, and the electron transit layer 4. 1 is obtained by forming these electrodes 8 to 10 after making holes for connecting them.

Second Embodiment
A structural example of the switching element according to the second embodiment of the present invention will be described with reference to FIG. FIG. 6 is a cross-sectional view showing a structural example of a switching element according to the second embodiment of the present invention. In FIG. 6, the same reference numerals are given to the same parts as those of the switching element 1 according to the first embodiment shown in FIG. 1. Furthermore, below, the switching element 1a according to the second embodiment will be described with a focus on the parts that are different from the switching element 1 according to the first embodiment. The description will be omitted as appropriate in consideration of the description.

  As shown in FIG. 6, the switching element 1 a includes a substrate 2, a buffer layer 3, an electron transit layer 4, an electron supply layer 5, a barrier layer 6, a passivation layer 7, a source electrode 8, and a drain electrode. 9 and the gate electrode 10.

  However, in the switching element 1a, in the oxide region 61 formed in the barrier layer 6, the contact region 611a with which the lower part of the gate electrode 10 contacts is locally thick in the oxide region 61a. In the oxide region 61a, for example, the thickness of the contact region 611a is 2 nm or more and 40 nm or less, and the thickness of other portions is 1 nm or more and 20 nm or less. Except for this point, the switching element 1a is the same as the switching element 1 of the first embodiment shown in FIG.

  As described above, in the switching element 1a, the contact region 611a that particularly requires high breakdown voltage is locally thickened, so that it is possible to effectively suppress dielectric breakdown and leakage current. Furthermore, since it can suppress that the oxide area | region 61a becomes thick unnecessarily, it becomes possible to suppress that heat dissipation becomes worse.

  An example of a method for manufacturing the switching element 1a according to the second embodiment of the present invention will be described with reference to FIGS. 7-12 is sectional drawing which shows the example of the manufacturing method of the switching element which concerns on 2nd Embodiment of this invention.

In the manufacturing method of the switching element 1a of this example, first, as shown in FIG. 7, the buffer layer 3 is formed on the upper surface of the substrate 2, and the electron transit layer 4 is further formed on the upper surface of the buffer layer 3. An electron supply layer 5 is formed on the upper surface of the electron transit layer 4, and a barrier layer 6 is further formed on the upper surface of the electron supply layer 5. Then, a mask 20 is formed on the upper surface of the laminated structure composed of these layers. The mask 20 is made of, for example, SiO _X or SiN having a thickness of 50 nm to 1 μm.

  Next, as shown in FIG. 8, a first opening 21 a </ b> A is formed in part of the mask 20. The first opening 21aA can be formed by, for example, photolithography and etching. The position where the first opening 21aA is formed is the position where the contact region 611a is to be formed. The size of the first opening 21aA may be equal to the size of the lower portion of the gate electrode 10 in plan view.

  Next, as shown in FIG. 9, the barrier layer 6 is oxidized from the first opening 21aA of the mask 20 to form the initial oxide region 61aA. For example, the initial oxide region 61aA can be formed by performing the same heat treatment as in the first embodiment.

  Next, as shown in FIG. 10, a mask 20 having a second opening 22aA including the initial oxide region 61aA is formed. At this time, for example, the second opening 22aA may be formed by expanding the first opening 21aA by isotropic etching (for example, wet etching), or the first opening 21aA may be formed by photolithography and etching. The second opening 22aA may be formed by spreading, or the mask 20 having the first opening 21aA may be removed to re-form the mask 20 having the second opening 22aA. The position where the second opening 22aA is formed is a position where the oxide region 61a is to be formed. Note that the size of the second opening 22aA may be equal to the size of the upper portion of the gate electrode 10 in plan view.

  Next, as illustrated in FIG. 11, the oxide region 61 a is formed by oxidizing the barrier layer 6 from the second opening 22 a </ i> A of the mask 20. For example, the oxide region 61a can be formed by performing the same heat treatment as in the first embodiment.

  By this second thermal oxidation, the thickness of the region (initial oxide region 61aA) that has been oxidized by the first thermal oxidation is further increased. Thereby, the oxide region 61a having the contact region 611a whose thickness is locally increased in the oxide region 61a can be formed.

  Next, as shown in FIG. 12, the mask 20 is removed (or the mask 20 is formed), and the passivation layer 7 is formed on the entire top surface of the stacked structure. Thereafter, as in the first embodiment, the source electrode 8, the drain electrode 9, and the gate electrode 10 are formed, whereby the switching element 1a shown in FIG. 6 is obtained.

  Another example of the method for manufacturing the switching element 1a according to the second embodiment of the present invention will be described with reference to FIGS. 13 to 18 are sectional views showing another example of the method for manufacturing the switching element according to the second embodiment of the present invention.

In the manufacturing method of the switching element 1a of this example, first, as shown in FIG. 13, the buffer layer 3 is formed on the upper surface of the substrate 2, the electron transit layer 4 is further formed on the upper surface of the buffer layer 3, and An electron supply layer 5 is formed on the upper surface of the electron transit layer 4, and a barrier layer 6 is further formed on the upper surface of the electron supply layer 5. Then, a mask 20 is formed on the upper surface of the laminated structure composed of these layers. The mask 20 is made of, for example, SiO _X or SiN having a thickness of 50 nm to 1 μm.

  Next, as shown in FIG. 14, a first opening 21 a </ b> B is formed in a part of the mask 20. The first opening 21aB can be formed by, for example, photolithography and etching. The position where the first opening 21aB is formed is the position where the oxide region 61a is to be formed. Note that the size of the first opening 21aB may be equal to the size of the upper portion of the gate electrode 10 in plan view.

  Next, as shown in FIG. 15, the barrier layer 6 is oxidized from the first opening 21aB of the mask 20 to form the initial oxide region 61aB. For example, the initial oxide region 61aB can be formed by performing the same heat treatment as in the first embodiment.

  Next, as shown in FIG. 16, a mask 20 having a second opening 22aB included in the initial oxide region 61aB is formed. At this time, for example, the second opening 22aB may be formed by depositing a material forming the mask 20 so as to fill the first opening 21aB, or the mask 20 having the first opening 21aB may be removed. The mask 20 having the second opening 22aB may be formed again. The position where the second opening 22aA is formed is a position where the contact region 611a is to be formed. The size of the second opening 22aB may be equal to the size of the lower portion of the gate electrode 10 in plan view.

  Next, as shown in FIG. 17, the oxide region 61 a is formed by oxidizing the barrier layer 6 from the second opening 22 aB of the mask 20. For example, the oxide region 61a can be formed by performing the same heat treatment as in the first embodiment.

  By this second thermal oxidation, the thickness of a part of the region (initial oxide region 61aB) that has been oxidized by the first thermal oxidation is further increased. Thereby, the oxide region 61a having the contact region 611a whose thickness is locally increased in the oxide region 61a can be formed.

  Next, as shown in FIG. 18, the mask 20 is removed (or the mask 20 is formed), and the passivation layer 7 is formed on the entire upper surface of the stacked structure. Thereafter, as in the first embodiment, the source electrode 8, the drain electrode 9, and the gate electrode 10 are formed, whereby the switching element 1a shown in FIG. 6 is obtained.

<Third Embodiment>
A structural example of the switching element according to the third embodiment of the present invention will be described with reference to FIG. FIG. 19 is a cross-sectional view showing a structural example of a switching element according to the third embodiment of the present invention. In FIG. 19, the same reference numerals are given to the same parts as those of the switching element 1 according to the first embodiment shown in FIG. 1. Furthermore, in the following, the switching element 1b according to the third embodiment will be described with a focus on the parts different from the switching element 1 according to the first embodiment, and the parts that are the same will be described. The description will be omitted as appropriate in consideration of the description.

  As shown in FIG. 19, the switching element 1b includes a substrate 2, a buffer layer 3, an electron transit layer 4, an electron supply layer 5b, a barrier layer 6b, a passivation layer 7, a source electrode 8, and a drain electrode. 9 and the gate electrode 10.

However, in the switching element 1b, the electron supply layer 5b and the barrier layer 6b are an integral layer whose composition changes continuously. Specifically, for example, the electron supply layer 5b and the barrier layer 6b have a total thickness of 10 nm to 200 nm, and In _y Ga _z Al _1-yz N (0 ≦ y <1, 0 ≦ z <1, 0 <y + z). Then, the composition y and z of indium and gallium decrease from the electron supply layer 5b toward the barrier layer 6b (upward in the figure), and become 0 on the upper surface of the barrier layer 6b (that is, AlN). Except for this point, the switching element 1b is the same as the switching element 1 of the first embodiment shown in FIG.

  As described above, in the switching element 1b, since the interface between the electron supply layer 5b and the barrier layer 6b is eliminated, it is possible to prevent generation of defects at the interface. Therefore, it is possible to suppress the collapse phenomenon.

  The oxide region 61b in the switching element 1b can be formed by the same method as in the first embodiment (see FIGS. 2 to 5). Moreover, in the switching element 1b, you may form the oxide area | region 61a similar to the switching element 1a of 2nd Embodiment (refer FIGS. 6-18).

  The present invention can be used for a switching element, and is particularly suitable for use in a switching element applied to a power device.

1, 1a, 1b: Switching element 2: Substrate 3: Buffer layer 4: Electron traveling layer (first semiconductor layer)
5, 5b: Electron supply layer (second semiconductor layer)
6, 6b: Barrier layer (third semiconductor layer)
61, 61a, 61b: oxide region 61D1, 61D2: end 61aA, 61aB: initial oxide region 611a: contact region 7: passivation layer 8: source electrode (first electrode)
8E: End portion 9: Drain electrode (second electrode)
9E: End portion 10: Gate electrode (control electrode)
10E1, 10E2: end 11: two-dimensional electron gas 20: mask 21: opening 21aA, 21aB: first opening 22aA, 22aB: second opening

Claims (7)

A first semiconductor layer;
A second semiconductor layer formed on an upper surface of the first semiconductor layer and having a band gap larger than that of the first semiconductor layer and heterojunction with the first semiconductor layer;
A third semiconductor layer formed on an upper surface of the second semiconductor layer;
A first electrode electrically connected to the first semiconductor layer;
A second electrode electrically connected to the first semiconductor layer and formed apart from the first electrode in plan view;
A control electrode positioned between the first electrode and the second electrode in plan view,
A part of the upper surface of the third semiconductor layer is oxidized to be an oxide region having a higher withstand voltage and lower thermal conductivity than the surroundings,
The control electrode is electrically connected to the third semiconductor layer through the oxide region;
In plan view, the end of the oxide region on the first electrode side is between the end of the control electrode on the first electrode side and the end of the first electrode on the control electrode side. Position to,
In plan view, the end of the oxide region on the second electrode side is between the end of the control electrode on the second electrode side and the end of the second electrode on the control electrode side. It is located,
The control electrode has a lower portion in contact with a contact region in the oxide region;
The switching element , wherein the contact region has a locally large thickness in the oxide region . The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are each made of a nitride semiconductor,
The switching element according to claim 1, wherein the third semiconductor layer does not contain indium and gallium. The first semiconductor layer is made of In _x Ga _1-x N (0 ≦ x <1);
The second semiconductor layer is made of In _y Ga _z Al _1-yz N (0 ≦ y <1, 0 ≦ z <1, 0 <y + z);
The switching element according to claim 2 , wherein the third semiconductor layer is made of AlN. The second semiconductor layer and the third semiconductor layer are composed of an integral layer whose composition changes continuously,
Toward the third semiconductor layer from the second semiconductor layer, it decreases the composition ratio of indium and gallium, according to claim 1 to 3 in which the upper surface of the third semiconductor layer, characterized in that it becomes 0 The switching element according to any one of claims. The oxide region, wherein the third switching element according to any one of claims 1 to 4, the semiconductor layer partially thermally oxidized, characterized in that one formed by. A first semiconductor layer; a second semiconductor layer formed on an upper surface of the first semiconductor layer and having a band gap larger than the first semiconductor layer and heterojunction with the first semiconductor layer; and an upper surface of the second semiconductor layer A laminated structure forming step of forming a laminated structure comprising: a third semiconductor layer formed on
A mask partially opened is formed on the top surface of the stacked structure, and the third semiconductor layer is oxidized from the opening of the mask to form an oxide region on a part of the top surface of the third semiconductor layer. An oxidation process;
A first electrode electrically connected to the first semiconductor layer; a second electrode electrically connected to the first semiconductor layer and formed apart from the first electrode in plan view; and in plan view An electrode forming step of forming a control electrode located between the first electrode and the second electrode and electrically connected to the third semiconductor layer via the oxide region,
In plan view, the end of the oxide region on the first electrode side is between the end of the control electrode on the first electrode side and the end of the first electrode on the control electrode side. Position to,
In plan view, the end of the oxide region on the second electrode side is between the end of the control electrode on the second electrode side and the end of the second electrode on the control electrode side. It is located,
The oxidation step comprises:
Forming a first mask partially open, and oxidizing the third semiconductor layer from the opening of the first mask;
Forming a second mask having an opening including a region oxidized in the first oxidation step, and oxidizing the third semiconductor layer from the opening of the second mask. ,
The oxidation step forms the oxide region having a contact region whose thickness is locally increased,
In the electrode forming step, the control electrode having a lower portion in contact with the contact region is formed . A first semiconductor layer; a second semiconductor layer formed on an upper surface of the first semiconductor layer and having a band gap larger than the first semiconductor layer and heterojunction with the first semiconductor layer; and an upper surface of the second semiconductor layer A laminated structure forming step of forming a laminated structure comprising: a third semiconductor layer formed on
A mask partially opened is formed on the top surface of the stacked structure, and the third semiconductor layer is oxidized from the opening of the mask to form an oxide region on a part of the top surface of the third semiconductor layer. An oxidation process;
A first electrode electrically connected to the first semiconductor layer; a second electrode electrically connected to the first semiconductor layer and formed apart from the first electrode in plan view; and in plan view An electrode forming step of forming a control electrode located between the first electrode and the second electrode and electrically connected to the third semiconductor layer via the oxide region,
In plan view, the end of the oxide region on the first electrode side is between the end of the control electrode on the first electrode side and the end of the first electrode on the control electrode side. Position to,
In plan view, the end of the oxide region on the second electrode side is between the end of the control electrode on the second electrode side and the end of the second electrode on the control electrode side. It is located,
The oxidation step comprises:
Forming a first mask partially open, and oxidizing the third semiconductor layer from the opening of the first mask;
Forming a second mask in which a portion included in the region oxidized in the first oxidation step is open, and oxidizing the third semiconductor layer from the opening of the second mask; Including
The oxidation step forms the oxide region having a contact region whose thickness is locally increased,
In the electrode forming step, the control electrode having a lower portion in contact with the contact region is formed .

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