JP5945463B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device in which a plurality of substrates on which circuit elements constituting pixels are arranged are electrically connected.

  In recent years, with the rapid spread of personal computers, the demand for digital cameras as image input devices is expanding. There are several factors that determine the image quality of a digital camera. Among these factors, the number of pixels of the image sensor is a large factor that determines the resolution of a captured image. For this reason, digital cameras having more than 12 million pixels have recently been commercialized.

  Known imaging devices include amplification type solid-state imaging devices represented by MOS type image sensors such as CMOS (Complementary Metal Oxide Semiconductor) and charge transfer type solid-state imaging devices represented by CCD (Charge Coupled Device) image sensors. Yes. These solid-state imaging devices are widely used for digital still cameras, digital video cameras, and the like. In recent years, MOS solid-state imaging devices having a low power supply voltage are often used from the viewpoint of power consumption as solid-state imaging devices mounted on mobile devices such as camera-equipped mobile phones and PDAs (Personal Digital Assistants).

  Conventionally, in such a MOS solid-state imaging device, a semiconductor chip in which a pixel region in which a plurality of pixels are arranged is electrically connected to a semiconductor chip in which a signal processing circuit is formed as one device. Various configured solid-state imaging devices have been proposed. For example, in Patent Document 1, a semiconductor chip in which a micropad is formed on the wiring layer side for each unit pixel cell or a cell in which a plurality of pixels are combined, and a micropad is formed on the wiring layer side at a position corresponding to the micropad of the semiconductor chip. A solid-state imaging device is disclosed in which the signal processing chip is connected by micro bumps.

  FIG. 10 shows a configuration of a conventional solid-state imaging device. A conventional solid-state imaging device is configured by vertically stacking a first substrate 201 having a MOS image sensor and a second substrate 202 having a signal processing circuit. Light enters the first substrate 201 from a surface opposite to the surface connected to the second substrate 202. That is, the first substrate 201 is configured such that a wiring layer is formed on the front surface side of the substrate, and light enters from the back surface side opposite to the surface on which the wiring layer is formed.

  In the wiring layer of the first substrate 201, as will be described later, a large number of micropads 203 are formed for each cell composed of unit pixels or for each cell in which a plurality of pixels are combined. A number of micropads 204 corresponding to the micropads 203 of the first substrate 201 are formed on the surface of the second substrate 202 on the wiring layer side. The first substrate 201 and the second substrate 202 are arranged so that the micropad 203 and the micropad 204 face each other. The micro pad 203 and the micro pad 204 are electrically connected and integrated through the micro bump 205. The micropads 203 and 204 are formed of micropads smaller than normal pads.

  The second substrate 202 is formed to have a larger area than the first substrate 201. A normal pad 206 is disposed on the surface of the second substrate 202 at a position corresponding to the outside of the first substrate 101. The pad 206 constitutes an interface with a system other than the system including two substrates.

  FIG. 11 shows the configuration of the first substrate 201. The first substrate 201 includes a pixel portion 208 in which a plurality of pixel cells 207 are two-dimensionally arranged, and a control circuit 209 that controls the pixel cells 207.

  FIG. 12 shows a circuit configuration in the pixel cell 207 of the first substrate 201. Here, one pixel cell is composed of four pixels. The pixel cell 207 includes four photoelectric conversion elements 221A, 221B, 221C, and 221D. The photoelectric conversion elements 221A, 221B, 221C, and 221D are connected to the sources of the corresponding four transfer transistors 222A, 222B, 222C, and 222D, respectively. The gates of the transfer transistors 222A, 222B, 222C, and 222D are connected to transfer wirings 227A, 227B, 227C, and 227D to which transfer pulses are supplied. The drains of the transfer transistors 222A, 222B, 222C, and 222D are commonly connected to the source of the reset transistor 223. Further, a charge holding unit FD called a so-called floating diffusion between the drains of the transfer transistors 222A, 222B, 222C, and 222D and the source of the reset transistor 223 is connected to the gate of the amplification transistor 224.

  The drain of the reset transistor 223 is connected to the power supply wiring 232, and the gate of the reset transistor 223 is connected to the reset wiring 228 to which a reset pulse is supplied. The drain of the activation transistor 225 is connected to the power supply wiring 232, and the source of the activation transistor 225 is connected to the drain of the amplification transistor 224. The gate of the activation transistor 225 is connected to an activation wiring 229 to which an activation pulse is supplied. The source of the amplification transistor 224 is connected to the drain of the injection transistor 230. The source of the injection transistor 230 is connected to the ground potential, and the gate of the injection transistor 230 is connected to the injection wiring 231 to which an injection pulse is supplied. A midpoint of connection between the amplification transistor 224 and the injection transistor 230 is connected to the output terminal 226.

  The photoelectric conversion elements 221A, 221B, 221C, and 221D are, for example, photodiodes, generate (generate) signal charges based on incident light, and hold and store the generated (generated) signal charges. The transfer transistors 222A, 222B, 222C, and 222D are transistors that transfer signal charges accumulated in the photoelectric conversion elements 221A, 221B, 221C, and 221D to the charge holding unit FD. On / off of the transfer transistors 222A, 222B, 222C, and 222D is controlled by transfer pulses supplied from the control circuit 209 via the transfer wirings 227A, 227B, 227C, and 227D. The charge holding unit FD constitutes an input unit of the amplification transistor 224, and is a floating diffusion capacitor that temporarily holds and accumulates signal charges transferred from the photoelectric conversion elements 221A, 221B, 221C, and 221D.

  The reset transistor 223 is a transistor that resets the charge holding unit FD. On / off of the reset transistor 223 is controlled by a reset pulse supplied from the control circuit 209 via the reset wiring 228. It is also possible to reset the photoelectric conversion elements 221A, 221B, 221C, and 221D by simultaneously turning on the reset transistor 223 and the transfer transistors 222A, 222B, 222C, and 222D.

  The amplification transistor 224 is a transistor that outputs, from a source, an amplified signal obtained by amplifying a signal based on the signal charge stored in the charge holding unit FD and input to the gate. The activation transistor 225 and the injection transistor 230 are transistors that supply a current for driving the amplification transistor 224 to the amplification transistor 224. The activation transistor 225 is turned on / off by an activation pulse supplied from the control circuit 209 via the activation wiring 229, and the injection transistor 230 is turned on / off from the control circuit 209 via the injection wiring 231. Controlled by the injection pulse supplied.

  The photoelectric conversion elements 221A, 221B, 221C, and 221D, transfer transistors 222A, 222B, 222C, and 222D, the reset transistor 223, the amplification transistor 224, the activation transistor 225, and the injection transistor 230 form a single pixel cell 207. Composed. In the conventional example, there is no vertical signal line on the first substrate 201 for outputting a signal to be read out of the substrate.

  Next, the operation of the pixel cell 207 will be described with reference to FIG. First, an injection pulse Pn1 is applied through the injection wiring 231 to turn on the injection transistor 230, and the potential of the output terminal 226 is fixed to 0V. Subsequently, a reset pulse Pr is applied via the reset wiring 228, the reset transistor 223 is turned on, and the potential of the charge holding portion FD is reset to a high level (power supply potential). When the potential of the charge holding portion FD becomes a high level, the amplification transistor 224 is turned on. Subsequently, after the application of the injection pulse Pn1 is released and the injection transistor 230 is turned off, the activation pulse Pk1 is applied via the activation wiring 229 and the activation transistor 225 is turned on. When the activation transistor 225 is turned on, the potential of the output terminal 226 rises to a potential corresponding to the potential of the charge holding portion FD. The potential of the output terminal 226 at this time is called a reset level.

  Subsequently, after the activation pulse Pk1 is released and the activation transistor 225 is turned off, the transfer pulse Pt1 is applied via the transfer wiring 227A to turn on the transfer transistor 222A, and the corresponding photoelectric conversion element 221A. Are transferred to the charge holding portion FD. Subsequently, an injection pulse Pn2 is applied via the injection wiring 231 to turn on the injection transistor 230, and the potential of the output terminal 226 becomes 0V. Subsequently, when the activation pulse Pk2 is applied via the activation wiring 229 and the activation transistor 225 is turned on, the potential of the output terminal 226 rises to a potential corresponding to the potential of the charge holding portion FD. The potential of the output terminal 226 at this time is called a signal level.

  A signal based on the potential of the output terminal 226 passes through the microbump 205 and enters the second substrate 202. The second substrate 202 detects the difference between the signal level and the reset level, digitizes an analog signal corresponding to the difference, demultiplexes and stores it in the memory, and sequentially outputs it from the solid-state imaging device. Here, the operation of reading the signal of one photoelectric conversion element 221A among the four photoelectric conversion elements 221A, 221B, 221C, and 221D has been described. A similar operation is sequentially performed for the other three photoelectric conversion elements 221B, 221C, and 221D.

  Although there is a slight difference in photosensitive timing among the photoelectric conversion elements 221A, 221B, 221C, and 221D by the above operation, the photosensitive timing is almost aligned within the screen, and the upper and lower sides of the pixel portion 208 are aligned. Thus, it is said that the synchronization of exposure can be realized, and the image processing speed can be improved without causing a large deterioration in image quality at the time of signal reading.

JP 2006-49361 A

  In the above-described prior art, although there is a slight difference in photosensitive timing among the four photoelectric conversion elements 221A, 221B, 221C, and 221D, the photosensitive timing is almost aligned within the screen, and At the bottom, it is possible to achieve exposure simultaneity. In order to realize this simultaneity of exposure, the above-described conventional solid-state imaging device holds an AD conversion circuit that converts an analog signal output from a pixel into a digital signal and the same number of digital signals as photoelectric conversion elements. And a memory.

  In the operation in the mode for displaying a live view image on the viewfinder and the mode for recording a moving image for HDTV, it is assumed that 60 frames or more per second, and in some cases 120 frames per second are required. Due to the recent increase in the number of pixels in digital cameras, it is necessary to operate many readout circuits in parallel in order to read out signals from all pixels at a high frame rate, which is realized by increasing the chip area and power consumption. It is very difficult.

  On the other hand, in live view image display and HDTV video mode, the number of pixels such as 12 million pixels or 16 million pixels is not necessary. Therefore, when reading a signal from the pixel, a method of reading out the signal by thinning out the pixel can be considered. However, when thinning is performed, moire or the like occurs, and the image quality deteriorates.

  The present invention has been made in view of the above-described problems, and an object thereof is to reduce deterioration in image quality.

  The present invention is a solid-state imaging device in which a first substrate and a second substrate are electrically connected, and the first substrate includes a plurality of first pixels arranged in a matrix. The second substrate includes a plurality of second pixels arranged in a matrix, and each of the plurality of first pixels has a color of first to nth (n is an integer of 2 or more). A photoelectric conversion element that generates a color signal corresponding to any one of the colors, and each of the plurality of second pixels includes a signal storage circuit that stores the color signal generated by the photoelectric conversion element. The solid-state imaging device includes an averaging circuit that averages each color signal accumulated in the signal accumulation circuit of two or more second pixels arranged in the same column, and the averaged color signal. An output circuit that outputs to the outside of the second pixel, and the mth (m is an integer from 1 to n) The first pixel having the photoelectric conversion element that generates a color signal corresponding to a color of the first pixel corresponds to the mth color, and the mth (m is any one of 1 to n) ) Is the second pixel corresponding to the m-th color, and the same color in the second substrate. The solid-state imaging device is characterized in that two or more second pixels corresponding to are arranged in the same column.

  In the solid-state imaging device according to the aspect of the invention, the averaging circuit may store the color signal stored in the signal storage circuit of two or more second pixels corresponding to the same color arranged in the same column. Are averaged.

  In the solid-state imaging device of the present invention, the first pixels are classified into a plurality of first groups, one of the first groups includes a plurality of the first pixels, and the second pixels are , Classified into a plurality of second groups associated with each of the plurality of first groups, one of the second groups including a plurality of the second pixels, and one of the first groups In the second group, two or more of the first pixels corresponding to a predetermined color among the first to nth colors are arranged in different columns, and in the second group, the two or more of the first pixel corresponding to the predetermined color Second pixels are arranged in the same column, and the averaging circuit is accumulated in the signal accumulation circuit of two or more second pixels corresponding to the predetermined color arranged in the same column. The color signals are averaged.

  In the solid-state imaging device according to the present invention, two or more second pixels corresponding to the predetermined color are arranged adjacent to the same column.

  In the solid-state imaging device of the present invention, the averaging circuit averages the accumulated color signals at different timings for each of the second groups after the color signals are accumulated in the signal accumulation circuit. It is characterized by that.

  In the solid-state imaging device of the present invention, the output circuit outputs an averaged color signal from a part of the second pixels obtained by thinning out the second pixels in the column direction. .

  According to the present invention, each color signal accumulated in a signal accumulation circuit included in each of two or more pixels targeted for averaging is averaged to form an image formed by each signal output from the pixel. Generation of moiré can be suppressed and random noise components included in the signal can be reduced. Therefore, deterioration in image quality can be reduced.

It is a block diagram which shows the structure of the imaging device to which the solid-state imaging device by one Embodiment of this invention is applied. It is sectional drawing of the solid-state imaging device by one Embodiment of this invention. It is a block diagram which shows the structure of the solid-state imaging device by one Embodiment of this invention. It is a block diagram which shows the structure of the solid-state imaging device by one Embodiment of this invention. It is a reference figure showing a group which a pixel of a solid imaging device by one embodiment of the present invention comprises. It is a circuit diagram which shows the circuit structure of the pixel with which the solid-state imaging device by one Embodiment of this invention is provided. It is a circuit diagram which shows the structure of the circuit arrange | positioned between the pixels with which the solid-state imaging device by one Embodiment of this invention is provided. It is a timing chart which shows operation | movement of the pixel with which the solid-state imaging device by one Embodiment of this invention is provided. It is a timing chart which shows operation | movement of the pixel with which the solid-state imaging device by one Embodiment of this invention is provided. It is sectional drawing which shows the structure of the conventional solid-state imaging device. It is a block diagram which shows the structure of the 1st board | substrate which the conventional solid-state imaging device has. It is a circuit diagram which shows the circuit structure of the pixel cell of the 1st board | substrate which the conventional solid-state imaging device has. It is a timing chart which shows operation | movement of the pixel which the conventional solid-state imaging device has.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration of a digital camera as an example of an imaging apparatus to which the solid-state imaging apparatus according to the present embodiment is applied. The imaging device according to one embodiment of the present invention may be an electronic device having an imaging function, and may be a digital video camera, an endoscope, or the like in addition to a digital camera. A digital camera 10 shown in FIG. 1 includes a lens unit 1, a lens control device 2, a solid-state imaging device 3, a drive circuit 4, a memory 5, a signal processing circuit 6, a recording device 7, a control device 8, and a display device 9.

  The lens unit 1 includes a zoom lens and a focus lens, and forms light from the subject as a subject image on the light receiving surface of the solid-state imaging device 3. The lens control device 2 controls zoom, focus, aperture, and the like of the lens unit 1. The light taken in via the lens unit 1 is imaged on the light receiving surface of the solid-state imaging device 3. The solid-state imaging device 3 converts the subject image formed on the light receiving surface into an image signal and outputs the image signal. A plurality of pixels are two-dimensionally arranged in the row direction and the column direction on the light receiving surface of the solid-state imaging device 3.

  The drive circuit 4 drives the solid-state imaging device 3 and controls its operation. The memory 5 temporarily stores image data. The signal processing circuit 6 performs a predetermined process on the image signal output from the solid-state imaging device 3. Processing performed by the signal processing circuit 6 includes amplification of an image signal, various corrections of image data, compression of image data, and the like.

  The recording device 7 includes a semiconductor memory for recording or reading image data, and is built in the digital camera 10 in a detachable state. The display device 9 displays a moving image (live view image), displays a still image, displays a moving image and a still image recorded in the recording device 7, displays a state of the digital camera 10, and the like.

  The control device 8 controls the entire digital camera 10. The operation of the control device 8 is defined by a program stored in a ROM built in the digital camera 10. The control device 8 reads out this program and performs various controls according to the contents defined by the program.

  FIG. 2 shows a cross-sectional structure of the solid-state imaging device 3. The solid-state imaging device 3 has a structure in which two substrates (first substrate 20 and second substrate 21) on which circuit elements (photoelectric conversion elements, transistors, capacitors, etc.) constituting pixels are arranged overlap each other. Circuit elements constituting the pixels are distributed and arranged on the first substrate 20 and the second substrate 21. The first substrate 20 and the second substrate 21 are electrically connected so that an electric signal can be exchanged between the two substrates when the pixels are driven.

  Of the two main surfaces of the first substrate 20 (surface having a relatively larger surface area than the side surface), a photoelectric conversion element is formed on the main surface side on which the light L is irradiated. The irradiated light enters the photoelectric conversion element. Of the two main surfaces of the first substrate 20, a connection portion 250 for connecting to the second substrate 21 is formed on the main surface opposite to the main surface on which the light L is irradiated. A signal based on the signal charge generated by the photoelectric conversion element arranged on the first substrate 20 is output to the second substrate 21 via the connection unit 250. In the example illustrated in FIG. 2, the areas of the main surfaces of the first substrate 20 and the second substrate 21 are different, but the areas of the main surfaces of the first substrate 20 and the second substrate 21 may be the same.

  FIG. 3 shows the configuration of the solid-state imaging device 3 on the first substrate 20. As shown in FIG. 3, the solid-state imaging device 3 includes a pixel unit 200A and a vertical scanning circuit 300A. The pixel unit 200A includes pixels 100A arranged in a two-dimensional matrix. In FIG. 3, the pixels 100A are arranged in 4 rows and 4 columns, but the arrangement of the pixels is not limited to this, and the number of rows and the number of columns may be two or more. The array of the pixels 100A is a Bayer array in which four pixels corresponding to red (R), green (Gr, Gb), and blue (B) are used as a unit of the array. The color of the pixel 100A corresponds to the color of the color filter arranged on the pixel 100A. For example, when an R color filter is disposed on the pixel 100A, the pixel 100A corresponds to R. Photoelectric conversion elements in the pixel 100A (photoelectric conversion elements 201, 202, 203, and 204 described later) accumulate signal charges corresponding to the colors of the color filters arranged on the pixel 100A.

  The vertical scanning circuit 300A controls the driving of the pixel portion 200A in units of rows. In order to perform this drive control, the vertical scanning circuit 300A includes unit circuits 301A-1, 301A-2, 301A-3, and 301A-4, which are the same number as the number of rows. Each unit circuit 301A-i (i = 1, 2, 3, 4) outputs a control signal for controlling the pixels 100A for one row to the signal line 110A provided for each row. The signal line 110A is connected to the pixel 100A, and supplies the control signal output from the unit circuit 301A-i to the pixel 100A. In FIG. 3, each signal line 110A corresponding to each row is represented by a single line, but each signal line 110A includes a plurality of signal lines.

  FIG. 4 shows the configuration of the solid-state imaging device 3 on the second substrate 21. As shown in FIG. 4, the solid-state imaging device 3 includes a pixel unit 200B, a vertical scanning circuit 300B, a column processing circuit 350, a horizontal scanning circuit 400, and an output amplifier 410.

  The pixel unit 200B includes pixels 100B arranged in a two-dimensional matrix and a current source 130 provided for each column. In FIG. 4, the pixels 100 </ b> B are arranged in 4 rows and 4 columns, but the arrangement of the pixels is not limited to this, and the number of rows and columns may be two or more. The color arrangement corresponding to the pixel 100B is different from the color arrangement corresponding to the pixel 100A. Specifically, the pixel 100B corresponding to B is arranged in the first column, the pixel 100B corresponding to Gr is arranged in the second column, the pixel 100B corresponding to R is arranged in the third column, and corresponds to Gr. The pixels 100B to be arranged are arranged in the fourth column. Thereby, as a whole of the pixel portion 200B, the pixels 100B corresponding to the same color are arranged in the same column. The color of the pixel 100B corresponds to the color of the pixel 100A that has generated the signal charge accumulated in the pixel 100B. For example, a pixel 100B that accumulates signal charges generated in the pixel 100A corresponding to R corresponds to R.

  The pixel 100B is connected to the vertical signal line 120 arranged for each column. The current source 130 is connected to the vertical signal line 120, and forms a source follower circuit with amplification transistors (second amplification transistors 241, 242, 243, and 244 described later) in the pixel 100B.

  The vertical scanning circuit 300B performs drive control of the pixel portion 200B in units of rows. In order to perform this drive control, the vertical scanning circuit 300B includes unit circuits 301B-1, 301B-2, 301B-3, and 301B-4, which are the same number as the number of rows. Each unit circuit 301B-i (i = 1, 2, 3, 4) outputs a control signal for controlling the pixels 100B for one row to the signal line 110B provided for each row. The signal line 110B is connected to the pixel 100B, and supplies the control signal output from the unit circuit 301B-i to the pixel 100B. In FIG. 4, each signal line 110B corresponding to each row is represented by one line, but each signal line 110B includes a plurality of signal lines. The pixel signal of the pixel 100B in the row selected by the control signal is output to the vertical signal line 120.

  The column processing circuit 350 performs signal processing such as noise suppression on the pixel signal output to the vertical signal line 120. An output channel 430 (horizontal signal line, output signal line) is connected to the column processing circuit 350 provided corresponding to each column, and an output amplifier 410 is connected to the output channel 430. The horizontal scanning circuit 400 outputs the pixel signals of one row of pixels 100 </ b> B output to the vertical signal line 120 and processed by the column processing circuit 350 to the output amplifier 410 in time series in the horizontal order. The output amplifier 410 amplifies the input pixel signal and outputs it to the outside of the solid-state imaging device 3 as an image signal.

  In this embodiment, the column processing circuit 350, the horizontal scanning circuit 400, and the output amplifier 410 are disposed on the second substrate 21, but these may be disposed on the first substrate 20. Further, circuit elements constituting each of the column processing circuit 350, the horizontal scanning circuit 400, and the output amplifier 410 may be distributed on the first substrate 20 and the second substrate 21.

  In the present embodiment, an area composed of all pixels of the solid-state imaging device 3 is set as a pixel signal readout target area, but a part of an area composed of all pixels of the solid-state imaging apparatus 3 may be set as a readout target area. It is desirable that the read target area includes at least all pixels in the effective pixel area. Further, the read target area may include an optical black pixel (a pixel that is always shielded from light) arranged outside the effective pixel area. The pixel signal read from the optical black pixel is used for correcting a dark current component, for example.

  In the present embodiment, the plurality of pixels 100 </ b> A share one connection unit 250, and the plurality of pixels 100 </ b> B share one connection unit 250. In addition, a plurality of pixels 100A sharing one connection unit 250 form the same group, and a plurality of pixels 100B sharing one connection unit 250 form the same group. FIG. 5 shows an example of a group formed by the pixel 100A and a group formed by the pixel 100B. FIG. 5A shows a group formed by the pixel 100A, and FIG. 5B shows a group formed by the pixel 100B. 5 shows the arrangement of some of the pixels 100A and 100B among the pixels 100A and 100B constituting the pixel portions 200A and 200B, the arrangement of the remaining pixels 100A and 100B is the same as the arrangement shown in FIG. is there.

  As shown in FIG. 5A, in the first substrate 20, four pixels 100 </ b> A arranged in one row and four columns share one connection unit 250. Specifically, the pixels 100A-1 and 100A-3 corresponding to B arranged in the first and first columns in the first row and the second and fourth columns in the first row in the array of FIG. The pixels 100 </ b> A- 2 and 100 </ b> A- 4 corresponding to Gb arranged in the same share the connection part 250-1. These four pixels 100A-1, 100A-2, 100A-3, and 100A-4 constitute a group G1. Further, two pixels 100A corresponding to Gr arranged in the second row and first and third columns in the array of FIG. 5A and R arranged in the second row and second and fourth columns. The corresponding two pixels 100A share the connection part 250-2. These four pixels 100A form a group G2.

  Further, two pixels 100A corresponding to B arranged in the third row and the first and third columns in the arrangement of FIG. 5A and Gb arranged in the third row and the second and fourth columns. The corresponding two pixels 100A share the connection part 250-3. These four pixels 100A form a group G3. Further, in the array of FIG. 5A, two pixels 100A corresponding to Gr arranged in the fourth row and first and third columns, and R arranged in the fourth row and second and fourth columns. The corresponding two pixels 100A share the connection part 250-4. These four pixels 100A form a group G4.

  As shown in FIG. 5B, in the second substrate 21, the four pixels 100 </ b> B arranged in 2 rows and 2 columns share one connection portion 250. Specifically, the pixels 100B-1 and 100B-3 corresponding to B arranged in the first column of the first and second rows in the array of FIG. 5B and the second column of the first and second rows. The pixels 100B-2 and 100B-4 corresponding to Gb arranged in the same share the connection part 250-1. These four pixels 100B-1, 100B-2, 100B-3, 100B-4 constitute a group G1 '. Further, in the array of FIG. 5B, two pixels 100B corresponding to R arranged in the third column of the first row and the second row, and Gr arranged in the fourth column of the first row and the second row. The corresponding two pixels 100B share the connection part 250-2. These four pixels 100B form a group G2 '.

  Further, in the array of FIG. 5B, two pixels 100B corresponding to B arranged in the first column of the third and fourth rows, and Gb arranged in the second column of the third and fourth rows. The corresponding two pixels 100B share the connection part 250-3. These four pixels 100B form a group G3 '. Further, two pixels 100B corresponding to R arranged in the third column of the third and fourth rows in the array of FIG. 5B and Gr arranged in the fourth column of the third and fourth rows are arranged. The corresponding two pixels 100B share the connection part 250-4. These four pixels 100B form a group G4 '.

  As described above, the connection portions 250 and the groups are arranged so that a total of 16 pixels in the four groups on the second substrate 21 correspond to a total of 16 pixels in the four groups on the first substrate 20. It is determined.

  Each pixel 100A in the group G1 corresponds to each pixel 100B in the group G1 '. That is, the signal charge generated in the pixel 100A in the group G1 is input and accumulated in the pixel 100B in the group G1 'via the connection unit 250-1. In addition, each pixel 100A in the group G2 corresponds to each pixel 100B in the group G2 '. That is, the signal charge generated in the pixel 100A in the group G2 is input and accumulated in the pixel 100B in the group G2 'via the connection unit 250-2.

  Each pixel 100A in the group G3 corresponds to each pixel 100B in the group G1 '. That is, the signal charge generated in the pixel 100A in the group G3 is input and accumulated in the pixel 100B in the group G1 'via the connection unit 250-3. Also, each pixel 100A in the group G4 corresponds to each pixel 100B in the group G4 '. That is, the signal charge generated in the pixel 100A in the group G4 is input and accumulated in the pixel 100B in the group G4 'via the connection unit 250-4.

  The vertical scanning circuits 300A and 300B associate each pixel 100A in the group G1 with each pixel 100B in the group G1 ′, and each pixel 100A in the group G2 and each pixel 100B in the group G2 ′. , Each pixel 100A in the group G3 and each pixel 100B in the group G3 ′ are associated, each pixel 100A in the group G4 and each pixel 100B in the group G4 ′ are associated, A control signal for controlling the pixels 100A and 100B is generated and output to the pixels 100A and 100B via the signal lines 110A and 110B.

  Next, the configuration of the pixels 100A and 100B will be described. FIG. 6 shows a circuit configuration of four pixels 100A and four pixels 100B sharing one connection portion 250. The group composed of four pixels 100A arranged on the first substrate 20 includes photoelectric conversion elements 201, 202, 203, 204, first transfer transistors 211, 212, 213, 214, and a charge holding unit 230 (floating). Diffusion), a first reset transistor 220, a first amplification transistor 240, and a current source 280. The group composed of four pixels 100B arranged on the second substrate 21 includes a clamp capacitor 260, second transfer transistors 271, 272, 273, 274, second reset transistors 221, 222, 223, 224, Analog memories 231, 232, 233, and 234, second amplification transistors 241, 242, 243, and 244, and selection transistors 291, 292, 293, and 294 are included. The arrangement position of each circuit element shown in FIG. 6 does not necessarily coincide with the actual arrangement position.

  The correspondence between the pixel 100A in the group G1 in FIG. 5A and each circuit element in FIG. 6 is as follows. The pixel 100A-1 includes a photoelectric conversion element 201, a first transfer transistor 211, a charge holding unit 230, a first reset transistor 220, a first amplification transistor 240, and a current source 280. The pixel 100A-2 includes a photoelectric conversion element 202, a first transfer transistor 212, a charge holding unit 230, a first reset transistor 220, a first amplification transistor 240, and a current source 280. The pixel 100A-3 includes a photoelectric conversion element 203, a first transfer transistor 213, a charge holding unit 230, a first reset transistor 220, a first amplification transistor 240, and a current source 280. The pixel 100A-4 includes a photoelectric conversion element 204, a first transfer transistor 214, a charge holding unit 230, a first reset transistor 220, a first amplification transistor 240, and a current source 280. The charge holding unit 230, the first reset transistor 220, the first amplification transistor 240, and the current source 280 are shared by the four pixels 100A. The correspondence relationship between the pixels 100A in the groups G2, G3, and G4 in FIG. 5A and the circuit elements in FIG. 6 is the same as described above.

  The correspondence relationship between the pixels 100B in the group G1 'in FIG. 5B and the circuit elements in FIG. 6 is as follows. The pixel 100B-1 includes a clamp capacitor 260, a second transfer transistor 271, a second reset transistor 221, an analog memory 231, a second amplification transistor 241, and a selection transistor 291. The pixel 100B-2 includes a clamp capacitor 260, a second transfer transistor 272, a second reset transistor 222, an analog memory 232, a second amplification transistor 242, and a selection transistor 292. The pixel 100B-2 includes a clamp capacitor 260, a second transfer transistor 273, a second reset transistor 223, an analog memory 233, a second amplification transistor 243, and a selection transistor 293. The pixel 100B-6 includes a clamp capacitor 260, a second transfer transistor 274, a second reset transistor 224, an analog memory 234, a second amplification transistor 244, and a selection transistor 294. The clamp capacitor 260 is shared by the four pixels 100B. The correspondence between the pixels 100B in the groups G2 ', G3', and G4 'in FIG. 5B and the circuit elements in FIG. 6 is the same as described above.

  One ends of the photoelectric conversion elements 201, 202, 203, and 204 are grounded. The drain terminals of the first transfer transistors 211, 212, 213, and 214 are connected to the other ends of the photoelectric conversion elements 201, 202, 203, and 204. The gate terminals of the first transfer transistors 211, 212, 213, and 214 are connected to the vertical scanning circuit 300A, and transfer pulses ΦTX1-1, ΦTX1-2, ΦTX1-3, and ΦTX1-4 are supplied.

  One end of the charge holding unit 230 is connected to the source terminals of the first transfer transistors 211, 212, 213, and 214, and the other end of the charge holding unit 230 is grounded. The drain terminal of the first reset transistor 220 is connected to the power supply voltage VDD, and the source terminal of the first reset transistor 220 is connected to the source terminals of the first transfer transistors 211, 212, 213, and 214. The gate terminal of the first reset transistor 220 is connected to the vertical scanning circuit 300A, and the reset pulse ΦRST1 is supplied.

  The drain terminal of the first amplification transistor 240 is connected to the power supply voltage VDD. A gate terminal which is an input portion of the first amplification transistor 240 is connected to the source terminals of the first transfer transistors 211, 212, 213 and 214. One end of the current source 280 is connected to the source terminal of the first amplification transistor 240, and the other end of the current source 280 is grounded. As an example, the current source 280 may be configured by a transistor having a drain terminal connected to the source terminal of the first amplification transistor 240, a source terminal grounded, and a gate terminal connected to the vertical scanning circuit 300A. One end of the clamp capacitor 260 is connected to the source terminal of the first amplification transistor 240 and one end of the current source 280 via the connection part 250.

  The drain terminals of the second transfer transistors 271, 272, 273 and 274 are connected to the other end of the clamp capacitor 260. The gate terminals of the second transfer transistors 271, 272, 273, and 274 are connected to the vertical scanning circuit 300B, and transfer pulses ΦTX2-1, ΦTX2-2, ΦTX2-3, and ΦTX2-4 are supplied. The drain terminals of the second reset transistors 221, 222, 223, 224 are connected to the power supply voltage VDD, and the source terminals of the second reset transistors 221, 222, 223, 224 are the second transfer transistors 271, 272, 273, 274. Connected to the source terminal. The gate terminals of the second reset transistors 221, 222, 223, and 224 are connected to the vertical scanning circuit 300B, and reset pulses ΦRST2-1, ΦRST2-2, ΦRST2-3, and ΦRST2-4 are supplied.

  One ends of the analog memories 231, 232, 233, and 234 are connected to the source terminals of the second transfer transistors 271, 272, 273, and 274, and the other ends of the analog memories 231, 232, 233, and 234 are grounded. The drain terminals of the second amplification transistors 241, 242, 243, and 244 are connected to the power supply voltage VDD. The gate terminals constituting the input parts of the second amplification transistors 241, 242, 243, 244 are connected to the source terminals of the second transfer transistors 271, 272, 273, 274. The drain terminals of the selection transistors 291, 292, 293 and 294 are connected to the source terminals of the second amplification transistors 241, 242, 243 and 244. The source terminals of the selection transistors 291 and 293 are connected to the vertical signal lines 120 in the odd columns, and the source terminals of the selection transistors 292 and 294 are connected to the vertical signal lines 120 in the even columns. The gate terminals of the selection transistors 291, 292, 293, and 294 are connected to the vertical scanning circuit 300B, and selection pulses ΦSEL1, ΦSEL2, ΦSEL3, and ΦSEL4 are supplied. For each of the transistors described above, the polarity may be reversed, and the source terminal and the drain terminal may be reversed.

  The photoelectric conversion elements 201, 202, 203, and 204 are, for example, photodiodes, generate (generate) signal charges based on incident light, and hold and store the generated (generated) signal charges. The first transfer transistors 211, 212, 213, and 214 are transistors that transfer signal charges accumulated in the photoelectric conversion elements 201, 202, 203, and 204 to the charge holding unit 230. On / off of the first transfer transistors 211, 212, 213, and 214 is controlled by transfer pulses ΦTX1-1, ΦTX1-2, ΦTX1-3, and ΦTX1-4 from the vertical scanning circuit 300A. The charge holding unit 230 is a floating diffusion capacitor that temporarily holds and accumulates signal charges transferred from the photoelectric conversion elements 201, 202, 203, and 204.

  The first reset transistor 220 is a transistor that resets the charge holding unit 230. ON / OFF of the first reset transistor 220 is controlled by a reset pulse ΦRST1 from the vertical scanning circuit 300A. It is also possible to reset the photoelectric conversion elements 201, 202, 203, and 204 by simultaneously turning on the first reset transistor 220 and the first transfer transistors 211, 212, 213, and 214. The reset of the charge holding unit 230 / photoelectric conversion elements 201, 202, 203, and 204 is performed by controlling the amount of charge accumulated in the charge holding unit 230 / photoelectric conversion elements 201, 202, 203, and 204. The state (potential) of the photoelectric conversion elements 201, 202, 203, 204 is set to the reference state (reference potential, reset level).

  The first amplification transistor 240 is a transistor that outputs an amplified signal obtained by amplifying a signal based on the signal charge input to the gate terminal and accumulated in the charge holding unit 230 from the source terminal. The current source 280 functions as a load of the first amplification transistor 240 and supplies a current for driving the first amplification transistor 240 to the first amplification transistor 240. The first amplification transistor 240 and the current source 280 form a source follower circuit.

  The clamp capacitor 260 is a capacitor that clamps (fixes) the voltage level of the amplified signal output from the first amplification transistor 240. The second transfer transistors 271, 272, 273, and 274 are transistors that sample and hold the voltage level at the other end of the clamp capacitor 260 and accumulate them in the analog memories 231, 232, 233, and 234. On / off of the second transfer transistors 271, 272, 273, and 274 is controlled by transfer pulses ΦTX2-1, ΦTX2-2, ΦTX2-3, and ΦTX2-4 from the vertical scanning circuit 300B.

  The second reset transistors 221, 222, 223, and 224 are transistors that reset the analog memories 231, 232, 233, and 234. On / off of the second reset transistors 221, 222, 223, and 224 is controlled by reset pulses ΦRST2-1, ΦRST2-2, ΦRST2-3, and ΦRST2-4 from the vertical scanning circuit 300B. The analog memories 231, 232, 233, and 234 are reset by controlling the amount of charge stored in the analog memories 231, 232, 233, and 234, and setting the states (potentials) of the analog memories 231, 232, 233, and 234 to the reference state (Reference potential, reset level). The analog memories 231, 232, 233, and 234 hold and store the analog signals sampled and held by the second transfer transistors 271, 272, 273, and 274.

  The capacity of the analog memories 231, 232, 233, and 234 is set to be larger than the capacity of the charge holding unit 230. For the analog memories 231, 232, 233, and 234, it is more preferable to use a MIM (Metal Insulator Metal) capacity or a MOS (Metal Oxide Semiconductor) capacity, which is a capacity with a small leakage current (dark current) per unit area. Thereby, resistance to noise is improved, and a high-quality signal can be obtained.

  The second amplification transistors 241, 242, 243 and 244 output from the source terminal an amplified signal obtained by amplifying a signal based on the signal charges stored in the analog memories 231, 232, 233 and 234 input to the gate terminal. It is a transistor. The second amplification transistors 241, 242, 243, and 244 and the current source 130 connected to the vertical signal line 120 form a source follower circuit. The selection transistors 291, 292, 293, and 294 are transistors that select the pixel 100B and transmit the output of the second amplification transistors 241, 242, 243, and 244 to the vertical signal line 120. On / off of the selection transistors 291, 292, 293, and 294 is controlled by selection pulses ΦSEL1, ΦSEL2, ΦSEL3, and ΦSEL4 from the vertical scanning circuit 300B.

  As described above, the pixel 100B in which the second reset transistor 221 and the selection transistor 291 are arranged corresponds to the pixel 100B-1 in FIG. 5B, and the second reset transistor 222 and the selection transistor 292 are arranged. The pixel 100B corresponds to the pixel 100B-2 in FIG. 5B, and the pixel 100B-1 and the pixel 100B-2 are arranged in the same row. As will be described later, since the operations of the second reset transistors 221 and 222 during the signal readout period are performed simultaneously, the reset pulse ΦRST2-1 may be supplied to both of the second reset transistors 221 and 222. As will be described later, since the operations of the selection transistors 291 and 292 during the signal reading period are performed simultaneously, the selection pulse ΦSEL1 may be supplied to both the selection transistors 291 and 292.

  A connection unit 250 is disposed between the first substrate 20 and the second substrate 21. The amplified signal output from the first amplification transistor 240 of the first substrate 20 is output to the second substrate 21 via the connection unit 250.

  In FIG. 6, the connection part 250 is disposed on the path between the source terminal of the first amplification transistor 240 and one end of the current source 280 and one end of the clamp capacitor 260, but this is not restrictive. The connecting portion 250 may be disposed anywhere on the electrically connected path from the first transfer transistors 211, 212, 213, 214 to the second transfer transistors 271, 272, 273, 274.

  For example, it is connected to a path between the source terminals of the first transfer transistors 211, 212, 213, and 214 and one end of the charge holding unit 230, the source terminal of the first reset transistor 220, and the gate terminal of the first amplification transistor 240. The part 250 may be arranged. Alternatively, the connection part 250 may be arranged in a path between the other end of the clamp capacitor 260 and the drain terminals of the second transfer transistors 271, 272, 273, 274.

  FIG. 7 shows only the circuit configuration related to the pixels 100B in the groups G1 'and G3' in FIG. 5 among the circuit configurations arranged between the pixels 100B arranged on the second substrate 21. On the second substrate 21, averaging transistors 275 and 276 that perform an averaging process for averaging the signal charges accumulated in the plurality of analog memories of the pixel 100B are arranged.

  One of the source terminal and the drain terminal of the averaging transistor 275 is connected to one end of the analog memories 231 and 233 of the pixel 100B in the group G1 '. The other of the source terminal and the drain terminal of the averaging transistor 275 is connected to one end of the analog memories 231 and 233 of the pixel 100B in the group G3 '. Although not shown, one ends of the analog memories 231 and 233 are connected to the source terminals of the second transfer transistors 271 and 273. The gate terminal of the averaging transistor 275 is connected to the vertical scanning circuit 300B and is supplied with an averaging pulse ΦMIX.

  One of the source terminal and the drain terminal of the averaging transistor 276 is connected to one end of the analog memories 232 and 234 of the pixel 100B in the group G1 '. The other of the source terminal and the drain terminal of the averaging transistor 276 is connected to one end of the analog memories 232 and 234 of the pixel 100B in the group G3 '. Although not shown, one ends of the analog memories 232 and 234 are connected to the source terminals of the second transfer transistors 272 and 274. The gate terminal of the averaging transistor 276 is connected to the vertical scanning circuit 300B, and the averaging pulse ΦMIX is supplied.

  The averaging transistor 275 averages signal charges stored in the analog memories 231 and 233 in the group G1 'and the analog memories 231 and 233 in the group G3', respectively. In other words, the averaging transistor 275 averages the signal charges stored in the analog memories of the four pixels 100B corresponding to B arranged in the same column. On / off of the averaging transistor 275 is controlled by a selection pulse ΦMIX from the vertical scanning circuit 300B.

  The averaging transistor 276 averages the signal charges stored in the analog memories 232 and 234 in the group G1 'and the analog memories 232 and 234 in the group G3', respectively. That is, the averaging transistor 276 averages the signal charges accumulated in the analog memories of the four pixels 100B corresponding to Gb arranged in the same column. On / off of the averaging transistor 276 is controlled by a selection pulse ΦMIX from the vertical scanning circuit 300B.

  Similarly, an averaging transistor that averages the signal charges accumulated in the analog memories 231 and 233 in the group G2 ′ and the analog memories 231 and 233 in the group G4 ′, and the analog memory 232 in the group G2 ′. , 234 and analog transistors 232 and 234 in the group G4 ′ are also arranged with averaging transistors for averaging the signal charges accumulated therein.

  Next, the operation of the pixel 100A and the pixel 100B will be described with reference to FIG. FIG. 8 shows control signals supplied to the pixels 100A and 100B for each row from the vertical scanning circuits 300A and 300B. However, the four pixels 100A in the same group where the first transfer transistors 211, 212, 213, and 214 to which the transfer pulses ΦTX1-1, ΦTX1-2, ΦTX1-3, and ΦTX1-4 are supplied are arranged. Since they are arranged in different columns of the same row, four types of transfer pulses ΦTX1-1, ΦTX1-2, ΦTX1-3, and ΦTX1-4 are supplied from the vertical scanning circuit 300A to the same row. Hereinafter, the operation will be described in units of a group including the four pixels 100A and a group including the four pixels 100B illustrated in FIG.

[Operation during period T1]
First, when the reset pulse ΦRST1 changes from “L” (Low) level to “H” (High) level, the first reset transistor 220 is turned on. At the same time, the transfer pulse ΦTX1-1 changes from the “L” level to the “H” level, whereby the first transfer transistor 211 is turned on. As a result, the photoelectric conversion element 201 is reset.

  Subsequently, when the reset pulse ΦRST1 and the transfer pulse ΦTX1-1 change from the “H” level to the “L” level, the first reset transistor 220 and the first transfer transistor 211 are turned off. Thereby, resetting of the photoelectric conversion element 201 is completed, and exposure (accumulation of signal charge) is started. In the same manner as described above, the photoelectric conversion elements 202, 203, and 204 are sequentially reset, and exposure is started. In FIG. 7, the reset pulse ΦRST1 is at the “H” level at the timing when the transfer pulses ΦTX1-1, ΦTX1-2, ΦTX1-3, and ΦTX1-4 are at the “H” level. , 203, and 204, the reset pulse ΦRST1 may always be at the “H” level.

[Operation during period T2]
Subsequently, when the reset pulse ΦRST2-1 changes from the “L” level to the “H” level, the second reset transistor 221 is turned on. As a result, the analog memory 231 is reset. At the same time, the transfer pulse ΦTX2-1 changes from the “L” level to the “H” level, whereby the second transfer transistor 271 is turned on. As a result, the potential at the other end of the clamp capacitor 260 is reset to the power supply voltage VDD, and the second transfer transistor 271 starts to sample and hold the potential at the other end of the clamp capacitor 260.

  Subsequently, when the reset pulse ΦRST1 changes from the “L” level to the “H” level, the first reset transistor 220 is turned on. As a result, the charge holding unit 230 is reset. Subsequently, when the reset pulse ΦRST1 changes from the “H” level to the “L” level, the first reset transistor 220 is turned off. Thereby, the reset of the charge holding unit 230 is completed. The timing for resetting the charge holding unit 230 may be during the exposure period, but by resetting the charge holding unit 230 at a timing immediately before the end of the exposure period, noise due to the leakage current of the charge holding unit 230 is further reduced. can do.

  Subsequently, when the reset pulse ΦRST2-1 changes from the “H” level to the “L” level, the second reset transistor 221 is turned off. As a result, the reset of the analog memory 231 is completed. At this time, the clamp capacitor 260 clamps the amplified signal (the amplified signal after resetting the charge holding unit 230) output from the first amplification transistor 240.

[Operation during period T3]
First, when the transfer pulse ΦTX1-1 changes from the “L” level to the “H” level, the first transfer transistor 211 is turned on. As a result, the signal charge accumulated in the photoelectric conversion element 201 is transferred to the charge holding unit 230 via the first transfer transistor 211 and accumulated in the charge holding unit 230. This completes the exposure (accumulation of signal charge). The period from the start of exposure in period T1 to the end of exposure in period T3 is an exposure period (signal accumulation period). Subsequently, when the transfer pulse ΦTX1-1 changes from the “H” level to the “L” level, the first transfer transistor 211 is turned off.

  Subsequently, when the transfer pulse ΦTX2-1 changes from the “H” level to the “L” level, the second transfer transistor 271 is turned off. As a result, the second transfer transistor 271 finishes sampling and holding the potential at the other end of the clamp capacitor 260.

[Operation during period T4]
The operation in the above-described periods T2 and T3 is the operation of one pixel 100A among the four pixels 100A constituting one group. In the period T4, operations similar to those in the periods T2 and T3 are performed on the remaining three pixels 100A. It is more desirable that the length of the exposure period of each pixel is the same.

  Hereinafter, a change in potential at one end of the analog memory 231 will be described. The same applies to changes in the potential at one end of the analog memories 232, 233, and 234. The change in potential at one end of the charge holding unit 230 due to the transfer of the signal charge from the photoelectric conversion element 201 to the charge holding unit 230 after the reset of the charge holding unit 230 is completed, and the gain of the first amplification transistor 240 is α1. Then, the change ΔVamp1 of the potential of the source terminal of the first amplification transistor 240 due to the transfer of the signal charge from the photoelectric conversion element 201 to the charge holding unit 230 is α1 × ΔVfd.

When the total gain of the analog memory 231 and the second transfer transistor 271 is α2, one end of the analog memory 231 is sampled and held by the second transfer transistor 271 after the signal charge is transferred from the photoelectric conversion element 201 to the charge holding unit 230. The potential change ΔVmem is α2 × ΔVamp1, that is, α1 × α2 × ΔVfd. Since the potential of one end of the analog memory 231 at the time when the reset of the analog memory 231 is completed is the power supply voltage VDD, the signal charge is transferred from the photoelectric conversion element 201 to the charge holding unit 230 and then sampled by the second transfer transistor 271. The held potential Vmem at one end of the analog memory 231 is expressed by the following equation (1). In the equation (1), ΔVmem <0 and ΔVfd <0.
Vmem = VDD + ΔVmem
= VDD + α1 × α2 × ΔVfd (1)

  Α2 is expressed by the following equation (2). In the equation (2), CL is a capacitance value of the clamp capacitor 260, and CSH is a capacitance value of the analog memory 231. In order to further reduce the decrease in gain, the capacitance CL of the clamp capacitor 260 is more desirably larger than the capacitance CSH of the analog memory 231.

[Operation during period T5]
First, when the averaging pulse ΦMIX changes from the “L” level to the “H” level, the averaging transistors 275 and 276 are turned on. As a result, the potentials at one ends of the analog memories 231 and 233 become the same, and the potentials at the respective ends of the analog memories 232 and 234 become the same, and the signal charges accumulated in the analog memories are averaged. . This operation ends when the averaging pulse ΦMIX changes from the “H” level to the “L” level.

[Operation during period T6]
In the period T6, signals based on the signal charges accumulated in the analog memories 231 and 232 of the two pixels 100B arranged in the same row are read out simultaneously. First, the selection transistors 291 and 292 are turned on when the selection pulses ΦSEL1 and ΦSEL2 change from the “L” level to the “H” level. As a result, a signal based on the potential Vmem shown in the equation (1) is output to the vertical signal line 120 via the selection transistors 291 and 292.

  Subsequently, when the reset pulses ΦRST2-1 and ΦRST2-2 change from the “L” level to the “H” level, the second reset transistors 221 and 222 are turned on. As a result, the analog memories 231 and 232 are reset, and a signal based on the potential at one end of the analog memories 231 and 232 at the time of reset is output to the vertical signal line 120 via the selection transistors 291 and 292.

  Subsequently, as the reset pulses ΦRST2-1 and ΦRST2-2 change from the “H” level to the “L” level, the second reset transistors 221 and 222 are turned off. Subsequently, when the selection pulses ΦSEL1 and ΦSEL2 change from the “H” level to the “L” level, the selection transistors 291 and 292 are turned off.

  The column processing circuit 350 obtains a difference signal obtained by taking a difference between a signal based on the potential Vmem shown in the expression (1) and a signal based on the potential of one end of the analog memories 231 and 232 when the analog memories 231 and 232 are reset. Is generated. This difference signal is a signal based on the difference between the potential Vmem and the power supply voltage VDD shown in the equation (1), and immediately after the signal charges accumulated in the photoelectric conversion elements 201 and 202 are transferred to the charge holding unit 230. This signal is based on the difference ΔVfd between the potential at one end of the charge holding unit 230 and the potential of the charge holding unit 230 immediately after the one end of the charge holding unit 230 is reset. Therefore, a signal component based on the signal charges accumulated in the photoelectric conversion elements 201 and 202 is obtained in which the noise component due to resetting the analog memories 231 and 232 and the noise component due to resetting the charge holding unit 230 are suppressed. be able to.

  The signal output from the column processing circuit 350 is output to the output amplifiers 410 and 420 via the output channels 430 and 440 by the horizontal scanning circuit 400. The output amplifiers 410 and 420 process the input signal and output it as an image signal. Thus, reading of signals from the two pixels 100B arranged in the same row among the four pixels 100B constituting one group is completed.

  With the above operation, the pixel signals corresponding to B are output from the pixels 100B in the first row among the pixels 100B corresponding to B arranged in the first column in FIG. 5B, and 2 in FIG. Among the pixels 100B corresponding to Gb arranged in the column, a pixel signal corresponding to Gb is output from the pixel 100B in the first row, and the pixel 100B corresponding to R arranged in the third column in FIG. 5B. Pixel signals corresponding to R are output from pixels 100B in the first row, and pixels 100B to Gr in the first row among pixels 100B corresponding to Gr arranged in the first column in FIG. 5B. The pixel signal to be output is output. Each pixel signal is a pixel signal obtained by averaging the four pixels 100B adjacent in the column direction. Accordingly, an averaged pixel signal is output from a part of the pixels 100B obtained by thinning out the pixels 100B in the column direction.

  In the above operation, averaging processing is performed on the four pixels 100B adjacent in the column direction, and signals are read from the pixels 100B at a rate of one row per four rows. Therefore, averaging processing is performed on both pixels 100B of two groups adjacent in the column direction on the second substrate 21, and signals are read from only two pixels 100B of one group of the two groups. For example, in FIG. 5B, the group G1 ′ and the group G3 ′ are adjacent to each other in the column direction, and after the averaging process is performed on the pixels 100B in these groups, the pixels 100B-1, A signal is read from 100B-2, but no signal is read from the other pixels 100B in the groups G1 ′ and G3 ′.

  Therefore, in the pixel 100B in the group G1 ′, the operation in the periods T5 and T6 in FIG. 8 is performed, but in the pixel 100B in the group G3 ′, the operation in the period T5 in FIG. 8 is performed and the operation in the period T6 is performed. Absent. The same applies to the groups G2 ′ and G4 ′. The pixel 100B in the group G2 ′ performs the operations in the periods T5 and T6 in FIG. 8, while the pixel 100B in the group G4 ′ performs the operation in the period T5 in FIG. It is performed and the operation in the period T6 is not performed.

  In the above operation, the signal holding unit 230 must hold the signal charge transferred from the photoelectric conversion elements 201, 202, 203, and 204 to the charge holding unit 230 until the readout timing of each pixel 100A. When noise is generated while the charge holding unit 230 holds the signal charge, the noise is superimposed on the signal charge held by the charge holding unit 230, and the signal quality (S / N) is deteriorated.

  The main causes of noise generated during the period in which the charge holding unit 230 holds the signal charge (hereinafter referred to as the holding period) are the charge due to the leakage current of the charge holding unit 230 (hereinafter referred to as the leakage charge). , Charge due to light incident on portions other than the photoelectric conversion elements 201, 202, 203, 204 (hereinafter referred to as photocharge). Assuming that the leak charge and photocharge generated in unit time are qid and qpn, respectively, and the length of the holding period is tc, the noise charge Qn generated during the holding period is (qid + qpn) tc.

  The capacity of the charge holding unit 230 is Cfd, the capacity of the analog memories 231, 232, 233, and 234 is Cmem, and the ratio of Cfd to Cmem (Cmem / Cfd) is A. As described above, the gain of the first amplification transistor 240 is α1, and the total gain of the analog memories 231, 232, 233, 234 and the second transfer transistors 271, 272, 273, 274 is α2. If the signal charges generated in the photoelectric conversion elements 201, 202, 203, and 204 during the exposure period are Qph, the signal charges held in the analog memories 231, 232, 233, and 234 after the end of the exposure period are A × α1 × α2. × Qph.

  Signals based on the signal charges transferred from the photoelectric conversion elements 201, 202, 203, 204 to the charge holding unit 230 are sampled and held by the second transfer transistors 271, 272, 273, 274, and analog memories 231, 232, 233, 234 are sampled and held. Stored in Therefore, the time from when the signal charge is transferred to the charge holding unit 230 until the signal charge is stored in the analog memories 231, 232, 233, and 234 is short, and noise generated in the charge holding unit 230 can be ignored. . S / N is A × α1 × α2 × Qph / Qn, assuming that the noise generated in the period in which the analog memories 231, 232, 233, and 234 hold signal charges is the same Qn as described above.

  On the other hand, the S / N in the case where the signal charge held in the capacitor storage unit is read from the pixel via the amplification transistor is Qph / Qn. Therefore, the S / N of this embodiment is A × α1 × α2 times the S / N of the prior art. The capacitance values of the analog memories 231, 232, 233, and 234 are set so that A × α1 × α2 is greater than 1 (for example, the capacitance values of the analog memories 231, 232, 233, and 234 are set to the capacitance of the charge holding unit 230. By making it sufficiently larger than the value, it is possible to reduce degradation of signal quality.

  In the present embodiment, regarding the group constituted by the pixels 100A, the operation timing of each group is the same regardless of the position in the vertical direction (hereinafter referred to as the vertical position). In addition, regarding the group constituted by the pixels 100B, the operation timing of each group having different vertical positions is a timing corresponding to each operation period. FIG. 9 schematically shows the operation timing of the group unit when the pixels 100A and 100B are arranged in n rows. The vertical position in FIG. 9 indicates the vertical position, that is, the row position in the arrangement of the pixels 100A and 100B, and the horizontal position indicates the time position. FIG. 9 corresponds to the case where the arrangement of the pixels 100A and 100B is a more general n rows × n columns.

  The reset period corresponds to the period T1 in FIG. 7, the signal transfer period corresponds to the periods T2, T3, and T4 in FIG. 7, the averaging process period corresponds to the period T5 in FIG. 7, and the readout period corresponds to the period in FIG. Corresponds to T6. Regarding the group constituted by the pixels 100A, the reset period and the signal transfer period of each group are the same regardless of the vertical position. On the other hand, regarding the group constituted by the pixels 100B, the signal transfer periods of the groups having different vertical positions are the same, but the averaging process period and the readout period are different. In the operation described above, the exposure timing is different for each pixel in the same group, but the synchronism of exposure can be realized in a plurality of groups as a whole.

  In the above description, the averaging process is performed on the four pixels 100B adjacent in the column direction. However, the number of pixels 100B to be subjected to the averaging process may not be four. For example, the averaging process may be performed on two pixels 100B adjacent in the column direction, or the averaging process may be performed on eight pixels 100B adjacent in the column direction.

  As described above, according to the present embodiment, each signal (signal charge) accumulated in the signal accumulation circuit (analog memory) included in each of the plurality of pixels 100B is averaged and output from the pixel. It is possible to suppress the occurrence of moire in the image formed by each signal. Further, by performing the averaging, it is possible to reduce the random noise component included in the signal. Therefore, according to the present embodiment, it is possible to reduce deterioration in image quality.

  In the present embodiment, four pixels 100B corresponding to the same color are adjacent in the vertical direction (column direction), and the signal charges accumulated in the analog memory of these four pixels 100B are averaged. Thus, by averaging the signal charges of the pixels 100B adjacent in the vertical direction, the layout of the averaging transistors 275 and 276 can be simplified. Further, even if crosstalk occurs between two pixels 100B adjacent to each other in the vertical direction and corresponding to the same color, the crosstalk occurs compared to the case where crosstalk occurs between two pixels 100B corresponding to different colors. Degradation of image quality due to talk can be reduced.

  In the present embodiment, an averaged signal is output from only one pixel 100B among the four pixels 100B arranged in the vertical direction. As a result, the number of rows in the vertical direction from which signals are read out is one-fourth of the number of rows in the pixel array, so that signals can be read out faster than in the case of reading out signals from all rows. And power consumption can be reduced. In addition, since signals are read from the pixels 100B in the same row in a plurality of groups having the same vertical position on the second substrate 21, it is possible to perform control for reading out the averaged signal for each row. The control relating to the reading of the data becomes easy.

  In addition, since some circuit elements are shared among a plurality of pixels, the chip area can be reduced as compared with the case where the circuit elements are not shared between the plurality of pixels. Furthermore, since the first amplification transistor 240 and the current source 280 are shared among a plurality of pixels, the number of current sources that operate simultaneously can be suppressed. For this reason, it is possible to reduce the occurrence of a power supply voltage drop or a GND (ground) voltage increase due to simultaneous operation of a large number of current sources.

  In addition, since the area of the photoelectric conversion element of the first substrate 20 can be increased as compared with the case where all the circuit elements of the pixel are arranged on one substrate, the sensitivity is improved. Further, by using an analog memory, the area of the signal storage region provided on the second substrate 21 can be reduced.

  Further, by providing the analog memories 231, 232, 233, and 234, it is possible to reduce deterioration of signal quality. In particular, the signal charge held in the analog memory by making the capacitance value of the analog memory larger than the capacitance value of the charge holding portion (for example, making the capacitance value of the analog memory more than five times the capacitance value of the charge holding portion). However, it becomes larger than the signal charge held by the charge holding unit. For this reason, it is possible to reduce the influence of signal deterioration due to the leak current of the analog memory.

  Further, by providing the clamp capacitor 260 and the second transfer transistors 271, 272, 273, 274, the influence of noise generated in the first substrate 20 can be reduced. Noise generated in the first substrate 20 includes noise (for example, reset) generated at the input portion of the first amplification transistor 240 resulting from the operation of a circuit (for example, the first reset transistor 220) connected to the first amplification transistor 240. Noise), noise derived from the operating characteristics of the first amplification transistor 240 (for example, noise due to variations in circuit threshold of the first amplification transistor 240), and the like.

  In addition, the signal when the analog memories 231, 232, 233, and 234 are reset and the first amplification transistor 240 generated by transferring the signal charge from the photoelectric conversion elements 201, 202, 203, and 204 to the charge holding unit 230 are displayed. By outputting a signal corresponding to the output fluctuation from the pixel 100B in a time-sharing manner and performing differential processing of each signal outside the pixel 100B, the influence of noise generated in the second substrate 21 can be reduced. The noise generated in the second substrate 21 is derived from the operation of a circuit (for example, the second reset transistors 221, 222, 223, 224) connected to the second amplification transistors 241, 242, 243, 244. There is noise (for example, reset noise) generated at the input portion of the transistors 241, 242, 243, and 244.

  The first pixel according to the present invention corresponds to, for example, the pixel 100A. The second pixel according to the present invention corresponds to, for example, the pixel 100B. The signal storage circuit according to the present invention corresponds to the analog memories 231, 232, 233, and 234, for example. The averaging circuit according to the present invention corresponds to the averaging transistors 275 and 276, for example. The output circuit according to the present invention corresponds to the selection transistors 291, 292, 293, 294, for example.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the above-described embodiments, and includes design changes and the like without departing from the gist of the present invention. . In the above description, the configuration of the solid-state imaging device in which two substrates are connected by the connection unit is shown, but three or more substrates may be connected by the connection unit. In the case of a solid-state imaging device in which three or more substrates are connected at the connection portion, two of the three or more substrates correspond to the first substrate and the second substrate.

  DESCRIPTION OF SYMBOLS 1 ... Lens part, 2 ... Lens control apparatus, 3 ... Solid-state imaging device, 4 ... Drive circuit, 5 ... Memory, 6 ... Signal processing circuit, 7 ... Recording apparatus , 8 ... Control device, 9 ... Display device, 100A, 100B ... Pixel, 130, 280 ... Current source, 200A, 200B ... Pixel unit, 201, 202, 203, 204 ... Photoelectric conversion elements 211, 212, 213, 214 ... first transfer transistor, 220 ... first reset transistor, 221,222,223,224 ... second reset transistor, 230 ... charge retention , 231, 232, 233, 234... Analog memory, 240, first amplification transistor, 241, 242, 243, 244, second amplification transistor, 250, connection portion 251 253 micropad, 252... Microbump, 260... Clamp capacitance, 271, 272, 273, 274... Second transfer transistor, 275, 276... Averaging transistor, 291, 292, 293, 294 ... Selection transistors, 300A, 300B ... Vertical scanning circuit, 350 ... Column processing circuit, 400 ... Horizontal scanning circuit, 410 ... Output amplifier, 430 ... Output channel

Claims (6)

A solid-state imaging device in which a first substrate and a second substrate are electrically connected,
The first substrate includes a plurality of first pixels arranged in a matrix,
The second substrate includes a plurality of second pixels arranged in a matrix,
Each of the plurality of first pixels includes a photoelectric conversion element that generates a color signal corresponding to any one of the first to nth (n is an integer of 2 or more) colors,
Each of the plurality of second pixels is
A signal storage circuit for storing the color signal generated by the photoelectric conversion element;
The solid-state imaging device
An averaging circuit that averages each color signal accumulated in the signal accumulation circuit of two or more second pixels arranged in the same column;
An output circuit for outputting the averaged color signal to the outside of the second pixel;
Have
The first pixel having the photoelectric conversion element that generates a color signal corresponding to the m-th color (m is an integer from 1 to n) is the first pixel corresponding to the m-th color. There,
The second pixel having the signal storage circuit for storing a color signal corresponding to an mth color (m is any one of 1 to n) is the second pixel corresponding to the mth color. ,
2. The solid-state imaging device according to claim 2, wherein two or more second pixels corresponding to the same color are arranged in the same column on the second substrate.   The averaging circuit averages the color signals accumulated in the signal accumulation circuits of two or more second pixels corresponding to the same color arranged in the same column. Item 2. The solid-state imaging device according to Item 1. The first pixels are classified into a plurality of first groups, and the one first group includes a plurality of the first pixels,
The second pixels are classified into a plurality of second groups associated with each of the plurality of first groups, and one second group includes a plurality of the second pixels,
In one of the first groups, two or more first pixels corresponding to a predetermined color among the first to nth colors are arranged in different columns,
In the second group, two or more second pixels corresponding to the predetermined color are arranged in the same column,
The averaging circuit averages the color signals accumulated in the signal accumulation circuit of two or more second pixels corresponding to the predetermined color arranged in the same column. The solid-state imaging device according to claim 2.   4. The solid-state imaging device according to claim 3, wherein two or more second pixels corresponding to the predetermined color are arranged adjacent to the same column.   4. The averaging circuit according to claim 3, wherein after the color signals are accumulated in the signal accumulation circuit, the accumulated color signals are averaged at different timings for each of the second groups. Solid-state imaging device.   The solid-state imaging device according to claim 2, wherein the output circuit outputs an averaged color signal from a part of the second pixels obtained by thinning the second pixels in the column direction.

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