JP5946136B2 - Heterojunction bipolar transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a heterojunction bipolar transistor including a base layer made of germanium and a method for manufacturing the same.

  Heterojunction bipolar transistors (HBTs) are being applied to high-speed electronic circuits because of their high speed. In the HBT, the base layer is made of a material having a band gap smaller than that of the emitter layer, so that the injection of holes from the base to the emitter is suppressed by the potential barrier generated at the valence band edge. For this reason, the HBT has a characteristic that a high current gain can be obtained even if the impurity concentration of the base layer is increased. By increasing the impurity concentration of the base layer, the base resistance can be lowered, thereby achieving high speed operation and low noise operation.

  Further, the same material as that of the base layer is usually used for the collector layer of the HBT as described above. However, when a high breakdown voltage is required, a material having a wide band gap is also used for the collector layer. In this way, a configuration in which a material having a wider band gap than the base layer is used for the collector layer is called a double-heterojunction bipolar transistor (DHBT).

  Normally, when the collector layer is composed of only a material having a wider band gap than the base layer, a potential barrier 411 is generated due to the conduction band edge discontinuity 411 at the junction between the collector 403 and the base 404, as shown in FIG. The injection of electrons from the base 404 to the collector 403 is hindered. In FIG. 4, reference numeral 405 denotes an emitter.

  In order to prevent the above-described problem, as shown in FIG. 5, the base 504 is made of a material whose energy level at the conduction band edge is larger than that of the collector 503, and a so-called Type-II junction is formed between the collector 503 and the base 504. There is also the technology. In FIG. 5, reference numeral 505 denotes an emitter.

  An InP-based HBT using a material system lattice-matched with InP is expected to be applied to an ultra-high-speed circuit due to good electrical characteristics of the material. In an InP-based HBT, InGaAs is usually used for the base layer, which is lattice-matched with InP and has a narrower band gap than InP. Further, GaAsSb lattice-matched with InP is used as a base layer of DHBT because it forms a Type-II junction with InP (see Patent Document 1). Therefore, by forming the base layer from GaAsSb, the potential barrier problem due to the conduction band edge discontinuity in the collector-base junction described above can be solved.

JP 2012-227245 A

E. Higurashi et al., "Room temperature GaN-GaAs direct bonding by argon-beam surface activation", Proceedings of SPIE, Vol. 6717, 67170L, 2007.

  However, since InGaAs and GaAsSb all have a low hole mobility, there is a limit in reducing the base resistance even if the impurity concentration is increased in a base layer made of these materials. For this reason, for example, the above-described potential barrier problem can be solved by configuring the base layer from GaAsSb, but there is a problem that it is not easy to further increase the speed.

  The present invention has been made to solve the above-described problems. In a heterojunction bipolar transistor, the problem of a potential barrier at a collector-base junction is solved, and further speeding-up can be achieved. The purpose is to do.

  A heterojunction bipolar transistor according to the present invention includes a substrate made of InP, a collector layer made of InP formed on the substrate, a base layer made of Ge formed in contact with the collector layer, and made of a base layer. And an emitter layer made of InP.

  The method of manufacturing a heterojunction bipolar transistor according to the present invention includes a first step of forming a first semiconductor layer made of InP serving as a collector layer on a substrate made of InP, and a second step made of Ge serving as a base layer. A second step of bonding the semiconductor layer on the first semiconductor layer by a surface activated bonding method, and a third semiconductor layer made of InP to be an emitter layer on the second semiconductor layer by a surface activated bonding method. And a third step of pasting together.

  As described above, according to the present invention, since the base layer is made of germanium (Ge), in the heterojunction bipolar transistor, the problem of the potential barrier at the collector-base junction is solved, and further speedup is achieved. An excellent effect of being able to be obtained is obtained.

FIG. 1 is a configuration diagram showing a configuration of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 2 is a band diagram showing the state of the band gap energy of the collector layer 103, base layer 104, and emitter layer 105 in the heterojunction bipolar transistor according to the embodiment of the present invention. FIG. 3A is a cross-sectional view schematically showing a state in the middle of manufacturing for explaining the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 3B is a cross-sectional view schematically showing a state in the middle of manufacturing for explaining the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 3C is a cross-sectional view schematically showing a state in the middle of manufacturing for explaining the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 3D is a cross-sectional view schematically showing a state in the middle of manufacturing for explaining the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 3E is a cross-sectional view schematically showing a state in the middle of manufacturing for explaining the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 4 is a band diagram showing the state of the band gap energy of the collector layer 403, base layer 404, and emitter layer 405 when the collector layer is made of a material having a wider band gap than the base layer. FIG. 5 is a band diagram showing the state of the band gap energy in the collector layer 503, the base layer 504, and the emitter layer 505 when the base 504 is made of a material whose energy level at the conduction band edge is larger than that of the collector 503. is there.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing a configuration of a heterojunction bipolar transistor (HBT) in an embodiment of the present invention. FIG. 1 schematically shows a cross section.

  In this heterojunction bipolar transistor, first, a subcollector layer 102 is formed on a substrate 101 made of InP, and a collector layer 103 made of InP is formed on the subcollector layer 102. On the collector layer 103, a base layer 104 made of germanium (Ge) is formed in contact. Further, an emitter layer 105 made of InP is formed on and in contact with the base layer 104. An emitter cap layer 106 is formed on the emitter layer 105.

  Here, for example, the collector layer 103 and the base layer 104 are first mesas, and the emitter layer 105 and the emitter cap layer 106 are second mesas. The second mesa has a smaller area in plan view than the first mesa. In such a mesa shape, the collector electrode 111 is connected on the sub-collector layer 102 on the side of the second mesa. A base electrode 112 is connected on the base layer 104 on the side of the first mesa. An emitter electrode 113 is connected on the emitter cap layer 106.

  For example, the substrate 101 may be made of InP, which has a high resistance by doping iron. The subcollector layer 102 may be made of InP and InGaAs into which n-type impurities are introduced at a high concentration. The collector layer 103 may be made of InP into which an n-type impurity is introduced. The base layer 104 may be made of Ge into which p-type impurities are introduced. The emitter layer 105 may be made of InP into which an n-type impurity is introduced. The emitter cap layer 106 may be made of InGaAs into which n-type impurities are introduced at a high concentration.

  According to the heterojunction bipolar transistor of the embodiment configured as described above, as shown in the band diagram of FIG. 2, the heterojunction between the base layer 104 made of Ge and the collector layer 103 made of InP is Type-II. Become. Therefore, a potential barrier is not formed at the junction between the base layer 104 and the collector layer 103. As a result, according to the heterobipolar transistor in the embodiment, there is no problem in current injection into the collector layer 103.

  Further, according to the embodiment, since the base layer 104 is made of Ge having a higher hole mobility than InGaAs and GaAsSb, the base resistance can be reduced, the speed of the heterojunction bipolar transistor can be further increased, and Noise can be achieved.

  Next, a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention will be described with reference to FIGS. 3A to 3E. 3A to 3E are cross-sectional views schematically showing a state in the middle of manufacturing for explaining the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention.

  First, as shown in FIG. 3A, for example, a sub-collector layer made of InP and InGaAs in which n-type impurities are introduced at a high concentration on a substrate 101 made of InP that has been made high resistance by doping iron. 102, and an n-InP layer 203 made of InP into which an n-type impurity is introduced. These may be formed by epitaxial growth on the substrate 101 by deposition methods such as well-known metal organic chemical vapor deposition (MOVPE) and molecular beam epitaxy (MBE). The n-InP layer 203 becomes the collector layer 103.

Next, as shown in FIG. 3B, surface activation is performed on the p-Ge layer 204 made of Ge into which a p-type impurity is introduced via the sacrificial layer 302 on the other substrate 301 made of Ge or GaAs. The n-InP layer 203 is bonded by a bonding method. Ge and InP have different lattice constants, but can be bonded at room temperature (20 to 25 ° C.) according to the surface activated bonding method (see Non-Patent Document 1). Here, the sacrificial layer 302 may be made of, for example, AlAs. The sacrificial layer 302 and the p-Ge layer 204 can be formed by epitaxial growth on the other substrate 311 by a deposition method such as a metal organic chemical vapor deposition method or a molecular beam epitaxial growth method. In the growth of the p-Ge layer 204, GeH ₄ may be used as a source gas.

  Next, the sacrificial layer 302 is selectively removed by wet etching with a hydrofluoric acid-based etchant to remove the other substrate 301. As shown in FIG. 3C, the subcollector layers 102, n are formed on the substrate 101. The InP layer 203 and the p-Ge layer 204 are stacked. Since the sacrificial layer 302 is made of AlAs, the sacrificial layer 302 is selectively removed by wet etching using a hydrofluoric acid-based etchant without etching the p-Ge layer 204, other layers, or the substrate. Can do.

Next, as shown in FIG. 3D, an n ⁺ -InGaAs layer 206 made of InGaAs and an n-type impurity doped with n-type impurities at a high concentration via a sacrificial layer 312 on another substrate 311 made of InP. An n-InP layer 205 made of InP into which impurities are introduced is formed, and the n-InP layer 205 is bonded to the p-Ge layer 204 by a surface activated bonding method. The sacrificial layer 312 may be made of AlAs, for example. The sacrificial layer 312, the n ⁺ -InGaAs layer 206, and the n-InP layer 205 can be formed by epitaxial growth on the other substrate 311 by a deposition method such as a metal organic chemical vapor deposition method or a molecular beam epitaxial growth method. .

Next, the sacrificial layer 312 is selectively removed by wet etching with a hydrofluoric acid-based etchant to remove the other substrate 311. As shown in FIG. 3E, the subcollector layers 102, n are formed on the substrate 101. The InP layer 203, the p-Ge layer 204, the n-InP layer 205, and the n ⁺ -InGaAs layer 206 are stacked. Since the sacrificial layer 312 is made of AlAs, the sacrificial layer 312 is selectively removed by wet etching with a hydrofluoric acid-based etchant without etching the n ⁺ -InGaAs layer 206, other layers, and the substrate. be able to.

As described above, after forming each semiconductor layer (first semiconductor layer, second semiconductor layer, and third semiconductor layer), as shown below, a collector layer, a base layer, and an emitter layer are formed to form a heterojunction bipolar. A transistor is used. First, the emitter electrode 113 is formed on the n ⁺ -InGaAs layer 206. For example, the emitter electrode 113 may be formed by patterning a film of an electrode metal material deposited by a vacuum deposition method or a sputtering method by a well-known lift-off method or etching.

Next, by patterning the n-InP layer 205 and the n ⁺ -InGaAs layer 206, the emitter layer 105 and the emitter cap layer 106 are formed and used as the second mesa.

  Next, the base electrode 112 is formed on the side of the second mesa of the p-Ge layer 204 exposed by forming the second mesa. For example, the base electrode 112 may be formed by patterning a film of an electrode metal material deposited by a vacuum evaporation method or a sputtering method by a well-known lift-off method or etching.

  Next, the n-InP layer 203 and the p-Ge layer 204 are patterned to form the collector layer 103 and the base layer 104, which are used as the first mesa. Next, a collector electrode 111 is formed on the side of the first mesa of the subcollector layer 102 exposed by forming the first mesa. For example, the collector electrode 111 may be formed by patterning a film of an electrode metal material deposited by a vacuum deposition method or a sputtering method by a well-known lift-off method or etching.

  As described above, according to the present invention, since the base layer is made of Ge, the problem of the potential barrier at the collector-base junction can be solved and the speed can be further increased in the heterojunction bipolar transistor. become.

  The present invention is not limited to the embodiment described above, and many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious.

  DESCRIPTION OF SYMBOLS 101 ... Subcollector layer, 102 ... Subcollector layer, 103 ... Collector layer, 104 ... Base layer, 105 ... Emitter layer, 106 ... Emitter cap layer, 111 ... Collector electrode, 112 ... Base electrode, 113 ... Emitter electrode

Claims (2)

A substrate made of InP;
A collector layer made of InP formed on the substrate;
A base layer made of Ge formed on and in contact with the collector layer;
A heterojunction bipolar transistor comprising: an emitter layer made of InP formed in contact with the base layer. Forming a first semiconductor layer made of InP serving as a collector layer on a substrate made of InP;
A second step of bonding a second semiconductor layer made of Ge serving as a base layer on the first semiconductor layer by a surface activated bonding method;
And a third step of bonding a third semiconductor layer made of InP to be an emitter layer on the second semiconductor layer by a surface activated bonding method.

Images