JP5953705B2 - SOI wafer and method for manufacturing SOI wafer - Google Patents

Description

  The present invention relates to an SOI (Silicon On Insulator) wafer used for forming a semiconductor element, and more particularly to a characteristic structure of an SOI wafer and a method for manufacturing the SOI wafer.

  As one of semiconductor device wafers, there is an SOI wafer in which a silicon layer is formed on a silicon oxide film which is an insulating layer. This SOI wafer has features such as a small parasitic capacitance and high radiation resistance, since the silicon layer on the surface layer of the substrate, which is a device manufacturing region, is electrically separated from the inside of the substrate by a silicon oxide film. Therefore, SOI wafers are advantageous in terms of high-speed switching operation, low power consumption operation, soft error prevention, and the like, compared with conventional bulk silicon wafers, and are widely used as substrates for forming high-performance semiconductor elements. .

  The SOI wafer has, for example, the structure shown in FIG. 14, and a support substrate semiconductor wafer 110 made of a support substrate semiconductor 111 having a silicon oxide film 112 formed on the surface, and an upper surface of the support substrate semiconductor wafer 110. And an active layer 120 formed. As one method for manufacturing the SOI wafer 101, a conventional bonding method can be given. In the manufacturing method of the SOI wafer 101 using the conventional bonding method, the process A to the process C shown in FIG. 15 are generally performed. See, for example, US Pat.

A support substrate semiconductor 111 made of single crystal silicon (Si) and an active layer substrate semiconductor 121 also made of single crystal silicon are prepared.
Step A: The supporting substrate semiconductor 111 is subjected to a thermal oxidation process to form an insulating silicon oxide film 112 on the entire surface of the supporting substrate semiconductor 111.
Step B: The support substrate semiconductor 111 on which the silicon oxide film 112 is formed and the active layer substrate semiconductor 121 are brought into close contact with each other, and heat treatment (for example, about 1000 ° C. for about 2 hours) is performed to support the substrate semiconductor 111 and the active layer. The substrate semiconductor 121 is bonded together.
Step C: An active layer (SOI layer) having a desired thickness and shape by polishing the surface (dotted line in Step B) and the end surface of the active layer substrate semiconductor 121 on which the support substrate semiconductor 111 is not bonded. ) 120 is formed.
Thereby, the conventional SOI wafer 101 shown in FIG. 14 is completed.

JP 2004-235251 A

  As is well known, in the semiconductor wafer manufacturing process, there is a step of injecting charges into the support substrate semiconductor wafer 110 such as ion implantation, that is, into the support substrate semiconductor 111. Here, as described above, the silicon oxide film 112 is formed so as to cover the entire surface of the support substrate semiconductor 111. In general, since ions implanted in the ion implantation step are positively charged (+), the support substrate semiconductor 111 covered with the silicon oxide film 112 is positively charged (FIG. 16 (FIG. 16). a)).

  Alternatively, in the jet scrub process of the cleaning process, the surface of the conventional SOI wafer 101 is polarized due to friction between the conventional SOI wafer 101 and water, and the inside of the semiconductor wafer 110 for the support substrate, that is, the support substrate semiconductor 111 is charged. It is also possible that

  Here, the positive charge injected into the support substrate semiconductor wafer 110 and charged in the support substrate semiconductor 111 is discharged into the atmosphere (floating in the atmosphere) if the silicon oxide film 112 is thin (less than 1 μm). It is countered by the negative charge of negative ions). However, as the silicon oxide film 112 becomes thicker (1 μm or more), the positive charges charged in the support substrate semiconductor 111 are less likely to be discharged into the atmosphere.

  When semiconductor manufacturing is continued with the positive charge accumulated inside the support substrate semiconductor wafer 110, the support substrate semiconductor wafer 110 (support) is placed when the semiconductor substrate 110 is placed on the transfer stage 50 used in the wafer manufacturing facility. Due to the positive charges collected on the outermost layer portion of the substrate semiconductor 111), negative charges are attracted to the surface of the transfer stage 50, and the transfer stage 50 is charged to minus (-) (FIG. 16B).

  Therefore, the boundary where the SOI wafer 101 and the transfer stage 50 are in contact (the part indicated by the arrow Y in FIG. 16B) is the uppermost layer portion of the support substrate semiconductor wafer 110 (support substrate semiconductor 111) where positive charges are collected. Between the negatively charged surface of the transfer stage 50, the two charged charges across the boundary have positive and negative polarities. Therefore, when the SOI wafer 101 is separated from the transfer stage 50, the electrostatic adsorption phenomenon occurs because the two charged charges across the boundary have different polarities.

As a result, for example, there is a problem that a conveyance failure or the like due to sticking between the SOI wafer 101 and the conveyance stage 50 used in the wafer manufacturing facility due to the electrostatic adsorption phenomenon occurs.
In addition, the lifetime of the silicon oxide film 112 may be shortened, or threshold voltage fluctuations and breakdown voltage may be reduced due to charging on the active layer 120 side.

  Therefore, an object of the present invention is to eliminate the occurrence of electrostatic adsorption phenomenon between an SOI wafer and a transfer stage used in a wafer manufacturing facility by using a simple method, and to prevent the wafer from being caused by the electrostatic adsorption phenomenon. An object of the present invention is to provide an SOI wafer and a method for manufacturing the SOI wafer that can prevent the occurrence of a conveyance failure or the like.

The present invention is directed to an SOI wafer in which an active layer semiconductor layer is formed on a first main surface of a support substrate semiconductor wafer having an oxide film formed on the surface thereof. And in order to achieve the said objective, the SOI wafer of this invention has the semiconductor exposure part which the support substrate semiconductor inside a wafer exposes to the side surface of the semiconductor wafer for support substrates.
With such a configuration, it is possible to prevent electric charges from being accumulated inside the semiconductor wafer for supporting substrate even if a positive ion implantation process or the like is performed.

Preferably, the semiconductor exposed portion is formed in a region on the second main surface side facing the first main surface where the active layer semiconductor layer is formed from the outer peripheral end of the support substrate semiconductor wafer.
If formed in this way, an SOI wafer having a semiconductor exposed portion can be manufactured without changing the outer diameter size even if the conventional wafer is used as it is.

Further, the semiconductor exposed portion may be formed by cutting or polishing the outer peripheral portion of the support substrate semiconductor wafer substantially vertically.
If formed in this way, it is possible to avoid the occurrence of the knife edge problem in which the outer peripheral edge of the semiconductor wafer for supporting substrate becomes an acute angle in the final stage of the semiconductor wafer manufacturing process.

  Further, the semiconductor exposed portion may be formed by polishing an oxide film formed on the outer peripheral portion of the support substrate semiconductor wafer along the shape of the outer peripheral portion.

It is desirable that a high concentration impurity layer be formed in the exposed semiconductor portion.
If a high-concentration impurity layer is formed, the resistance value of the exposed portion of the semiconductor becomes low, so that positive ions implanted into the semiconductor wafer for supporting substrate can be expected to be quickly released into the atmosphere.

  The semiconductor exposed portion described above is formed in a single process by bringing one polishing pad into contact with the surface of the semiconductor layer for the active layer and the side surface of the semiconductor wafer for the supporting substrate, and simultaneously polishing the surface and the side surface. can do. The polishing pad is preferably made of a deformable material, and the polishing pad is deformed so that the polishing pad is brought into contact with both the surface of the semiconductor layer for the active layer and the side surface of the semiconductor wafer for the support substrate. Polishing of the surface of the active layer semiconductor layer and formation of the exposed semiconductor portion can be easily realized.

According to the present invention, since the semiconductor exposed portion where the support substrate semiconductor is exposed is formed on the support substrate semiconductor wafer, the inside of the support substrate semiconductor wafer is not charged and is used in the wafer manufacturing facility. No electrostatic adsorption phenomenon occurs with the transfer stage.
Therefore, in the SOI wafer manufacturing process, it is possible to prevent the occurrence of defective wafer conveyance caused by the electrostatic adsorption phenomenon.

Sectional drawing explaining the structural example of the SOI wafer 1 which concerns on one Embodiment of this invention. The figure for demonstrating the principle which can prevent an electrostatic adsorption phenomenon with the structure of the SOI wafer 1 which concerns on one Embodiment of this invention. The figure explaining the manufacturing method example 1 of the SOI wafer 1 which concerns on one Embodiment of this invention. The figure explaining the manufacturing method example 2 of the SOI wafer 1 which concerns on one Embodiment of this invention. The figure explaining the manufacturing method example 3 of the SOI wafer 1 which concerns on one Embodiment of this invention. The figure explaining the manufacturing method example 4 of the SOI wafer 1 which concerns on one Embodiment of this invention. The figure explaining the manufacturing method example 5 of the SOI wafer 1 which concerns on one Embodiment of this invention. The figure explaining the manufacturing method example 6 of the SOI wafer 1 which concerns on one Embodiment of this invention. The figure explaining the manufacturing method example 7 of the SOI wafer 1 which concerns on one Embodiment of this invention. The figure explaining the manufacturing method example 8 of the SOI wafer 1 which concerns on one Embodiment of this invention. The figure explaining the case where the manufacturing method example 7 and the manufacturing method example 8 of the SOI wafer 1 which concern on one Embodiment of this invention are applied to the manufacturing method example 3-the manufacturing method example 6. FIG. The figure explaining the grinding | polishing method using the interlayer film CMP process in manufacture of the conventional SOI wafer 101 The figure explaining the grinding | polishing method using the interlayer film CMP process in manufacture of the SOI wafer 1 of this invention Diagram explaining the knife edge problem Sectional drawing explaining the structure of the conventional SOI wafer 101 The figure explaining the example of the manufacturing method of the conventional SOI wafer 101 The figure for demonstrating the electrostatic adsorption phenomenon generate | occur | produced with the structure of the conventional SOI wafer 101

  Hereinafter, with respect to an SOI wafer used for forming a semiconductor element provided by the present invention, the structure of the SOI wafer, the principle by which the problem is solved, and a method for manufacturing the SOI wafer will be described in order with reference to the drawings.

1. Structure of SOI Wafer FIG. 1 is a cross-sectional view illustrating a structure example of an SOI wafer 1 according to an embodiment of the present invention. The SOI wafer 1 of this embodiment shown in FIG. 1 includes a support substrate semiconductor wafer 10, a buried oxide film 12 a, and an active layer 20. Further, a semiconductor exposed portion 13 is formed on the semiconductor wafer 10 for support substrate.

  In this SOI wafer 1, a silicon oxide film 12 (consisting of 12a and 12b) having an insulating property is formed on the entire surface of a support substrate semiconductor 11 made of single crystal silicon (Si) by thermal oxidation. Based on what you have. An active layer 20 made of single crystal silicon is formed on the first main surface (the upper surface in FIG. 1) of the support substrate semiconductor 11 on which the silicon oxide film 12 is formed. Of the silicon oxide film 12, a portion of the silicon oxide film sandwiched between the active layer 20 and the support substrate semiconductor 11 is particularly referred to as a buried oxide film (also referred to as a BOX layer or a BOX oxide film) 12a. The support substrate semiconductor wafer 10 is constituted by the silicon oxide film 12 b excluding the buried oxide film 12 a in the silicon oxide film 12 and the support substrate semiconductor 11.

Further, the semiconductor wafer 10 for support substrate is provided with a semiconductor exposed portion 13 in which the silicon oxide film 12b is removed and the support substrate semiconductor 11 is exposed and directly exposed to the atmosphere. In the example shown in FIG. 1, a predetermined position on the second main surface (the lower surface in FIG. 1) facing the first main surface on which the active layer 20 of the semiconductor wafer 10 for support substrate is formed (details are given) The semiconductor exposed portion 13 is formed in a later-described manner.
The semiconductor exposed portion 13 formed on the support substrate semiconductor wafer 10 is not limited to the position and shape shown in FIG. 1, and may be formed at the position and shape shown in the manufacturing method example described later. .

  As will be described later, the semiconductor exposed portion 13 is used for charging a transfer arm, a transfer stage, a chamber stage, etc. (hereinafter collectively referred to as a transfer stage) used in the wafer manufacturing facility in the manufacturing process of the SOI wafer 1. It is formed on the support substrate semiconductor wafer 10 in order to eliminate the occurrence of an electrostatic adsorption phenomenon between the possible conductive member and the second main surface of the support substrate semiconductor wafer 10.

2. Principle for Solving Problems FIG. 2 is a diagram for explaining the principle by which the structure of the SOI wafer 1 according to one embodiment of the present invention can prevent the occurrence of the electrostatic adsorption phenomenon, which is a conventional problem to be solved. .

  When a positive ion implantation process is performed on the SOI wafer 1 of the present invention, the inside of the support substrate semiconductor wafer 10, that is, the support substrate semiconductor 11 is positively charged (+) (FIG. 2A). )).

As described in the background art, if the thickness of the silicon oxide film 12 formed on the surface of the support substrate semiconductor 11 is as thin as less than 1 μm, the positive charge charged in the support substrate semiconductor 11 passes through the silicon oxide film 12. Are discharged into the atmosphere (ie, counteracted by the negative charge of negative ions floating in the atmosphere).
However, when the thickness of the silicon oxide film 12 formed on the support substrate semiconductor 11 becomes 1 μm or more, most of the positive charges charged on the support substrate semiconductor 11 are accumulated in the support substrate semiconductor 11 without being discharged into the atmosphere. It will be. Therefore, the support substrate semiconductor wafer 10 is positively charged.

  However, in the structure of the SOI wafer 1 which is a characteristic of the present invention, the silicon oxide film 12b is removed on the second main surface side of the support substrate semiconductor wafer 10 so that the support substrate semiconductor 11 is exposed and directly exposed to the atmosphere. A semiconductor exposed portion 13 is formed. As a result, the positive charges injected into the support substrate semiconductor wafer 10 by the positive ion implantation process are immediately discharged into the atmosphere from the semiconductor exposed portion 13 without accumulating in the support substrate semiconductor 11 (FIG. 2). (B)). Accordingly, the support substrate semiconductor 11 is not positively charged after the positive ion implantation process.

For this reason, in the structure of the SOI wafer 1 of the present invention, a minus (−) is not charged on the surface portion of the transfer stage 50 (the dotted line region in FIG. 2C) with which the SOI wafer 1 contacts. Accordingly, when the SOI wafer 1 is pulled away from the transfer stage 50, the electrostatic adsorption phenomenon does not occur because the SOI wafer 1 is not charged.
Therefore, in the SOI wafer manufacturing process, it is possible to prevent the occurrence of defective wafer conveyance caused by the electrostatic adsorption phenomenon.

3. Manufacturing Method of SOI Wafer As a manufacturing method for realizing the SOI wafer 1 of the present invention having the above-described structure, for example, the following manufacturing method can be considered.
3-11 is a figure explaining the manufacturing method example 1-the manufacturing method example 8 of the SOI wafer 1 which concerns on one Embodiment of this invention.

<Production Method Example 1>
FIG. 3 is a diagram for explaining a manufacturing method example 1 of the SOI wafer 1 according to the embodiment of the present invention. In this manufacturing method example 1, the following process A to process D are performed.
First, a support substrate semiconductor 11 and an active layer substrate semiconductor 21 made of single crystal silicon are prepared. This support substrate semiconductor 11 has an outer peripheral size Sd (hereinafter referred to as a desired outer peripheral size Sd) of the SOI wafer 1 that is finally required when the silicon oxide film 12 is formed on the surface in the next step A. Prepare an outer peripheral size S of the same size. That is, assuming that the silicon oxide film 12 having a thickness T is formed, the outer peripheral size S of the prepared support substrate semiconductor 11 satisfies S = Sd−2T.

Step A: The supporting substrate semiconductor 11 is subjected to a thermal oxidation process to form an insulating silicon oxide film 12 on the entire surface of the supporting substrate semiconductor 11.
Step B: The support substrate semiconductor 11 on which the silicon oxide film 12 is formed and the active layer substrate semiconductor 21 are brought into close contact, and heat treatment is performed to bond the support substrate semiconductor 11 and the active layer substrate semiconductor 21 together.
Step C: An active layer (SOI layer) having a desired thickness and shape by polishing the surface (dotted line in Step B) and the end surface of the active layer substrate semiconductor 21 on the side where the support substrate semiconductor 11 is not bonded. ) 20 is formed. Thereby, the SOI wafer 1 including the active layer 20, the buried oxide film 12a, and the support substrate semiconductor wafer 10 is formed.
Step D: A portion of the support substrate semiconductor wafer 10 where the active layer 20 is not formed (second main surface) is polished to form a semiconductor exposed portion 13 where the support substrate semiconductor 11 is exposed. At this time, in order not to change the outer diameter of the SOI wafer 1, it is desirable to form the semiconductor exposed portion 13 in the region X in the range from the outer peripheral end of the support substrate semiconductor wafer 10 to the second main surface. .

<Production Method Example 2>
FIG. 4 is a diagram for explaining a manufacturing method example 2 of the SOI wafer 1 according to the embodiment of the present invention. In this manufacturing method example 2, the following process A to process D are performed.
First, a support substrate semiconductor 11 made of single crystal silicon is prepared. The support substrate semiconductor 11 is prepared so that when the silicon oxide film 12 is formed on the surface in the next step A, the outer peripheral size S is the same as the desired outer peripheral size Sd. That is, similarly to the manufacturing method example 1 described above, the outer peripheral size S of the support substrate semiconductor 11 to be prepared satisfies S = Sd−2T.

Step A: The supporting substrate semiconductor 11 is subjected to a thermal oxidation process to form an insulating silicon oxide film 12 on the entire surface of the supporting substrate semiconductor 11.
Step B: A part of one main surface (second main surface) of the support substrate semiconductor 11 on which the silicon oxide film 12 is formed is polished to form a semiconductor exposed portion 13 where the support substrate semiconductor 11 is exposed. At this time, in order not to change the outer diameter of the SOI wafer 1, the semiconductor exposed portion is in a region in the range X from the outer peripheral end of the support substrate semiconductor 11 on which the silicon oxide film 12 is formed to the second main surface. It is desirable to form 13.
Step C: An active layer substrate semiconductor 21 made of single crystal silicon is prepared. The other main surface (first main surface) of the support substrate semiconductor 11 on which the silicon oxide film 12 is formed, on which the semiconductor exposed portion 13 is not formed, and the active layer substrate semiconductor 21 are brought into close contact with each other, and heat treatment is performed to perform the support substrate semiconductor. 11 and the active layer substrate semiconductor 21 are bonded together.
Step D: An active layer (SOI layer) having a desired thickness and shape by polishing the surface (dotted line in Step C) and the end surface of the active layer substrate semiconductor 21 on which the support substrate semiconductor 11 is not bonded. ) 20 is formed. Thereby, the SOI wafer 1 including the active layer 20, the buried oxide film 12a, and the support substrate semiconductor wafer 10 is formed.

<Production Method Example 3>
FIG. 5 is a diagram for explaining a manufacturing method example 3 of the SOI wafer 1 according to the embodiment of the present invention. In this manufacturing method example 3, the following process A to process D are performed.
First, a support substrate semiconductor 11 and an active layer substrate semiconductor 21 made of single crystal silicon are prepared. This support substrate semiconductor 11 is a semiconductor substrate having an outer peripheral size S that is the same as or larger than the desired outer peripheral size Sd in order to cut (or polish) the outer peripheral portion of the SOI wafer 1 in a later step D. prepare. That is, regardless of the thickness of the silicon oxide film 12 to be formed, the outer peripheral size S of the prepared support substrate semiconductor 11 satisfies S ≧ Sd.

Step A: The supporting substrate semiconductor 11 is subjected to a thermal oxidation process to form an insulating silicon oxide film 12 on the entire surface of the supporting substrate semiconductor 11.
Step B: The support substrate semiconductor 11 on which the silicon oxide film 12 is formed and the active layer substrate semiconductor 21 are brought into close contact, and heat treatment is performed to bond the support substrate semiconductor 11 and the active layer substrate semiconductor 21 together.
Step C: An active layer (SOI layer) having a desired thickness and shape by polishing the surface (dotted line in Step B) and the end surface of the active layer substrate semiconductor 21 on the side where the support substrate semiconductor 11 is not bonded. ) 20 is formed. Thereby, the SOI wafer 1 including the active layer 20, the buried oxide film 12a, and the support substrate semiconductor wafer 10 is formed.
Step D: The outer peripheral portion of the support substrate semiconductor wafer 10 is cut (or polished) substantially perpendicularly with a width W equal to or greater than the thickness of the formed silicon oxide film 12 (dotted line in Step C), thereby supporting substrate semiconductor. A semiconductor exposed portion 13 where 11 is exposed is formed. The width W for cutting (or polishing) is determined so that the outer peripheral size S of the SOI wafer 1 after cutting (or polishing) becomes a desired outer peripheral size Sd.

<Production Method Example 4>
FIG. 6 is a diagram for explaining a manufacturing method example 4 of the SOI wafer 1 according to one embodiment of the present invention. In this manufacturing method example 4, the following process A to process D are performed.
First, a support substrate semiconductor 11 made of single crystal silicon is prepared. The support substrate semiconductor 11 is a semiconductor substrate having an outer peripheral size S that is the same size as or larger than the desired outer peripheral size Sd in order to cut (or polish) the outer peripheral portion of the SOI wafer 1 in the subsequent process B. prepare. That is, similarly to the manufacturing method example 3 described above, the outer peripheral size S of the support substrate semiconductor 11 to be prepared satisfies S ≧ Sd.

Step A: The supporting substrate semiconductor 11 is subjected to a thermal oxidation process to form an insulating silicon oxide film 12 on the entire surface of the supporting substrate semiconductor 11.
Step B: Cutting (or polishing) the outer peripheral portion of the support substrate semiconductor 11 on which the silicon oxide film 12 is formed substantially perpendicularly with a width W equal to or greater than the thickness of the formed silicon oxide film 12 (step A). The semiconductor exposed portion 13 where the support substrate semiconductor 11 is exposed is formed. The width W for cutting (or polishing) is determined so that the outer peripheral size S of the SOI wafer 1 after cutting (or polishing) becomes a desired outer peripheral size Sd.
Step C: An active layer substrate semiconductor 21 made of single crystal silicon is prepared. One main surface (first main surface) of the support substrate semiconductor 11 on which the silicon oxide film 12 is formed and the active layer substrate semiconductor 21 are brought into intimate contact with each other, and heat treatment is performed to provide the support substrate semiconductor 11 and the active layer substrate semiconductor 21. Paste together.
Step D: An active layer (SOI layer) having a desired thickness and shape by polishing the surface (dotted line in Step C) and the end surface of the active layer substrate semiconductor 21 on which the support substrate semiconductor 11 is not bonded. ) 20 is formed. Thereby, the SOI wafer 1 including the active layer 20, the buried oxide film 12a, and the support substrate semiconductor wafer 10 is formed.

<Manufacturing method example 5>
FIG. 7 is a diagram for explaining a manufacturing method example 5 of the SOI wafer 1 according to one embodiment of the present invention. In this manufacturing method example 5, the following process A to process D are performed.
First, a support substrate semiconductor 11 and an active layer substrate semiconductor 21 made of single crystal silicon are prepared. This support substrate semiconductor 11 is prepared so as to have an outer peripheral size S that is the same as or larger than the desired outer peripheral size Sd in order to polish the outer peripheral portion of the SOI wafer 1 in the subsequent step D. That is, regardless of the thickness of the silicon oxide film 12 to be formed, the outer peripheral size S of the prepared support substrate semiconductor 11 satisfies S ≧ Sd.

Step A: The supporting substrate semiconductor 11 is subjected to a thermal oxidation process to form an insulating silicon oxide film 12 on the entire surface of the supporting substrate semiconductor 11.
Step B: The support substrate semiconductor 11 on which the silicon oxide film 12 is formed and the active layer substrate semiconductor 21 are brought into close contact, and heat treatment is performed to bond the support substrate semiconductor 11 and the active layer substrate semiconductor 21 together.
Step C: An active layer (SOI layer) having a desired thickness and shape by polishing the surface (dotted line in Step B) and the end surface of the active layer substrate semiconductor 21 on the side where the support substrate semiconductor 11 is not bonded. ) 20 is formed. Thereby, the SOI wafer 1 including the active layer 20, the buried oxide film 12a, and the support substrate semiconductor wafer 10 is formed.
Step D: The outer peripheral portion of the support substrate semiconductor wafer 10 is polished along the outer peripheral shape with a width W equal to or greater than the thickness of the formed silicon oxide film 12 (dotted line in Step C), so that the support substrate semiconductor 11 is An exposed semiconductor exposed portion 13 is formed. Note that the width W to be polished is determined so that the outer peripheral size S of the polished SOI wafer 1 becomes a desired outer peripheral size Sd.

<Production Method Example 6>
FIG. 8 is a diagram for explaining a manufacturing method example 6 of the SOI wafer 1 according to the embodiment of the present invention. In this manufacturing method example 6, the following process A to process D are performed.
First, a support substrate semiconductor 11 made of single crystal silicon is prepared. This support substrate semiconductor 11 is prepared so as to have an outer peripheral size S that is the same size as or larger than the desired outer peripheral size Sd in order to polish the outer peripheral portion of the SOI wafer 1 in the subsequent step B. That is, the outer peripheral size S of the support substrate semiconductor 11 to be prepared satisfies S ≧ Sd as in the above-described Manufacturing Method Example 5.

Step A: The supporting substrate semiconductor 11 is subjected to a thermal oxidation process to form an insulating silicon oxide film 12 on the entire surface of the supporting substrate semiconductor 11.
Step B: The outer peripheral portion of the support substrate semiconductor 11 on which the silicon oxide film 12 is formed is polished along the outer peripheral shape with a width W equal to or greater than the thickness of the formed silicon oxide film 12 (Step A). The semiconductor exposed portion 13 where the support substrate semiconductor 11 is exposed is formed. Note that the width W to be polished is determined so that the outer peripheral size S of the polished SOI wafer 1 becomes a desired outer peripheral size Sd.
Step C: An active layer substrate semiconductor 21 made of single crystal silicon is prepared. One main surface (first main surface) of the support substrate semiconductor 11 on which the silicon oxide film 12 is formed and the active layer substrate semiconductor 21 are brought into intimate contact with each other, and heat treatment is performed to provide the support substrate semiconductor 11 and the active layer substrate semiconductor 21. Paste together.
Step D: An active layer (SOI layer) having a desired thickness and shape by polishing the surface (dotted line in Step C) and the end surface of the active layer substrate semiconductor 21 on which the support substrate semiconductor 11 is not bonded. ) 20 is formed. Thereby, the SOI wafer 1 including the active layer 20, the buried oxide film 12a, and the support substrate semiconductor wafer 10 is formed.

<Production Method Example 7>
FIG. 9 is a diagram for explaining a manufacturing method example 7 of the SOI wafer 1 according to one embodiment of the present invention. In this manufacturing method example 7, after the process D of the manufacturing method example 1 (FIG. 3) described above is completed, the following step E is executed.
Process E: High concentration impurities such as phosphorus (P +) or boron (B +) are introduced into silicon existing in the vicinity of the semiconductor exposed portion 13 formed on the semiconductor wafer 10 for supporting substrate by an ion implantation method or a thermal diffusion method. Then, the high concentration impurity layer 14 is formed.

Similarly, this step E can be performed after the above-described manufacturing method example 3 (FIG. 5), step D, is completed. As a result of this execution, the high-concentration impurity layer shown in FIG. The SOI wafer 1 on which 14 is formed is completed.
Moreover, this process E can also be performed after the process D of the manufacturing method example 5 (FIG. 7) described above is completed. As a result of the execution, the high-concentration impurity layer 14 shown in FIG. The formed SOI wafer 1 is completed.

<Production Method Example 8>
FIG. 10 is a diagram for explaining a manufacturing method example 8 of the SOI wafer 1 according to one embodiment of the present invention. In the manufacturing method example 8, after the process B of the manufacturing method example 2 (FIG. 4) described above is completed, the following step E is executed.
Step E: High concentration impurities such as phosphorus (P +) or boron (B +) are ion-implanted into silicon existing in the vicinity of the semiconductor exposed portion 13 formed on the support substrate semiconductor 11 on which the silicon oxide film 12 is formed. Alternatively, the high-concentration impurity layer 14 is formed by introduction by a thermal diffusion method.

Similarly, this step E can be performed after step B of the manufacturing method example 4 (FIG. 6) described above is completed. As a result of this execution, the high-concentration impurity layer shown in FIG. The SOI wafer 1 on which 14 is formed is completed.
Moreover, this process E can also be performed after the process B of the manufacturing method example 6 (FIG. 8) described above is completed. As a result of this execution, the high-concentration impurity layer 14 shown in FIG. The formed SOI wafer 1 is completed.

  By adding the process E in the manufacturing method example 7 and the manufacturing method example 8 described above, the high concentration impurity layer 14 is formed in the semiconductor exposed portion 13, and the resistance value in the vicinity of the semiconductor exposed portion 13 is lowered. Therefore, it can be expected that the charge injected into the support substrate semiconductor wafer 10 can be discharged into the atmosphere from the semiconductor exposed portion 13 in a shorter time.

<Processing Method for Exposed Semiconductor Part 13>
Next, an effective processing method for forming the semiconductor exposed portion 13 on the support substrate semiconductor wafer 10 will be described.
The processing method described below is realized by using an interlayer CMP process, which is an essential process in the manufacture of the SOI wafer 1, and particularly as shown in manufacturing method example 3 (FIG. 5). This is suitable for a wafer structure in which the semiconductor exposed portion 13 is formed by polishing the outer peripheral portion of the semiconductor wafer 10 for use in a substantially vertical manner.

FIG. 12A is a diagram for explaining a method of polishing the surface of the active layer 120 formed on the surface of the semiconductor wafer 110 for the support substrate using an interlayer film CMP process in the manufacture of the conventional SOI wafer 101.
FIG. 12B shows the surface polishing of the active layer 20 formed on the surface of the semiconductor wafer 10 for the support substrate and the formation of the semiconductor exposed portion 13 using the interlayer CMP process in the manufacture of the SOI wafer 1 of the present invention. It is a figure explaining the method performed simultaneously.

The interlayer CMP process is a chemical mechanical polishing process in which a surface of an uneven insulating film or the like is scraped and flattened using a chemical polishing agent or a polishing pad.
Normally, in a general interlayer CMP process including conventional ones, the surface of the active layer 120 is polished flat by pressing the hard polishing pad 141 against the surface of the active layer 120 and rotating the SOI wafer 101 at a high speed. (FIG. 12A). That is, in the conventional interlayer film CMP process, only the surface of the active layer 120 has been planarized. Therefore, in the conventional manufacturing process of the SOI wafer 101, a separate process for discharging the charged electric charge inside the support substrate semiconductor wafer 110 is required.

  On the other hand, the interlayer CMP process provided by the present invention is characterized in that a deformable soft polishing pad 41 is used. A soft polishing pad 41 is pressed against the surface of the active layer 20 by a pressure applied by a head 42 that adsorbs the SOI wafer 1, and a slidable plate 43 is placed on the side surface of the support substrate semiconductor wafer 10. The soft polishing pad 41 deformed by the pressure applied by is pressed. In this state, by rotating the SOI wafer 1 at a high speed, the surface of the active layer 20 is polished flat, and the side surface of the support substrate semiconductor wafer 10 is also polished to grind the silicon insulating film 12b (FIG. 12B). That is, in the interlayer film CMP process of the present invention, the surface of the active layer 20 can be planarized, and at the same time, the semiconductor exposed portion 13 can be formed on the side surface of the support substrate semiconductor wafer 10.

  The polishing pad 41 does not need to be a deformable soft polishing pad. Even if the polishing pad 41 is a hard polishing pad depending on the shape, the surface of the active layer 20 is planarized and at the same time the semiconductor wafer 10 for the support substrate is formed. The semiconductor exposed portion 13 can be formed on the side surface. For example, a so-called cup-shaped polishing pad in which an outer peripheral side wall is provided at a substantially right angle on a circular bottom surface that matches the outer peripheral size Sd of the SOI wafer 1 can be considered.

As described above, according to the SOI wafer 1 according to an embodiment of the present invention, the support substrate semiconductor 11 is exposed to the support substrate semiconductor wafer 10 by removing the silicon oxide film 12b and directly exposed to the atmosphere. A semiconductor exposed portion 13 is formed.
The positive charge injected into the support substrate semiconductor wafer 10 by the positive ion implantation process by the semiconductor exposed portion 13 is immediately discharged into the atmosphere from the semiconductor exposed portion 13 without accumulating in the support substrate semiconductor 11. The
For this reason, even if the SOI wafer 1 of the present invention is placed on the transfer stage 50 used in the wafer manufacturing facility, the electrostatic adsorption phenomenon does not occur. Occurrence can be prevented.

Further, according to the method for manufacturing an SOI wafer according to an embodiment of the present invention, the same 1 is applied to the surface of the active layer 20 and the side surface of the semiconductor wafer 10 for the support substrate, using the deformable soft polishing pad 41. Two polishing pads 41 are pressed against each other.
As a result, the surface of the active layer 20 is planarized, and at the same time, the semiconductor exposed portion 13 is formed on the side surface of the support substrate semiconductor wafer 10.

  In addition, as shown in the said manufacturing method example 3 (FIG. 5) and manufacturing method example 4 (FIG. 6), the outer peripheral part of the semiconductor wafer 10 for support substrates is more than the thickness of the silicon oxide film 12 formed into a film. When the semiconductor exposed portion 13 in which the support substrate semiconductor 11 is exposed is formed by cutting or polishing substantially vertically with the width W, the effect of solving the knife edge problem is exhibited.

  The knife edge is a support as shown in FIG. 13A when the second main surface of the support substrate semiconductor wafer 10 on which the active layer 20 is not formed is polished in the final stage of the semiconductor wafer manufacturing process. This means that the outer peripheral edge 60 of the substrate semiconductor wafer 10 has an acute angle. The problem due to the knife edge means that the sharp outer peripheral edge 60 is stuck in a case or the like, resulting in poor conveyance, generation of case dust, and wafer chipping.

On the other hand, when the semiconductor exposed portion 13 is formed by cutting or polishing the outer peripheral portion of the semiconductor wafer 10 for supporting substrate substantially vertically as in the present invention, the supporting substrate is formed in the final stage of the semiconductor wafer manufacturing process. Even if the second main surface of the semiconductor wafer 10 for polishing is polished, the outer peripheral end portion 60 of the semiconductor wafer 10 for support substrate does not become an acute angle as shown in FIG.
Therefore, it is possible to prevent the occurrence of knife edge problems such as conveyance failure, generation of case dust, and wafer chipping.

  INDUSTRIAL APPLICABILITY The present invention can be used for manufacturing an SOI wafer in which a silicon layer is formed on a silicon oxide film that is an insulating layer, and in particular, in the SOI wafer manufacturing process, a wafer conveyance defect caused by electrostatic adsorption phenomenon. This is useful when it is desired to prevent the occurrence of the above.

DESCRIPTION OF SYMBOLS 1,101 SOI wafers 10 and 110 Support substrate semiconductor wafers 11 and 111 Support substrate semiconductors 12 and 12b and 112 Silicon oxide film 12a Embedded oxide film 13 Semiconductor exposed portion 14 High concentration impurity layer 20 and 120 Active layer (SOI layer)
21 Active layer substrate semiconductors 41 and 141 Polishing pads 42 and 142 Suction head 43 Plate 50 Transfer stage 60 Outer peripheral edge (knife edge)

Claims (5)

An SOI wafer in which an active layer semiconductor layer is formed on a first main surface of a support substrate semiconductor wafer having an oxide film formed on its surface,
On the side surface of the support substrate semiconductor wafer, there is a semiconductor exposed portion where the support substrate semiconductor inside the wafer is exposed,
An SOI wafer, wherein a high-concentration impurity layer is formed in the semiconductor exposed portion.   The semiconductor exposed portion is formed in a region on the second main surface side facing the first main surface where the active layer semiconductor layer is formed from an outer peripheral end portion of the support substrate semiconductor wafer. The SOI wafer according to claim 1, wherein the SOI wafer is characterized. A method of manufacturing an SOI wafer in which an active layer semiconductor layer is formed on a first main surface of a support substrate semiconductor wafer having an oxide film formed on a surface thereof,
Cutting or polishing an outer peripheral portion of the support substrate semiconductor wafer substantially perpendicularly with a width equal to or greater than the thickness of the oxide film to form a semiconductor exposed portion in which the support substrate semiconductor is exposed; and
A step of introducing a high concentration impurity into the semiconductor exposed portion to form a high concentration impurity layer,
The semiconductor exposure unit, the characterized in that it is formed an outer peripheral portion of the supporting semiconductor substrate wafer substantially by cutting or polishing vertically method of S OI wafer. A method of manufacturing an SOI wafer in which an active layer semiconductor layer is formed on a first main surface of a support substrate semiconductor wafer having an oxide film formed on a surface thereof,
Polishing the outer periphery of the support substrate semiconductor wafer along the outer periphery with a width equal to or greater than the thickness of the oxide film to form a semiconductor exposed portion where the support substrate semiconductor is exposed; and
A step of introducing a high concentration impurity into the semiconductor exposed portion to form a high concentration impurity layer,
The semiconductor exposure unit, the oxide film formed on the outer peripheral portion of the semiconductor wafer for the support substrate, characterized in that it is formed by grinding along the shape of the outer peripheral portion, the production of S OI wafer Way . A method of manufacturing an SOI wafer in which an active layer semiconductor layer is formed on a first main surface of a support substrate semiconductor wafer having an oxide film formed on a surface thereof,
One polishing pad is brought into contact with the surface of the active layer semiconductor layer and the side surface of the support substrate semiconductor wafer, and the surface and the side surface are polished simultaneously to form a semiconductor exposed portion where the support substrate semiconductor is exposed. Process ,
A step of introducing a high concentration impurity into the semiconductor exposed portion to form a high concentration impurity layer ,
The polishing pad is a deformable material,
The polishing step comprises deforming the polishing pad to bring the polishing pad into contact with both the surface of the active layer semiconductor layer and the side surface of the support substrate semiconductor wafer. Production method.

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