JP5960445B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device including a lateral diffusion type field effect transistor structure and a manufacturing technique thereof.

  Laterally diffused (LD) type field effect transistors are widely used in power semiconductor elements such as power amplifiers. In this type of LD field effect transistor, for example, the drain breakdown voltage can be increased by widening the distance between the drain region and the gate electrode in the lateral direction parallel to the main surface of the substrate.

1A and 1B illustrate a schematic configuration of a conventional LD-type MOS transistor (LDMOS) 100. FIG. FIG. 1A is a top view of the LDMOS 100. FIG. 1B is a schematic cross-sectional view taken along line Ib-Ib of the LDMOS 100 shown in FIG. As shown in FIG. 1B, the LDMOS 100 is formed on a P-type silicon substrate 110, a field insulating film 113 formed by a LOCOS (Local Oxidation of Silicon) method, and the P-type silicon substrate 110. A thin gate oxide film 115, a gate structure 116 formed on the gate oxide film 115, and a source region 120S and a drain region 120D made of N ⁺ -type impurity diffusion regions formed on both sides of the gate structure 116 are provided. Have. In the vicinity of the main surface in the silicon substrate 110, a substrate contact region 121 composed of a P ⁺ type impurity diffusion region laterally adjacent to the source region 120S is formed. In the silicon substrate 110, an N-type well region 111 is formed between the gate structure 116 and the drain region 120D. The gate structure 116 includes a gate electrode 117 and sidewall spacers 118S and 118D formed on both side walls of the gate electrode 117.

  As shown in FIG. 1A, this LDMOS 100 has a drawback that the element area is increased because the substrate contact region 121 is disposed outside the source region 120S in the lateral direction. Japanese Laid-Open Patent Publication No. 5-343678 (Patent Document 1) discloses an LDMOS structure that can improve such a drawback. FIG. 2 is a top view showing a part of the LDMOS structure 200 disclosed in Patent Document 1. In FIG. As shown in FIG. 2, the LDMOS structure 200 includes a gate electrode 217 extending in the X-axis direction. A source region 220S and a drain region 220D are formed on both sides of the gate electrode 217, and an extended drain region 211 is formed between the drain region 220D and the gate electrode 217. Since the source regions 220S and the substrate contact regions 221 are alternately arranged along the extending direction (X-axis direction) of the gate electrode 217, the element area (dimension in the Y-axis direction) can be reduced.

JP-A-5-343678 (FIG. 1, paragraph 0005, etc.)

  However, in the conventional LDMOS structure 200, when the misalignment occurs in the alignment (alignment) of the ion implantation mask for the substrate contact region 221 and the misalignment of the substrate contact region 221 occurs, the effective channel width decreases, and the current There is a problem that the driving ability is lowered.

  In view of the above, an object of the present invention is to provide a semiconductor device capable of ensuring a sufficient effective channel width and reducing the element area.

A semiconductor device according to an aspect of the present invention includes a gate insulating film formed on a main surface of a semiconductor substrate, a gate electrode formed on the gate insulating film and extending along the main surface, and the semiconductor substrate A source region formed of an impurity diffusion region of the first conductivity type formed on one side of both sides of the gate electrode, and formed on the other side of both sides of the gate electrode in the semiconductor substrate, A drain region composed of an impurity diffusion region of the same conductivity type as the first conductivity type, and a second region different from the first conductivity type, formed outside the source region with respect to the gate electrode in the semiconductor substrate. and a substrate contact region formed of impurity diffusion regions of the conductivity type, together with the a the end portions of the source region side and the drain region side of the gate electrode to form a rectangular shaped end, said semiconductor base The source region is formed so as to surround the drain region, and the end of the source region on the gate electrode side forms a rectangular end and is formed so as to surround the gate electrode, An outer peripheral end portion of the drain region has a linear portion and an arc portion facing the source region, and one end portion of the source region on the substrate contact region side is arranged along the extending direction of the gate electrode. a plurality of concave portions, the other end of the gate electrode side of the source region, the plurality of spaced apart by a recess arranged line Jo且 one and along the extending direction of the gate electrode continuously The substrate contact region has a plurality of facing regions arranged along the extending direction of the gate electrode and facing the plurality of concave portions, and the plurality of facing regions are the plurality of facing regions. In the concave part of Characterized in that it is arranged Re respectively.

  According to the present invention, the other end of the source region is spaced apart from the plurality of concave portions formed at one end of the source region, and is linear and continuous along the extending direction of the gate electrode. Therefore, even if the position of the substrate contact region is shifted in the separation direction or the proximity direction with respect to the gate electrode, the source region can be prevented from being divided due to the positional deviation. Further, since the opposing region constituting the substrate contact region is disposed in the concave portion of the source region, the element area can be reduced. Therefore, a sufficient effective channel width can be ensured and the element area can be reduced.

(A), (B) is a figure which illustrates schematic structure of the conventional LD type MOS transistor (LDMOS). 10 is a top view showing a part of an LDMOS structure disclosed in Patent Document 1. FIG. It is a top view which shows schematic structure of the semiconductor device of Embodiment 1 which concerns on this invention. FIG. 4 is an enlarged top view showing a partial region below the semiconductor device shown in FIG. 3. (A) is a schematic sectional drawing in the Va-Va line of the semiconductor device of FIG. 4, (B) is a schematic sectional drawing in the Vb-Vb line of the semiconductor device 1 of FIG. FIG. 6 is a cross sectional view for schematically illustrating a first manufacturing process for the semiconductor device of the first embodiment. FIG. 10 is a cross sectional view for schematically illustrating a second manufacturing process for the semiconductor device of the first embodiment. FIG. 10 is a cross sectional view for schematically illustrating a third manufacturing process for the semiconductor device of the first embodiment. FIG. 10 is a cross sectional view for schematically illustrating a fourth manufacturing process for the semiconductor device of the first embodiment. FIG. 10 is a cross sectional view for schematically illustrating a fifth manufacturing process for the semiconductor device of the first embodiment. FIG. 10 is a cross sectional view for schematically illustrating a sixth manufacturing process of the semiconductor device of the first embodiment. FIG. 10 is a cross sectional view for schematically illustrating a seventh manufacturing process for the semiconductor device of the first embodiment. FIG. 25 is a cross sectional view for schematically illustrating an eighth manufacturing process for the semiconductor device of the first embodiment. FIG. 23 is a cross sectional view for schematically illustrating a ninth manufacturing process for the semiconductor device of the first embodiment. It is sectional drawing for showing roughly the 10th manufacturing process of the semiconductor device of Embodiment 1. (A), (B) is a figure which shows the case where the position of the board | substrate contact area | region of Embodiment 1 each shifted to the near direction and the separation direction with respect to the gate structure. FIG. 3 is a diagram showing the arrangement of source regions when the position of a substrate contact region shown in FIG. 2 is shifted to the right. FIG. 6 is a top view showing a schematic configuration of a semiconductor device which is a modification of the first embodiment. FIG. 6 is a top view illustrating a schematic configuration of a semiconductor device according to a second embodiment. FIG. 20 is an enlarged top view showing a partial region below the semiconductor device 2 shown in FIG. 19. 20A is a schematic cross-sectional view taken along line XXIa-XXIa of the semiconductor device 1 of FIG. 20, and FIG. 20B is a schematic cross-sectional view taken along line XXIb-XXIb of the semiconductor device 1 of FIG.

  Hereinafter, various embodiments according to the present invention will be described with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and detailed description thereof is appropriately omitted so as not to overlap.

Embodiment 1 FIG.
FIG. 3 is a top view showing a schematic configuration of the semiconductor device 1 including the lateral diffusion type field effect transistor structure according to the first embodiment of the present invention.

As shown in FIG. 3, the semiconductor device 1 includes a drain region 20 made of an N ⁺ -type impurity diffusion region formed in a surface layer portion of a semiconductor substrate (not shown), and an outer peripheral end portion of the drain region 20. A gate structure 16 formed on the semiconductor substrate is provided so as to surround the field insulating film 12 interposed between the drain region 20 and the gate structure 16. The gate structure 16 has a rectangular ring shape as a whole, and extends in the X-axis direction and the Y-axis direction perpendicular thereto. The X axis and the Y axis are parallel to the main surface of the semiconductor substrate, and the Z axis shown in FIG. 3 is perpendicular to the main surface of the semiconductor substrate.

The semiconductor device 1 further includes a source region 21 formed of an N ⁺ -type impurity diffusion region formed in a surface layer portion of the semiconductor substrate so as to surround a rectangular outer peripheral end portion of the gate structure 16, and an outer peripheral end of the source region 21. And a substrate contact region 22 formed of a P ⁺ -type impurity diffusion region formed in the surface layer portion of the semiconductor substrate so as to surround the portion.

  The inner peripheral end of the source region 21 has a rectangular ring shape as a whole, and is formed linearly and continuously along the extending direction of the outer peripheral end of the gate structure 16 as shown in FIG. . On the other hand, the outer peripheral end portion of the source region 21 has a plurality of concave portions 21C,..., 21C arranged along the extending direction of the gate structure 16. These concave portions 21C,..., 21C are arranged at a predetermined pitch Pc (for example, about 2 μm to 10 μm), and each concave portion 21C has a certain width Wc (for example, about 2 μm to 10 μm). Further, the source region 21 has a linear end 21ec that forms a part of the outer peripheral end of the source region 21 between the adjacent concave portions 21C and 21C. As shown in FIG. 3, each linear end 21 ec extends by a certain width Wc along the extending direction (X-axis direction or Y-axis direction) of the outer peripheral end portion of the gate structure 16.

As shown in FIG. 3, the substrate contact region 22 includes a plurality of opposing regions (P ⁺ -type impurity diffusion regions) 22P,..., 22P that face the concave portions 21C,. These opposed regions 22P,..., 22P are respectively disposed in the recessed portions 21C,..., 21C over the entire outer peripheral end portion of the source region 21, and are formed in the lateral direction (X-axis direction) with the recessed portions 21C,. And a direction parallel to both the Y-axis direction and the Y-axis direction).

  Drain region 20 only needs to have an outer diameter within a range of about 100 μm to several hundred μm, for example. Further, the interval between the drain region 20 and the gate structure 16 may be set to a value (for example, within a range of about 10 μm to several tens of μm) according to the target breakdown voltage. The larger the distance between the drain region 20 and the gate structure 16, the greater the electric field relaxation effect in the region between the drain region 20 and the gate structure 16. Therefore, the larger the target breakdown voltage, the larger the distance. Is desirable.

  Note that contact plugs that electrically connect the drain region 20, the gate structure 16, the source region 21, and the substrate contact region 22 to the upper layer wiring group are formed. For convenience of explanation, these contact plugs and the upper layer wiring group are formed. Not shown.

  4 is an enlarged top view showing a partial region below the semiconductor device 1 shown in FIG. 3, and FIG. 5A is a schematic cross-sectional view taken along the line Va-Va of the semiconductor device 1 shown in FIG. And represents a cross section that crosses both the opposing region 22P of the substrate contact region 22 and the source region 21. FIG. 5B is a schematic cross-sectional view taken along the line Vb-Vb of the semiconductor device 1 of FIG. 4 and shows a cross section crossing the source region 21.

As shown in FIGS. 5A and 5B, the semiconductor device 1 includes an N-type well region 11 formed of a low-concentration N ⁻ -type impurity diffusion region in a P-type semiconductor substrate 10, and this N-type. An electric field relaxation region 13 made of an N-type impurity diffusion region surrounded by the well region 11 and a P-type diffusion region 14 facing the N-type well region 11 in the lateral direction are provided. The semiconductor device 1 includes a gate insulating film 15 formed on the main surface of the semiconductor substrate 10, a gate structure 16 formed on the gate insulating film 15, and one side of both sides of the gate structure 16. A source region 21 formed on the gate structure 16, a drain region 20 formed on the other side of the gate structure 16, and a counter region 22 </ b> P formed outside the source region 21 with respect to the gate structure 16. . A field insulating film 12 is interposed between the gate structure 16 and the drain region 20. The drain region 20, the source region 21, and the counter region 22P are impurity diffusion regions formed in the surface layer portion (relatively shallow region) of the semiconductor substrate 10. In the present embodiment, the source region 21 and the counter region 22P are joined to each other in the lateral direction.

  The gate insulating film 15 is a thin film made of a high dielectric constant material such as silicon oxide. The gate structure 16 includes a gate electrode 17 made of a polycrystalline silicon material doped with impurities at a high concentration, and side wall spacers 18S and 18D made of an insulating material formed on both side walls of the gate electrode 17. Yes.

  The field insulating film 12 interposed between the gate electrode 17 and the drain region 20 can be formed by, for example, a known LOCOS (Local Oxidation of Silicon) method. Instead of the field insulating film 12, a trench isolation structure composed of a groove formed by etching in the semiconductor substrate 10 and an insulating material embedded in the groove may be employed. As shown in FIGS. 5A and 5B, one end of the gate electrode 17 extends so as to run on the field insulating film 12 from above the gate insulating film 15. It functions as a field plate that reduces the electric field strength.

  In the present embodiment, a P-type single crystal silicon substrate is used as the semiconductor substrate 10, but the present invention is not limited to this. Instead of the single crystal silicon substrate, for example, a semiconductor substrate including a compound semiconductor layer or an epitaxial crystal layer may be used.

  As shown in FIG. 4, the source region 21 extends along the extending direction of the gate electrode 17 and has a constant width La (for example, within a range of several μm to several tens of μm). The source region 21 has concave portions 21C,..., 21C that are periodically arranged along the extending direction of the gate electrode 17. Each concave portion 21C has a constant width Lc (for example, within a range of 1 μm to several tens of μm), and this width Lc is always smaller than the entire width La of the source region 21. Therefore, since a diffusion region having a constant width Lb is always ensured between the one end 21ed of the concave portion 21C and the drain side end portion of the source region 21, the source region 21 is divided in the extending direction of the gate electrode 17. There is nothing. Therefore, the effective width (effective channel width) of the channel formed between the source region 21 and the drain region 20 when the semiconductor device 1 is driven is not reduced, and the current driving capability of the field effect transistor is not impaired. There is.

Further, as shown in FIG. 4, opposing regions 22 ^</ b ^> P having a conductivity type (P ⁺ type) opposite to that of the source region 21 are formed in each concave portion 21 ^</ b ^> C. In the present embodiment, one end 22ed of the facing region 22P is joined to one end 21ed of the concave portion 21C. The opposing region 22P has opposing ends 22ea and 22eb that are joined to the side ends 21ea and 21eb of the concave portion 21C, respectively. The side ends 21ea and 21eb and the opposing ends 22ea and 22eb are all linearly extending in a direction perpendicular to the extending direction of the gate electrode 17. Therefore, as will be described later, the alignment of the ion implantation mask for forming the substrate contact region 22 causes a shift in the separation direction or the proximity direction (Y-axis direction in the case of FIG. 4) with respect to the gate electrode 17. In addition, the side end 21ea and the facing end 22ea are not separated from each other, and a mutual joining state can be ensured. Similarly, the side end 21eb and the opposite end 22eb are not separated from each other, and it is possible to ensure the mutual joining state. Therefore, even if the substrate contact region 22 is misaligned, it is possible to suppress a decrease in the ON breakdown voltage during the operation of the field effect transistor.

  Next, a method for manufacturing the semiconductor device 1 will be described. 6 to 15 are cross-sectional views of the semiconductor structure for schematically showing an example of the manufacturing process of the semiconductor device of the first embodiment.

First, as shown in FIG. 6, a P-type silicon substrate is prepared as the semiconductor substrate 10. Next, the main surface (upper surface) of the semiconductor substrate 10 is thermally oxidized to form a protective oxide film having a thickness of about several tens of nanometers, and then a resist pattern is formed on the protective oxide film using a photolithography technique. To do. Then, N-type impurities such as phosphorus (P) are selectively ion-implanted into the semiconductor substrate 10 using this resist pattern as a mask (for example, the dose is about 10 ¹² ions / cm ² ). Thereafter, the resist pattern and the protective oxide film are removed. Then, the implanted N-type impurity ions are activated by heat treatment to form an N-type well region 11 as shown in FIG.

Next, as shown in FIG. 8, the field insulating film 12 is formed by the LOCOS method. The thickness of the field insulating film 12 may be controlled to be about several hundred nm. Specifically, a pad oxide film is formed on the structure of FIG. 7, and then a silicon nitride film (Si ₃ N ₄ ) is formed on the pad oxide film by a CVD (Chemical Vapor Deposition) method. Next, the silicon nitride film is selectively removed using a semiconductor lithography technique to form an opening. Next, the field insulating film 12 can be formed by heat-treating the semiconductor substrate (wafer) 10 in a heat treatment furnace. Thereafter, for example, the silicon nitride film is removed by plasma etching, and the pad oxide film is removed with an aqueous solution containing hydrogen fluoride (HF).

Next, using a photolithography technique, a resist pattern having an opening is formed immediately above the field insulating film 12 in FIG. Subsequently, N-type impurities such as phosphorus (P) are selectively ion-implanted into a region in the semiconductor substrate 10 immediately below the field insulating film 12 using this resist pattern as a mask (for example, the dose is 10 ¹² ions / cm). ² ). Further, the implanted N-type impurity ions are activated by annealing. As a result, an electric field relaxation region 13 is formed immediately below the field insulating film 12 as shown in FIG.

  Next, the exposed surface of the semiconductor substrate 10 of FIG. 9 is thermally oxidized in an oxygen atmosphere to form an oxide film 15P for a gate insulating film as shown in FIG. The thickness of the oxide film 15P may be controlled to be a thickness corresponding to the target breakdown voltage (for example, within a range of 10 nm to 100 nm). In the present embodiment, a thermal oxide film is formed as the oxide film 15P. However, the present invention is not limited to this. Instead of the thermal oxide film, a high dielectric constant thin film such as a silicon oxynitride film may be formed.

  Next, using a photolithography technique, a resist pattern having an opening is formed on the structure of FIG. 10 immediately above the region where the P-type diffusion region 14 is to be formed. Next, using this resist pattern as a mask, a P-type impurity such as boron (B) is ion-implanted into the semiconductor substrate 10. As a result, a P-type diffusion region 14 is formed in the semiconductor substrate 10 as shown in FIG. The P-type diffusion region 14 has a function of adjusting the threshold voltage of the field effect transistor, and also has a function as a channel stopper.

  Next, a conductive material layer such as polycrystalline silicon is formed over the entire surface of the structure in FIG. 11 by, for example, a low pressure CVD (Low-Pressure Chemical Vapor Deposition) method, and this conductive material layer is formed by photolithography. Patterning is performed using a technique and an etching technique. As a result, the gate electrode 17 is formed as shown in FIG. The thickness of the gate electrode 17 may be controlled to be several hundred nm, for example. Subsequently, an insulating film made of an insulating material such as silicon oxide is deposited on the structure of FIG. 12 by, for example, the CVD method, and this insulating film is etched back by anisotropic etching. As a result, the side wall spacers 18S and 18D shown in FIG. 13 are formed on both side walls of the gate electrode 17.

Next, a resist pattern 35 for the drain region 20 and the source region 21 is formed on the structure of FIG. 13 by photolithography (FIG. 14). Next, N-type impurities such as arsenic (As) are ion-implanted into a relatively shallow region in the semiconductor substrate 10 using the resist pattern 35, the field insulating film 12 and the gate structure 16 as an ion implantation mask (for example, a dose amount). Is about 10 ¹⁵ ions / cm ² ). Thereby, the drain region 20 and the source region 21 are formed as shown in FIG. Thereafter, the resist pattern 35 is removed.

Further, a resist pattern 36 that covers the drain region 20 and the source region 21 is formed by photolithography as shown in FIG. Next, using the resist pattern 36 as an ion implantation mask, a P-type impurity such as boron (B) is ion-implanted into a relatively shallow region in the semiconductor substrate 10 (for example, the dose is about 10 ¹⁵ ions / cm ² ). As a result, as shown in FIG. 15, the opposing region 22P forming the substrate contact region 22 is formed. Thereafter, the resist pattern 36 is removed. The impurity ions implanted for the drain region 20, the source region 21, and the substrate contact region 22 are activated by heat treatment.

  Through the steps described above, the semiconductor device 1 having the field-effect transistor structure illustrated in FIGS. 5A and 5B can be manufactured. 5A and 5B, a contact plug (not shown) that electrically connects the drain region 20, the gate electrode 17, the source region 21, and the substrate contact region 22 to the upper layer wiring group. ) And a step of forming the upper layer wiring group.

  Next, effects of the semiconductor device 1 of the first embodiment will be described.

  In the semiconductor device 1 of the present embodiment, as shown in FIG. 4, a diffusion region having a constant width Lb is necessarily provided between one end 21 ed of the concave portion 21C of the source region 21 and the drain side end portion of the source region 21. It is done. For this reason, even when a positional deviation occurs during alignment of the ion implantation mask 36 for the substrate contact region 22 (FIG. 15) or the ion implantation mask 35 for the source region 21 (FIG. 14), the positional deviation is fixed by a certain width. It can be absorbed in the diffusion region of Lb. Therefore, it is possible to reliably avoid the source region 21 being divided in the extending direction of the gate electrode 17.

  FIGS. 16A and 16B are views showing a state in which the position of the substrate contact region 22 is shifted in the proximity direction and the separation direction with respect to the gate structure 16. As shown in FIG. 16A, even when the position of the substrate contact region 22 is shifted in the direction approaching the gate structure 16, the one end 21ed of the concave portion 21C of the source region 21 and the drain side end portion of the source region 21 An impurity diffusion region can be secured between the source regions 21 and the source region 21 can be prevented from being divided due to this positional shift. Further, the side ends 21ea, 21eb of the concave portion 21C and the facing ends 22ea, 22eb of the facing region 22P are not separated from each other, and a mutual joining state is secured. On the other hand, as shown in FIG. 16B, even when the position of the substrate contact region 22 is shifted in the direction away from the gate structure 16, the side ends 21ea and 21eb of the concave portion 21C and the opposing end 22ea of the opposing region 22P. , 22eb are not spaced apart from each other and ensure a joint state with each other.

  On the other hand, FIG. 17 is a diagram showing the arrangement of the source regions 220S,..., 220S when the position of the substrate contact region 221 of Patent Document 1 shown in FIG. Since the source regions 220S,..., 220S are eroded by the displacement of the substrate contact region 221, the source regions 220S,..., 220S are completely divided in the extending direction of the gate electrode 217. Therefore, the structure of FIG. 17 has a smaller effective channel width than the structure of FIG.

  Therefore, in the semiconductor device 1 according to the first embodiment, even when the substrate contact region 22 and the source region 21 are misaligned, the effective channel width is not reduced, and deterioration of the current drive capability of the field effect transistor is suppressed. Can do. Moreover, since the opposing region 22P of the substrate contact region 22 is disposed in each concave portion 21C of the source region 21, the element area can be reduced.

Further, even when the substrate contact region 22 and the source region 21 are misaligned, the side ends 21ea and 21eb of the concave portion 21C and the opposing ends 22ea and 22eb of the opposing region 22P are not separated from each other and are joined to each other. Since the state can be secured, it is also possible to suppress a decrease in the on-breakdown voltage of the field effect transistor due to the positional deviation. If the substrate contact region 22 and the source region 21 are separated from each other, the N-type well region 11 is used as a collector as compared with the case where the substrate contact region 22 and the source region 21 are joined as in the present embodiment. Since the base resistance (resistance between the P-type opposing region 22P and the base) of the parasitic NPN bipolar transistor having the P-type semiconductor substrate 10 as a base and the N-type source region 21 as an emitter increases, the parasitic NPN the current amplification factor h _FE of the bipolar transistor is increased, the on-state breakdown voltage decreases. On the other hand, in the present embodiment, since the junction state between the substrate contact region 22 and the source region 21 can be ensured, it is possible to suppress a decrease in the ON breakdown voltage of the field effect transistor of the semiconductor device 1.

  Furthermore, as shown in FIG. 2, since the front end portions 220Se,..., 220Se of the source region 220S of Patent Document 1 form an acute angle, when a current having a high current density flows through the front end portions 220Se,. The parts 220Se,..., 220Se may be destroyed by Joule heat. On the other hand, in the semiconductor device 1 of the present embodiment, as shown in FIG. 4, the linear end 21 ec disposed between the concave portions 21 </ b> C and 21 </ b> C of the source region 21 is the extending direction of the gate electrode 17. Therefore, it is possible to avoid the portion near the linear end 21 ec from being destroyed by Joule heat.

  In the present embodiment, as shown in FIG. 3, the opposing regions 22P,..., 22P are electrically separated from each other in the extending direction of the gate structure 16, but the present invention is not limited to this. . Conductive regions that electrically connect the opposing regions 22P, ..., 22P may be provided. FIG. 18 is a top view showing a schematic configuration of a semiconductor device 1M which is a modification of the first embodiment. As shown in FIG. 18, the substrate contact region 22M of the present modification is a counter region 22P arranged so as to surround the entire outer peripheral end of the source region 21, like the substrate contact region 22 of the semiconductor device 1 of FIG. ,..., 22P, and an outer peripheral region 22L that electrically connects these opposing regions 22P,. Thereby, the potential of the entire substrate contact region 22M can be stabilized.

Embodiment 2. FIG.
Next, a second embodiment according to the present invention will be described. FIG. 19 is a top view showing a schematic configuration of the semiconductor device 2 including the lateral diffusion type field effect transistor structure of the second embodiment.

As shown in FIG. 19, semiconductor device 2 surrounds drain region 20 formed of an N ⁺ -type impurity diffusion region and an outer peripheral end portion of drain region 20, similarly to semiconductor device 1 of the first embodiment. The gate structure 16 formed on the semiconductor substrate, the field insulating film 12 interposed between the gate structure 16 and the drain region 20, and the rectangular outer peripheral end of the gate structure 16 are formed. And a source region 21 made of an N ⁺ -type impurity diffusion region.

In addition, the semiconductor device 2 has a substrate contact region 23 composed of a P ⁺ -type impurity diffusion region surrounding the entire outer peripheral end of the source region 21. A field insulating film 12P is interposed between the substrate contact region 23 and the source region 21. The field insulating film 12P is simultaneously formed in the same process as the field insulating film 12 on the inner peripheral side. The substrate contact region 23 has opposing regions 23P,..., 23P that are spaced apart from the outer peripheral end of the source region 21, and further, an external connection that electrically connects all of these opposing regions 23P,. It has a peripheral region 23L. The opposing regions 23P,..., 23P face the concave portions 21C,..., 21C of the source region 21 and are disposed in the concave portions 21C,. It is spaced apart from the outer peripheral end of 21 without joining.

  20 is an enlarged top view showing a partial region below the semiconductor device 2 shown in FIG. FIG. 21A is a schematic cross-sectional view taken along line XXIa-XXIa of the semiconductor device 1 in FIG. Represents. FIG. 21B is a schematic cross-sectional view taken along the line XXIb-XXIb of the semiconductor device 1 of FIG. 20, and shows a cross section crossing the source region 21 and the outer peripheral region 23L. The manufacturing process of the semiconductor device 2 of the present embodiment is performed except that the formation region of the substrate contact region 22 and the formation region of the substrate contact region 23 are different from each other and the field insulating film 12P is formed. This is almost the same as the manufacturing process of the semiconductor device 1 of the first embodiment.

  As shown in FIGS. 20 and 21A and 21B, the source region 21 and the substrate contact region 23 are separated from each other by a constant gap width Gp. The field effect transistor structure of the semiconductor device 1 of the first embodiment is a structure suitable for using the source region 21 and the substrate contact region 22 at the same potential, whereas the semiconductor device of the present embodiment. The field effect transistor structure No. 2 is a structure suitable for use by applying different voltages to the source region 21 and the substrate contact region 23.

  In the semiconductor device 2 of the second embodiment, the convex portions between the concave portions 21C and 21C of the source region 21 and the opposing regions 23P are alternately arranged along the extending direction of the gate electrode 17, and each concave portion A counter area 23P is arranged in 21C. For this reason, an element area can be made small.

Furthermore, since a part of the substrate contact region 23, that is, the facing region 23P protrudes in the direction of the source region 21, the contact area between the substrate contact region 23 and the P-type region in the semiconductor substrate 10 can be increased. Therefore, as compared with a configuration in which part of the substrate contact region 23 does not protrude in the direction of the source region 21 (a configuration in which the opposing region 23P does not exist), the configuration of the present embodiment uses the N-type well region 11 as a collector, The base resistance (resistance between the P-type opposing region 23P and the base) of the parasitic NPN bipolar transistor having the P-type region in the semiconductor substrate 10 as a base and the N-type source region 21 as an emitter can be reduced. since, it is possible to lower the current amplification factor _{h FE} of the parasitic NPN bipolar transistor. Therefore, the on breakdown voltage of the semiconductor device 2 can be improved.

Modifications of the first and second embodiments.
As mentioned above, although embodiment of this invention was described with reference to drawings, these are illustrations of this invention and can also employ | adopt various forms other than the above. For example, each of the semiconductor devices 1, 1M, and 2 has an N-channel field effect transistor structure, but is not limited thereto. A P-channel field effect transistor structure can be formed by changing the conductivity type of the impurity diffusion regions constituting the semiconductor devices 1, 1 </ b> M, and 2 to the opposite conductivity type.

  1,1M, 2 semiconductor device, 10 semiconductor substrate, 11 N-type well region, 12 field insulating film, 13 electric field relaxation region, 14 P-type diffusion region, 15 gate insulating film, 16 gate structure, 17 gate electrode, 18S, 18D Side wall spacer, 20 drain region, 21 source region, 21C concave portion, 21ec linear end, 21ea, 21eb lateral end, 22, 23 substrate contact region, 22P, 23P opposing region, 22ea, 22eb, 23ea, 23eb opposing end 22L, 23L Outer peripheral edge region.

Claims (7)

A gate insulating film formed on the main surface of the semiconductor substrate;
A gate electrode formed on the gate insulating film and extending along the main surface;
A source region comprising an impurity diffusion region of a first conductivity type formed on one side of both sides of the gate electrode in the semiconductor substrate;
A drain region formed on the other side of both sides of the gate electrode in the semiconductor substrate and comprising an impurity diffusion region of the same conductivity type as the first conductivity type;
A substrate contact region formed outside the source region with respect to the gate electrode in the semiconductor substrate and comprising an impurity diffusion region of a second conductivity type different from the first conductivity type;
The end portion on the source region side and the end portion on the drain region side of the gate electrode form a rectangular end portion and are formed so as to surround the drain region on the main surface of the semiconductor substrate. ,
An end portion of the source region on the gate electrode side forms a rectangular end portion and is formed so as to surround the gate electrode,
The outer peripheral end portion of the drain region has a straight portion and an arc portion facing the source region,
One end of the source region on the substrate contact region side has a plurality of concave portions arranged along the extending direction of the gate electrode,
The other end portion of the source region on the gate electrode side is spaced apart from the plurality of concave portions and is formed linearly and continuously along the extending direction of the gate electrode,
The substrate contact region has a plurality of facing regions arranged along the extending direction of the gate electrode and facing the plurality of concave portions,
The plurality of opposed regions are respectively disposed in the plurality of concave portions.   2. The semiconductor device according to claim 1, wherein the one end portion of the source region extends in a direction parallel to an extending direction of the gate electrode between adjacent concave portions of the plurality of concave portions. A semiconductor device having a linear end.   3. The semiconductor device according to claim 1, wherein the plurality of opposed regions of the substrate contact region and the plurality of concave portions of the source region are joined to each other in a lateral direction parallel to the main surface. A semiconductor device characterized by comprising: The semiconductor device according to claim 3,
Each of the plurality of concave portions has a linear side end extending in a direction parallel to the lateral direction and perpendicular to the extending direction of the gate electrode,
Each of the plurality of opposed regions has a linear opposed end extending in a direction parallel to the extending direction of the side ends,
The semiconductor device, wherein the side end and the opposite end are joined to each other.   3. The semiconductor device according to claim 1, wherein the substrate contact region and the one end of the source region are separated from each other in a lateral direction parallel to the main surface. . A semiconductor device according to any one of claims 1 to 5,
Before SL substrate contact region is a semiconductor device characterized by being formed so as to surround the source region. A semiconductor device according to any one of claims 1 to 6 ,
An insulating film formed near the main surface of the semiconductor substrate and interposed between the gate electrode and the drain region;
One end of the gate electrode extends from the gate insulating film to the insulating film.

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