JP5975669B2 - Semiconductor wafer jig and method for handling semiconductor wafer - Google Patents

Description

  The present invention relates to a semiconductor wafer jig used in a semiconductor manufacturing process and a semiconductor wafer handling method.

  In order to adapt a conventional semiconductor wafer to a thin semiconductor package (not shown) in the back grinding process, the back surface is back grinded and adhesively supported on the adhesive tape of the carry jig in the dicing process, and then the individual semiconductor chips are separated by a dicing blade. By separating, a large number of semiconductor chips are formed (see Patent Documents 1, 2, 3, and 4). In the semiconductor wafer back grinding process, the semiconductor wafer is thinly cut to a thickness of 100 μm or less, sometimes about 30 to 50 μm, with a rotating grindstone. There is a risk of coming.

  In view of this, in the past, (1) when a semiconductor wafer is back-ground, the inner region is back-ground while leaving the peripheral edge of the semiconductor wafer, and the remaining peripheral edge ensures the rigidity of the semiconductor wafer and bends. (2) A method for tightly attaching a rigidity securing ring to the peripheral edge of a semiconductor wafer and imparting rigidity to the semiconductor wafer by this rigidity securing ring to suppress and prevent bending has been proposed (see Patent Document 5). ).

JP 2009-260219 A JP 2009-164476 A JP 2005-191039 A Japanese Patent No. 4239974 JP 2011-159864 A

  However, when the method (1) is adopted, the strength of the semiconductor wafer can be improved and the warpage can be reduced. There will be a new problem that equipment and costs cannot be reduced. In the case of the method (2), although the problem (1) can be solved and it is very convenient, the rigidity securing ring is manufactured with an emphasis on imparting rigidity. It is unexpectedly difficult to remove the rigid securing ring in the close contact state from the part, and there may be a situation in which the work is delayed or complicated.

  The present invention has been made in view of the above, and can improve the rigidity of a semiconductor wafer, reduce manufacturing equipment and costs, and can be easily removed from the peripheral edge of a semiconductor wafer. And it aims at providing the handling method of a semiconductor wafer.

In the present invention, in order to solve the above-mentioned problem, rigidity is imparted to a thin semiconductor wafer having a thickness of 100 μm or less which is back-ground ,
A flat ring-shaped base layer facing the peripheral surface of one surface of the semiconductor wafer, and a weak adhesive layer provided on the opposing surface of the base material layer so as to adhere to the peripheral surface of the semiconductor wafer in a peelable manner. An adhesive layer is laminated on most of the opposing surfaces of the base material layer, and this adhesive layer is made of an adhesive whose peel strength decreases at about 60 ° C., and the arithmetic surface roughness Ra of the adhesive surface is 0.5 to 5 μm. The remaining portion other than the majority of the opposing surface of the base material layer is a peeling trigger portion having no adhesiveness.

In addition, a peeling opportunity part can be dividedly formed between the opposing surface remaining part of a base material layer, and the edge part of an adhesion layer.
Moreover, an adhesion layer can be formed in a substantially C shape, and the both ends of this adhesion layer can be made to oppose through the remainder of an opposing surface.

Moreover, an adhesive layer can be divided | segmented into plurality and the both ends of these some adhesive layers can also be made to oppose through the remainder of an opposing surface .

Further, in the present invention, in order to solve the above-mentioned problems, the adhesive layer of the semiconductor wafer jig described in claim 1 is detachably adhered to one side periphery of a thin semiconductor wafer having a thickness of 100 μm or less which is back-ground. The semiconductor wafer handling method for peeling the semiconductor wafer jig after performing a predetermined treatment on the semiconductor wafer,
The semiconductor wafer jig is peeled off from the peeling trigger part of the semiconductor wafer jig.

  Here, the semiconductor wafer in the claims is not particularly limited to the φ150, 200, 300, 450 mm type or the like. One side of the semiconductor wafer may be the front surface or the back surface of the semiconductor wafer. The base material layer and the adhesive layer may have the same thickness or width, or may have different thicknesses and widths. The base material layer and the adhesive layer may be formed integrally or separately.

The base material layer is mainly formed in a ring shape, but when a flat orientation flat is formed on the peripheral edge of the semiconductor wafer, the base material layer is formed in a shape along the peripheral edge of the semiconductor wafer. This base material layer does not specifically ask the presence or absence of transparency, opaqueness, translucency, coloring, and flexibility. The adhesive layer and the peeling trigger part do not ask a plurality . Furthermore, the predetermined processing applied to the semiconductor wafer corresponds to at least stress relief, PVD, CVD, back grinding, dicing, and the like.

  According to the present invention, when it is desired to peel off the semiconductor wafer jig, the peeling means interferes with the peeling trigger part of the semiconductor wafer jig that does not have adhesiveness, and the adhesive layer is pulled from one side of the semiconductor wafer. If peeled off, the semiconductor wafer jig can be peeled off and removed.

According to the present invention, there is an effect that the rigidity of a back-ground thin semiconductor wafer having a thickness of 100 μm or less can be improved and manufacturing equipment and cost can be reduced. Also, the semiconductor wafer jig is not fixed to the peripheral edge of one side of the semiconductor wafer with an adhesive so that it cannot be peeled off. Instead, the semiconductor wafer is attached to the semiconductor wafer using a weak adhesive layer. Accurate alignment is possible by stacking jigs and finely adjusting the position by repeatedly attaching and detaching them manually. Moreover, since the operation | work which apply | coats an adhesive agent is not required, there is little incurring the delay and complexity of an operation | work. Further, the semiconductor wafer jig can be reused without being discarded for each operation. As described above, the semiconductor wafer jig can be easily removed from the peripheral edge of the semiconductor wafer , thereby simplifying and speeding up the operation.
Moreover, since the adhesive layer is made of an adhesive whose peel strength decreases at about 60 ° C., the semiconductor wafer jig can be easily removed. Furthermore, since the arithmetic surface roughness Ra of the adhesive surface of the adhesive layer is in the range of 0.5 to 5 [mu] m, it is expected that the positioning operation with respect to the semiconductor wafer is facilitated and reliable adhesion is expected.

It is a section explanatory view showing typically an embodiment of a semiconductor wafer jig and a semiconductor wafer handling method concerning the present invention. It is a perspective explanatory view showing typically the relation between the semiconductor wafer and the semiconductor wafer jig in the embodiment of the semiconductor wafer jig according to the present invention. It is front explanatory drawing which shows typically the relationship between the semiconductor wafer and semiconductor wafer jig | tool in embodiment of the jig | tool for semiconductor wafers concerning this invention. It is back surface explanatory drawing which shows typically embodiment of the jig | tool for semiconductor wafers which concerns on this invention. It is back surface explanatory drawing which shows typically 2nd Embodiment of the jig | tool for semiconductor wafers which concerns on this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. A semiconductor wafer jig in the present embodiment includes a base material layer 10 facing a thin semiconductor wafer 1 as shown in FIGS. The adhesive layer 15 laminated on the facing surface 12 of the base material layer 10 and sticking to the peripheral edge of the back surface of the semiconductor wafer 1 is provided in a two-layer structure, and the adhesive layer 15 is provided on most of the facing surface 12 of the base material layer 10. The remaining portions 13 other than most of the facing surface 12 are formed on the non-adhesive peeling trigger portion 16.

  As shown in FIGS. 1 to 3, the semiconductor wafer 1 is made of, for example, a planar circular silicon wafer having a diameter of 200 mm, a circuit pattern is formed on the surface, and the back surface is back-ground by a general-purpose back-grinding device (not shown). Thus, the thickness is reduced to 100 μm or less. In this semiconductor wafer 1, a circuit pattern is formed on the back-grinded back surface as necessary, and a substantially semi-circular notch 2 for facilitating discrimination and alignment of the crystal direction is cut out at the periphery.

  As shown in FIGS. 3 and 4, the base material layer 10 and the adhesive layer 15 of the semiconductor wafer jig are formed to have the same width, for example. When it is desired to facilitate the work of peeling the semiconductor wafer jig, the width of the base material layer 10 is formed to be slightly wider than the width of the adhesive layer 15.

  As shown in FIGS. 1 to 4, the base material layer 10 is formed in a thin flat ring shape with a predetermined material, and a plurality of fixing holes 11 for positioning and fixing the semiconductor wafer 1 at the time of processing are formed at predetermined intervals in the circumferential direction. It is perforated and faces the peripheral edge of the back surface of the semiconductor wafer 1. The material of the base material layer 10 is not particularly limited. For example, silicon, glass epoxy resin or glass cloth composite, carbon fiber reinforced plastic, liquid crystal polymer, polyether ether ketone, polyether imide, polyimide, Examples include metals (aluminum, SUS, tungsten, iron-nickel alloys (42 alloy, etc.)), other alloys, and the like.

  The base material layer 10 is formed to have the same diameter as the semiconductor wafer 1 or a slightly larger diameter. When the base layer 10 has the same diameter as the semiconductor wafer 1, the outer peripheral edge is aligned with the peripheral edge of the semiconductor wafer 1, and when the diameter is slightly larger than the semiconductor wafer 1, the outer peripheral edge is The semiconductor wafer 1 is close to the outer edge within 3 mm from the peripheral edge. When the base material layer 10 is formed to have a diameter slightly larger than that of the semiconductor wafer 1, a positioning jig or the like of a handling device (not shown) directly contacts the edge of the thin semiconductor wafer 1 to cause chipping or cracking. It can be effectively suppressed.

  As shown in FIGS. 1, 3, and 4, the adhesive layer 15 is formed in a thin planar substantially C shape having a thickness of 200 μm or less (for example, about 100 μm) with a predetermined material having weak adhesiveness. Is laminated and adhered to the flat facing surface 12 of the base material layer 10 facing the back surface periphery of the semiconductor wafer 1, and removably adheres to the back surface periphery of the semiconductor wafer 1.

  The material of the pressure-sensitive adhesive layer 15 is not particularly limited, and examples thereof include pressure-sensitive adhesives such as silicone rubber and fluorine rubber, which have a peel strength that is reduced at about 60 ° C. and is excellent in heat resistance. The adhesive surface that adheres to the peripheral edge of the back surface of the semiconductor wafer 1 of the adhesive layer 15 can be roughly formed by a transfer method using a mold, addition of a filler, or the like, if necessary.

  The average surface roughness (arithmetic surface roughness) Ra of the adhesive surface is preferably in the range of 0.5 to 5 [mu] m in order to facilitate the positioning operation with respect to the semiconductor wafer 1 and ensure reliable adhesion. Such a pressure-sensitive adhesive layer 15 is laminated and adhered to most of the facing surface 12 of the base material layer 10, and both end portions face each other through a gap 13, in other words, the remaining portion 13 other than most of the facing surface 12.

  As shown in FIG. 3 and FIG. 4, the peeling trigger part 16 is defined as a gap between the remaining part 13 of the facing surface 12 and both ends of the adhesive layer 15, and is a semiconductor wafer jig adhered from the semiconductor wafer 1. It becomes a trigger when peeling. In the peeling trigger part 16, the fixing hole 11 of the base material layer 10 is selectively positioned as a working mark.

  In the above-described configuration, when the back-ground thin semiconductor wafer 1 having a thickness of 100 μm or less is subjected to dicing processing by giving rigidity, first, the back surface of the back-ground thin semiconductor wafer 1 is used as the upper surface, and this semiconductor wafer A pressure-sensitive adhesive layer 15 of a semiconductor wafer jig is pressed by a roller or the like on the periphery of the back surface of 1 to be detachably adhered without any gap (see FIG. 2). At this time, the outer peripheral edge of the semiconductor wafer jig can be positioned on the peripheral edge of the semiconductor wafer 1, and the peeling trigger part 16 of the semiconductor wafer jig can be opposed to the notch 2 of the semiconductor wafer 1.

  Next, the semiconductor wafer 1 having increased strength is adhered to the adhesive tape 21 of the carrier jig 20, and the carrier jig 20 is vacuum-adsorbed onto the chuck table 22 (see FIG. 1). If the carrier jig 20 is vacuum-sucked on the chuck table 22 with a vacuum pump, the semiconductor wafer 1 may be damaged if the semiconductor wafer 1 is subjected to a dicing process (see FIG. 1) with a dicing blade 23 that rotates at high speed from the back side. Therefore, a large number of semiconductor chips can be easily obtained.

  When it is desired to peel the semiconductor wafer jig from the back surface peripheral portion of the semiconductor wafer 1, if the fingertip or the like is locked to the peeling trigger portion 16 of the semiconductor wafer jig and pulled up, the back surface peripheral portion of the semiconductor wafer 1 is removed. The adhesive layer 15 is gradually peeled off, and the semiconductor wafer jig can be removed. At this time, if the characteristic of the adhesive layer 15 whose peel strength is reduced at about 60 ° C. is used, the semiconductor wafer jig can be easily removed.

  According to the above configuration, the strength of the semiconductor wafer 1 can be increased by adhering the semiconductor wafer jig along the peripheral portion of the back-ground thin semiconductor wafer 1. In addition, it is possible to effectively suppress and prevent bending and facilitate the subsequent handling and conveyance.

  Therefore, it is not necessary to back grind the inner region while leaving the peripheral portion of the semiconductor wafer 1, and a dedicated device can be reliably omitted, so that significant reduction in manufacturing equipment and cost can be expected. In addition, since there is no adhesive layer 15 that interferes with interference such as a fingertip, and only a gap that facilitates catching of the fingertip or the like exists in the peeling trigger part 16, the semiconductor in close contact with the peripheral edge of the semiconductor wafer 1 The wafer jig can be easily and safely removed, and the risk of work delays and complications can be eliminated. This effect is very significant when the semiconductor wafer 1 and the semiconductor wafer jig have the same diameter.

  In addition, since the semiconductor wafer jig is not fixed to the peripheral edge of the back surface of the semiconductor wafer 1 with an adhesive so as not to be peeled off, the adhesive is detachably attached using the weak adhesive layer 15. Accurate alignment is possible by stacking semiconductor wafer jigs and finely adjusting the position by repeatedly attaching and detaching them manually. In addition, since no work for applying the adhesive is required, the work is not delayed or complicated. Furthermore, it is possible to reuse the semiconductor wafer jig without discarding it for each operation.

Next, FIG. 5 shows a second embodiment of the present invention. In this case, the adhesive layer 15 is divided into two parts, and each adhesive layer 15 is curved and formed into a planar semicircular arc shape. The pressure-sensitive adhesive layer 15 is abutted via a gap, and the gap between the remaining portion 13 of the facing surface 12 and both ends of the pair of pressure-sensitive adhesive layers 15 is defined as a peeling trigger portion 16.
A notch 17 serving as a mark at the time of peeling is selectively cut out at the inner peripheral edge of at least one peeling trigger part 16 of the pair of peeling trigger parts 16, that is, the inner peripheral edge of the remaining part 13. The other parts are substantially the same as those in the above embodiment, and thus description thereof is omitted.

  Also in this embodiment, the same effect as the above embodiment can be expected, and since there are a plurality of peeling trigger parts 16, inconvenience associated with the number of peeling trigger parts 16 can be eliminated, and the semiconductor wafer jig It is clear that the peeling work can be facilitated. Further, the presence of the notch 17 makes it possible to clearly grasp where the peeling trigger part 16 is.

  In the above embodiment, the adhesive layer 15 of the semiconductor wafer jig is adhered to the peripheral edge of the back surface of the semiconductor wafer 1, but the adhesive layer 15 of the semiconductor wafer jig is adhered to the peripheral edge of the semiconductor wafer 1, and the semiconductor A circuit pattern or the like may be formed on the back surface of the wafer 1. Alternatively, the adhesive layer 15 of the semiconductor wafer jig may be adhered to the peripheral edge of the back surface of the semiconductor wafer 1, and then the semiconductor wafer jig may be peeled off and adhered to the peripheral edge of the surface of the semiconductor wafer 1 again.

  Further, the adhesive layer 15 is divided into a plurality of parts (for example, divided into three parts, four parts, etc.), and the plurality of adhesive layers 15 are abutted via gaps, and the gaps between the plurality of adhesive layers 15 are respectively used as peeling trigger parts 16. Also good. In addition, the adhesive layer 15 is laminated and adhered to the entire surface including the remaining portion 13 of the facing surface 12 of the base material layer 10, and a predetermined treatment (for example, surface is applied to the exposed adhesive surface of the facing portion of the adhesive layer 15 facing the remaining portion 13). By performing a roughening process, a UV process, or the like, a non-adhesive peeling trigger part 16 can be formed to facilitate removal of the semiconductor wafer jig.

  Further, the surface of the remaining portion 13 of the base material layer 10 can be colored to facilitate visual grasping of the peeling trigger portion 16. Furthermore, in the above-described embodiment, the fingertip or the like is locked to the peeling trigger part 16 of the semiconductor wafer jig, but the peeling trigger part 16 is automatically lifted by being sandwiched from the outside by a pair of thin holding plates, or the peeling trigger part. It is also possible to automatically pull up a long and narrow holding plate 16 from the outside.

  The semiconductor wafer jig and the semiconductor wafer handling method according to the present invention can be used in the field of semiconductor manufacturing.

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 10 Base material layer 12 Opposing surface 13 Remaining part 15 Adhesive layer 16 Peeling trigger part 17 Notch

Claims (2)

A semiconductor wafer jig for imparting rigidity to a thin semiconductor wafer having a thickness of 100 μm or less which is back-ground ,
A flat ring-shaped base layer facing the peripheral surface of one surface of the semiconductor wafer, and a weak adhesive layer provided on the opposing surface of the base material layer so as to adhere to the peripheral surface of the semiconductor wafer in a peelable manner. An adhesive layer is laminated on most of the opposing surfaces of the base material layer, and this adhesive layer is made of an adhesive whose peel strength decreases at about 60 ° C., and the arithmetic surface roughness Ra of the adhesive surface is 0.5 to 5 μm. A semiconductor wafer jig, characterized in that the remaining portion other than most of the facing surface of the base material layer is a peeling trigger portion having no adhesiveness. The adhesive layer of the semiconductor wafer jig according to claim 1 is releasably adhered to one side periphery of a thin semiconductor wafer having a thickness of 100 μm or less that is back-ground , and the semiconductor wafer is subjected to a predetermined treatment, and then the semiconductor A method for handling a semiconductor wafer for peeling a wafer jig,
A semiconductor wafer handling method, comprising: peeling a semiconductor wafer jig from a peeling trigger part of the semiconductor wafer jig.

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