JP5987628B2 - Semiconductor device - Google Patents

Description

  The technology disclosed in the present application relates to a semiconductor device that performs analog signal input and digital signal output using a common terminal, and relates to improving the accuracy of a signal level when an analog signal is input to the common terminal. is there.

  One-chip microcomputers incorporating an AD converter include one in which an analog signal input terminal for the AD converter is also used as an input terminal for a digital signal (for example, Patent Document 1).

  In some cases, the analog input terminal of the AD converter is also used as a digital input / output terminal (Non-Patent Document 1, etc.).

JP-A-5-2653

Fujitsu Microelectronics, "F2MC (registered trademark) -16LX 16-bit microcontroller MB90990 Series hardware manual", pages 12-13, [online], June 2009, [searched August 16, 2012], Internet <URL: http: //edevice.fujitsu.com/jp/manual/MANUALp/ja-pdf/CM44-10149-4.pdf>

  In a semiconductor device such as a microcontroller that also uses terminals for both analog signals and digital signals, signals that are not input / output when switching between analog signal input and digital signal output using a common terminal It is necessary to cut off the propagation of. For this reason, it is conceivable to provide an analog switch in a signal path from a common terminal to an analog signal processing circuit such as an AD converter. When outputting a digital signal, the analog switch is turned off to cut off the signal path between the common terminal and the analog signal processing circuit. When an analog signal is input, the analog switch is turned on, and the buffer circuit that outputs the digital signal is turned off to cut off the output of the digital signal.

  One example of the use of such a semiconductor device is in-vehicle use. In a vehicle-mounted application or other electronic control application, an analog signal from an external sensor may be input. In this case, the installation position of the semiconductor device such as the in-vehicle microcomputer is not necessarily close to the installation position of the sensor or the like. When the distance between the two is long, a resistance component may be included in the signal path through which the analog signal propagates. Further, depending on the system specifications, a high resistance component may be inserted into the signal path. Furthermore, in order to ensure the robustness and reliability of the system required for in-vehicle applications, etc., there is a case where propagation of an analog signal is required even in a situation such as a contact failure of a connection part on a signal path. Even in the case of such poor contact, a high resistance component is inserted into the signal path.

  Here, consider a case where a minute voltage signal is input as an analog signal. In this case, if a resistance component is included in the signal path, a voltage drop occurs when a current flows in the signal path, and the signal level deviates from a normal voltage value. In particular, if the resistance component included in the signal path is large, a voltage drop of a level that cannot be ignored compared to the voltage level of the analog signal may occur even if a minute current flows. It is also conceivable that the level is greatly shifted. Therefore, depending on the voltage level and voltage range of the input analog signal and the magnitude of the resistance component included in the signal path, there is a possibility that a leakage current in the transistor of the buffer circuit that is turned off becomes a problem. This is because a leakage current when the transistors constituting the buffer circuit are turned off flows through a signal path through which an analog signal is input.

  For this reason, attempts have been made to reduce the leakage current when the transistors constituting the buffer circuit are turned off. However, when the voltage level of the analog signal is very small, the leakage current can be reduced to a level that does not hinder the accuracy of the analog signal depending on the size of the resistance component included in the signal path. It can be difficult.

  Further, the magnitude of the leakage current at the off time increases as the potential difference between the source and drain terminals of the transistor in the off state increases. In the transistor constituting the buffer circuit, the source terminal is connected to the power supply voltage and the drain terminal is connected to the common terminal. Therefore, when the voltage level of the input analog signal is low, the potential difference between the source and drain terminals is This may increase the leakage current. If the voltage level of the analog signal is a very small voltage level, it may become more difficult to reduce the leakage current, and the accuracy of the analog signal may not be ensured depending on the resistance component included in the signal path. It is.

  The technology disclosed in the present application has been proposed in view of the above problems, and in a semiconductor device that performs switching between input of an analog signal and input / output of a digital signal with a common terminal, when an analog signal is input, Semiconductor that can reduce the error of the input analog signal by reducing the leakage current when the transistor is off by reducing the potential difference between the source and drain of the transistor in the buffer circuit that suppresses the output of the digital signal An object is to provide an apparatus.

  A semiconductor device according to a technique disclosed in the present application is a semiconductor device that performs input of an analog signal and input / output of a digital signal through an input / output terminal. A PMOS transistor and a regulator circuit are provided. The PMOS transistor is supplied with a high level voltage at its source terminal and connected at its drain terminal to the input / output terminal, and is turned off when an analog signal is inputted, and turned on when a first logic value of a digital signal is outputted. When the analog signal is input, the regulator circuit supplies a high level voltage having a voltage level corresponding to the voltage level of the analog signal to the source terminal of the PMOS transistor.

  In the semiconductor device according to the technique disclosed in the present application, the high-level voltage supplied to the source terminal of the PMOS transistor that outputs the first logic value of the digital signal corresponds to the voltage level of the analog signal when the analog signal is input. Control the voltage level. Thereby, the potential difference between the source and drain terminals of the PMOS transistor in the off state is kept small. In the PMOS transistor that is controlled to be in the off state, the voltage between the source and drain terminals is kept small, so that leakage current at the time of off can be suppressed. When an analog signal is input, a leak current flowing through the input / output terminal can be reduced, and even when there is a resistance component in the signal path of the analog signal, a deviation in the voltage level of the analog signal can be suppressed. The voltage accuracy of the analog signal can be ensured.

It is a schematic diagram which shows an application example. It is a block diagram of the microcontroller of a 1st embodiment. It is a block diagram of the microcontroller of a 2nd embodiment.

  FIG. 1 is a diagram schematically illustrating an application example in a case where the technology disclosed in the present application is applied to an in-vehicle controller. In the vehicle VE, the microcontroller 1 that performs various controls related to traveling is installed, for example, near the driver's seat. Here, various controls related to running include control around the foot such as an anti-lock brake system and an active suspension system. For the control around the foot, it is necessary to grasp the status of the components and system that constitute the foot around such as a tire and a suspension. For this reason, a sensor for detecting information related to these situations is required, and such information must be acquired around a tire, a suspension, or the like. The sensor SEN is necessarily installed in the vicinity of a tire, a suspension, or the like.

  For this reason, the sense signal (analog signal) from the sensor SEN installed around the foot must propagate through a long signal path SP to the microcontroller 1 installed near the driver's seat. In this case, the signal path SP may be wired by being connected with a connector (not shown) from the path length of the signal path SP and further due to structural restrictions of the vehicle VE. There may be a path resistance RSP that is a wiring resistance on the path. If the sense signal output from the sensor SEN is a voltage signal, the voltage level of the sense signal (analog signal) may deviate from the original value if there is a voltage drop due to current flowing through the path resistor RSP. It is done.

  Further, when the voltage value of the sense signal (analog signal) output from the sensor SEN is small, the voltage range is a small voltage width, or the path resistance RSP has a large resistance value, the current flowing through the signal path SP. Even if the current is a minute current such as a leak current, the deviation of the voltage value of the sense signal (analog signal) becomes large.

  In recent years, microcontrollers 1 have been required to be small in size, and there are cases where both digital input / output terminals and analog input terminals are used due to restrictions on the number of terminals (described later in FIGS. 2 and 3).

  In the embodiment described below, when a sense signal (analog signal) from the sensor SEN is input to a common terminal that is also used, a technique for suppressing leakage current from an input / output circuit of a digital signal that is turned off Will be described. This is a technique for preventing a deviation from the original value of the sense signal due to an unexpected current flowing through the signal path SP and a voltage drop caused by the path resistance RSP.

  FIG. 2 is a circuit block diagram of the first embodiment according to the present application. It is a figure shown centering on the part required for embodiment of this application, and it abbreviate | omits about another structure.

  The microcontroller 1 includes a common terminal T1 as a terminal for inputting a sense signal from the sensor SEN and outputting a digital signal. A PMOS transistor P1 and an NMOS transistor N1 are connected in series between the high-level power supply line 11 and the ground voltage so as to constitute an output buffer for outputting a digital signal, and a connection node between the PMOS transistor P1 and the NMOS transistor N1 Are connected to a common terminal T1. Further, an analog switch X1 in which a PMOS transistor and an NMOS transistor are connected in parallel in order to switch between closing and opening of a signal path to the A / D converter 13 that converts an input sense signal (analog signal) into a digital signal. Are connected to a common terminal T1.

  The functional circuit F is a circuit that performs signal processing for performing various control functions controlled by the microcontroller 1. Although detailed description about these controls is omitted, these are various controls related to the vehicle VE. It also includes control around the foot such as an anti-lock brake system and active suspension system.

  In addition to the function circuit F, control including various functions including the A / D converter 13 and the D / A converter 17 is performed. Here, the A / D converter 13 converts the sensation signal SEN (analog signal) input from the common terminal T1 into a digital signal and supplies the digital signal to the functional circuit F. The D / A converter 17 converts the digital signal calculated by the functional circuit F into an analog signal.

  In the first embodiment, the leakage current when the PMOS transistor P1 constituting the digital signal output buffer is turned off is suppressed. The configuration having this function is the signal path switching control unit 3, the voltage detection circuit 5, and the regulator circuit 7.

  The signal path switching control unit 3 has a function of switching the connection of the signal path with the common terminal T1 based on the signal from the functional circuit F. In the case of outputting a digital signal, a signal for turning off each transistor of the analog switch X1 is outputted toward the gate terminal, and the PMOS transistor P1 and the NMOS transistor N1 constituting the digital signal output buffer are turned on / off. The signal to be controlled is output to the gate terminal. The on-control of the PMOS transistor P1 and the NMOS transistor N1 according to the digital signal is performed based on the signal from the functional circuit F. Further, when inputting a sensation signal (analog signal), the PMOS transistor P1 and the NMOS transistor N1 are turned off, and a signal for turning on each transistor of the analog switch X1 is output.

  The voltage detection circuit 5 includes an A / D converter 13, a digital voltage dividing circuit 15, and a D / A converter 17. Here, the A / D converter 13 and the D / A converter 17 are circuits provided in advance for performing signal processing related to various controls including the functional circuit F. Usually, since it is used for signal processing related to various controls, when a signal is exchanged with the functional circuit F, the voltage detection circuit 5 is configured according to the command signal S from the functional circuit F.

  The input terminal of the A / D converter 13 is connected to the common terminal T1 via the analog switch X1. The output terminal is connected to the digital voltage dividing circuit 15. The output terminal of the digital voltage dividing circuit 15 is connected to the input terminal of the D / A converter 17, and the output terminal of the D / A converter 17 is input to an error amplifier 19 of the regulator circuit 7 described later.

  The connection between the A / D converter 13 and the digital voltage dividing circuit 15 is intermittently performed according to the command signal S. The command signal S is a signal generated by the functional circuit F, and is a signal generated intermittently during idle time during the signal processing operation by the functional circuit F.

  The D / A converter 17 also intermittently converts the output signal from the digital voltage dividing circuit 15 into an analog voltage divided signal in response to the command signal S. The converted analog voltage-divided signal is held in a holding circuit (not shown) until the next command signal S is input, and is output to the regulator circuit 7.

  The regulator circuit 7 includes voltage dividing resistors R1 and R2, a power supply transistor P2, and an error amplifier 19.

  The power feeding transistor P2 and the voltage dividing resistors R1 and R2 are connected in series in this order between the power supply voltage VCC and the ground voltage. The gate terminal of the power supply transistor P2 is connected to the output terminal of the error amplifier 19. The input terminal of the error amplifier 19 is connected to the output terminal of the D / A converter 17 and the connection point of the voltage dividing resistors R1 and R2.

  Next, an operation when a sense signal (analog signal) is input will be described. When the functional circuit F recognizes that it is a sense signal (analog signal) input mode, the signal path switching control unit 3 controls the gate terminals of the PMOS transistor P1 and the NMOS transistor N1 to keep them both in the off state, The gate terminal of the MOS transistor constituting the analog switch X1 is controlled to keep the analog switch X1 in the on state. Thus, the common terminal T1 is connected to the A / D converter 13.

  The sense signal (analog signal) input from the common terminal T1 is converted into a digital signal by the A / D converter 13. At a normal timing, the converted digital signal is input to the functional circuit F and used for signal processing for various controls. When the command signal S is intermittently issued from the functional circuit F, the converted digital signal is output to the digital voltage dividing circuit 15.

  The digital voltage dividing circuit 15 performs digital calculation so that when the input digital signal is converted into an analog voltage value, the voltage dividing ratio is the same as the voltage dividing ratio divided by the voltage dividing resistors R1 and R2. Outputs a partial pressure signal. For example, if the voltage division ratio is 1/2, the digital voltage dividing circuit 15 is realized by shifting the bit string constituting the digital signal by 1 bit to the lower side. Similarly, other voltage division ratios can be obtained by performing digital calculation.

  The digital voltage dividing signal output from the digital voltage dividing circuit 15 is input to the D / A converter 17 and converted into an analog voltage dividing signal. The converted analog voltage dividing signal is a voltage signal obtained by dividing the sense signal (analog signal) by the same ratio as the voltage dividing ratio of the voltage dividing resistors R1 and R2. It is held in a holding circuit (not shown). The holding circuit is a circuit using a capacitor or the like, for example. It is held until the next command signal S is issued and updated by the newly output analog voltage dividing signal.

  The analog voltage-divided signal output and held from the D / A converter 17 is input to one input terminal of the error amplifier 19. A high level voltage (voltage supplied to the high level power supply line 11) divided by the voltage dividing resistors R1 and R2 is input to the other input terminal of the error amplifier 19.

  The error amplifier 19 controls the gate terminal of the power supply transistor P <b> 2 according to the difference between the voltage values input to both input terminals, and controls the voltage value of the high level voltage supplied to the high level power supply line 11. Specifically, control is performed so that the voltage divided by the voltage dividing resistors R1 and R2 approaches the analog divided signal output from the D / A converter 17 and the difference voltage between the two is eliminated. Since the voltage dividing ratio by the digital voltage dividing circuit 15 and the voltage dividing ratio by the voltage dividing resistors R1 and R2 are the same, as a result, the high level voltage supplied to the high level power supply line 11 is sensed to be input to the common terminal T1. The voltage level of the signal (analog signal) is controlled to be the same.

  Thereby, the potential difference between the source and drain terminals of the PMOS transistor P1 becomes a substantially small voltage, and the leakage current flowing between the source and drain terminals of the PMOS transistor P1 in the off state can be substantially eliminated. Since the leakage current is eliminated, the voltage drop between the common terminal T1 and the sensor SEN is substantially eliminated regardless of the path resistance RSP included in the signal path SP connected to the common terminal T1. The sense signal (analog signal) can be input with high accuracy without causing a deviation in the voltage level of the sense signal (analog signal).

  When the functional circuit F recognizes that it is a digital signal output mode, the signal path switching control unit 3 controls the gate terminal of the MOS transistor that constitutes the analog switch X1 to maintain the analog switch X1 in the OFF state. At the same time, based on the control from the function circuit F, the gate terminals of the PMOS transistor P1 and the NMOS transistor N1 are controlled to output digital signals. In this case, the power supply transistor P2 needs to be kept on. A switching circuit (not shown) that switches the input to the D / A converter 17 to the power supply voltage VCC instead of the digital voltage dividing circuit 15, or a ground voltage that connects the gate terminal of the power supply transistor P2 to the error amplifier 19 (not shown). This can be done by providing a switching circuit. As a result, the power supply voltage VCC or a voltage close to the power supply voltage VCC is supplied to the high-level power supply line 11, and the common terminal T1 can be driven to a sufficiently high voltage level by turning on the PMOS transistor P1.

  FIG. 3 is a circuit block diagram of the second embodiment according to the present application. It is a figure shown centering on the part required for embodiment of this application, and it abbreviate | omits about another structure.

  The microcontroller 1A of the second embodiment controls the high level voltage by directly monitoring the sense signal (analog signal) input to the common terminal T1. Unlike the microcontroller 1 of the first embodiment, the analog switch X1 and the high-level power supply line 11 are directly connected to the input terminal of the error amplifier 19.

  As a result, the error amplifier 19 is constantly input with the high level voltage supplied to the high level power supply line 11 and the voltage level of the sense signal (analog signal) input via the analog switch X1. The voltage level of the sense signal (analog signal) can be controlled.

  In the second embodiment, since the sense signal (analog signal) input to the common terminal T1 is always input, the A / D converter 13 provided in advance for performing the control including the functional circuit F, There is no need to divert the D / A converter 17, and the voltage level of the sense signal (analog signal) can be directly input to the error amplifier 19.

  When outputting a digital signal, it is only necessary to have a circuit configuration similar to that of the first embodiment.

  Here, in the first embodiment, the microcontroller 1 is an example of a semiconductor device. The voltage dividing ratio by the voltage dividing resistors R1 and R2 is an example of a specified voltage dividing ratio. An analog voltage division signal output from the D / A converter 17 is an example of a detection voltage. In addition, a difference voltage from an analog divided signal output from the D / A converter 17 of a voltage divided by the voltage dividing resistors R1 and R2 is an example of an error voltage. The A / D converter 13 is an example of an AD conversion circuit, and the D / A converter 17 is an example of a DA conversion circuit.

  In the second embodiment, the microcontroller 1A is an example of a semiconductor device. A sense signal (analog signal) input via the analog switch X1 is an example of a detection voltage. Further, the difference voltage from the sense signal (analog signal) of the high level voltage of the high level power supply line 11 is an example of the error voltage.

  As described above in detail, according to the embodiment disclosed in the present application, a high level voltage fed to the source terminal of the PMOS transistor P1 that outputs a digital signal is supplied to the sense signal input from the common terminal T1. Since the voltage level is substantially the same as the voltage level of (analog signal), there is no potential difference between the source and drain terminals of the PMOS transistor. Thereby, the leakage current when the PMOS transistor P1 is in the off state can be suppressed. Since the leakage current is suppressed, a voltage drop due to the current flowing through the signal path SP flowing through the path resistance RSP included in the path does not occur, and the voltage level of the sense signal (analog signal) is very small. Even so, the voltage level does not shift due to the voltage drop, and the sense signal (analog signal) can be input with high accuracy in the signal path SP including the resistance component.

  Furthermore, according to the first embodiment, the A / D converter 13 and the D / A converter 17 used for signal processing for performing various controls in cooperation with the functional circuit F can be diverted and incorporated. Can be used effectively. The A / D converter 13 and the D / A converter 17 are intermittently acquired by using the idle time during which signal processing for performing various controls is not performed. Since the operation is intermittent, current consumption due to circuit operation can be suppressed.

  Further, according to the second embodiment, the high level voltage can be controlled to the sense signal (analog signal) that is always input to the common terminal T1. Regardless of the time variation of the voltage level of the sense signal (analog signal), the high level voltage supplied to the source terminal of the PMOS transistor P1 is always applied to the drain terminal of the PMOS transistor P1. It can be kept equal to the voltage level. Even when the voltage level of the sense signal (analog signal) changes sharply, the leakage current when the PMOS transistor P1 is off can be suppressed.

Needless to say, the technology disclosed in the present application is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the spirit of the present invention.
For example, in the present embodiment, the common terminal T1 is described as a terminal that serves both as an analog signal input terminal and a digital signal output terminal, but the present application is not limited thereto. It can also be used as an input / output terminal for digital signals. Further, the present invention can also be applied to a case where an analog signal input / output terminal that serves both as an input and an output of an analog signal suppresses a leakage current when the analog signal output buffer is turned off.

The shared terminal may be shared by a plurality of input, output and input / output circuits. For example, when the output of multiple digital signals is shared by a common terminal, even if the high level voltage supplied to the source terminal of the PMOS transistor that constitutes the digital signal output buffer is individually different, the analog signal The high level voltage of each PMOS transistor may be controlled in the same manner as in the present application.
When a plurality of analog signal inputs are shared by a common terminal, the high level voltage supplied to the source terminal of the PMOS transistor that constitutes the digital signal output buffer is controlled according to the input analog signal. good.

DESCRIPTION OF SYMBOLS 1, 1A Microcontroller 3 Signal path switching control part 5 Voltage detection circuit 7 Regulator circuit 11 High level power supply line 13 A / D converter 15 Digital voltage dividing circuit 17 D / A converter 19 Error amplifier F Functional circuit N1 NMOS transistor P1 PMOS transistor P2 Power supply transistor R1, R2 Voltage dividing resistor RSP Path resistance S Command signal SEN Sensor SP Signal path VCC Power supply voltage VE Vehicle X1 Analog switch

Claims (6)

A semiconductor device that performs input of analog signals and input / output of digital signals via input / output terminals,
A PMOS transistor having a high level voltage supplied to a source terminal, a drain terminal connected to the input / output terminal, turned off when the analog signal is input, and turned on when the first logic value of the digital signal is output;
A semiconductor device comprising: a regulator circuit that supplies the high-level voltage having a voltage level corresponding to the voltage level of the analog signal to the source terminal of the PMOS transistor when the analog signal is input. A voltage detection circuit that detects a voltage level of the analog signal input to the input / output terminal and outputs a detection voltage obtained by dividing the voltage level by a specified voltage dividing ratio;
The regulator circuit is:
A voltage dividing resistor provided between a source terminal of the PMOS transistor and a ground voltage, and outputting a divided voltage obtained by dividing the high level voltage by the specified voltage dividing ratio;
A power supply transistor that is interposed between a power supply voltage and a source terminal of the PMOS transistor and supplies the high-level voltage to the source terminal of the PMOS transistor;
2. The semiconductor device according to claim 1, further comprising an error amplifier that controls a conduction state of the power supply transistor in accordance with an input of the divided voltage and the detection voltage when the analog signal is input. The voltage detection circuit includes:
An AD conversion circuit for converting the voltage level of the analog signal into a digital value;
A digital voltage dividing circuit for converting the digital value into a digital divided value obtained by dividing the digital value by the specified voltage dividing ratio;
The semiconductor device according to claim 2, further comprising a DA conversion circuit that converts the digital voltage-divided value into the detection voltage. At least one of the AD conversion circuit and the DA conversion circuit is a circuit mounted for the semiconductor device to perform signal processing,
The voltage detection circuit detects a voltage level of the analog signal according to the AD conversion circuit and the DA conversion circuit during a period when the AD conversion circuit and the DA conversion circuit are not operating for the signal processing. The semiconductor device according to claim 3, wherein the detection voltage is output.   The voltage detection circuit detects a voltage level of the analog signal input to the input / output terminal every intermittent time, and holds the detection voltage according to the detected voltage level. Item 5. The semiconductor device according to any one of Items 2 to 4. The regulator circuit is:
A power supply transistor that is interposed between a power supply voltage and a source terminal of the PMOS transistor and supplies the high-level voltage to the source terminal of the PMOS transistor;
2. The semiconductor device according to claim 1, further comprising: an error amplifier that controls a conduction state of the power supply transistor in accordance with an input of the high-level voltage and the analog signal when the analog signal is input.

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