JP5995698B2 - Thin film transistor and manufacturing method thereof, crystalline oxide semiconductor thin film and manufacturing method thereof, display device, and X-ray sensor - Google Patents

Description

  The present invention relates to a thin film transistor and a manufacturing method thereof, a crystalline oxide semiconductor thin film and a manufacturing method thereof, a display device, and an X-ray sensor.

In recent years, a thin film transistor using an In—Ga—Zn—O-based (hereinafter sometimes abbreviated as InGaZnO) oxide semiconductor film containing In, Ga, Zn, and O as a channel layer (active layer) is used. : TFT) is actively researched and developed. The oxide semiconductor film can be formed at a low temperature, has higher mobility than amorphous silicon, and is transparent to visible light. Therefore, a flexible transparent thin film transistor is formed on a substrate such as a plastic plate or film. Is possible.
Here, Table 1 shows a comparison table of mobility of various transistor characteristics, process temperature, and the like.

Thin film transistors using polysilicon for the channel layer can achieve mobility of about 100 cm ² / Vs, but the process temperature is very high at 450 ° C or higher, so it can only be formed on substrates with high heat resistance such as glass. This is not possible and is not suitable for low cost, large area, and flexibility.
A thin film transistor using amorphous silicon for the channel layer can be formed at a relatively low temperature of about 300 ° C., so that the substrate selectivity is wider than that of polysilicon, but only a mobility of about 1 cm ² / Vs can be obtained. It is not suitable for high-definition display applications.
On the other hand, from the viewpoint of low-temperature film formation, thin film transistors using organic semiconductors for the channel layer can be formed at 100 degrees or less, and therefore are expected to be applied to flexible display applications using plastic film substrates with low heat resistance. However, the mobility is only as high as that of amorphous silicon.

  In oxide semiconductor systems such as InGaZnO, high mobility can be obtained even in an amorphous state, but on the other hand, it is described that the oxide semiconductor has been crystallized in order to further improve mobility and stability of characteristics. There are also some documents (see Patent Document 1 and Non-Patent Document 1).

Japanese Patent No. 4164562

K. Nomura et al., “Amorphous Oxide Semiconductors for High-Performance Flexible Thin-Film Transistors” Japanese Journal of Applied Physics, Vol. 45 4303-4308 2006

  For example, when a crystallization process is introduced as a process for improving semiconductor characteristics (mobility and stability of characteristics against time and drive stress), Patent Document 1 and Non-Patent Document 1 describe a very high process temperature (600 ° C. Above). In addition, when aiming to realize an epitaxial film having lattice matching with the substrate as in Patent Document 1, a more complicated process such as film formation of the initial layer and stepping of the substrate is required.

The present invention relates to a method for producing an electrically stable crystalline oxide semiconductor film in which an amorphous oxide semiconductor such as amorphous (amorphous) InGaZnO (hereinafter sometimes referred to as a-InGaZnO) is crystallized at a low temperature. Another object of the present invention is to provide a method for manufacturing a thin film transistor in which an amorphous oxide semiconductor is crystallized at a low temperature and has an electrically stable active layer.
It is another object of the present invention to provide an electrically stable thin film transistor, a display device, and an X-ray sensor that can be manufactured at a low temperature.

In order to achieve the above object, the following invention is provided.
<1> forming a gate electrode;
Forming a gate insulating film;
Forming an amorphous oxide semiconductor layer containing at least one element selected from In, Ga, Zn, and Sn;
A voltage is applied to the amorphous oxide semiconductor layer to increase the current density to 6.7 × 10 ⁻⁴ A / cm ² or more to crystallize at least a part of the amorphous oxide semiconductor layer , and then post-annealing is performed. forming an active layer Te,
Forming a source electrode and a drain electrode;
A method of manufacturing a thin film transistor including:
<2> The method for producing a thin film transistor according to <1>, wherein the amorphous oxide semiconductor layer contains at least one element selected from In, Ga, and Zn.
<3> The method for producing a thin film transistor according to <2>, wherein the amorphous oxide semiconductor layer contains In, Ga, and Zn.
<4> The active layer includes a crystal phase having a composition represented by (In _1-x Ga _x ) ₂ O ₃ (ZnO) _m (where 0 ≦ x ≦ 1, m is 1 or more and 5 or less) <1 The manufacturing method of the thin-film transistor in any one of>-<3>.
<5> The method for producing a thin film transistor according to any one of <1> to <3>, wherein the active layer includes a crystal phase having a composition represented by InGaO ₃ (ZnO) _m (where m is 1 or more and 5 or less). .
< 6 > When a voltage is applied to the amorphous oxide semiconductor layer, the amorphous oxide semiconductor layer is crystallized while controlling the temperature of the amorphous oxide semiconductor layer to be a room temperature or more and a crystallization temperature or less. <1> to <5> The manufacturing method of the thin-film transistor in any one.
< 7 > When a voltage is applied to the amorphous oxide semiconductor layer, the amorphous oxide semiconductor layer is crystallized while controlling the temperature of the amorphous oxide semiconductor layer between room temperature and 250 ° C. Any one of <1> to <5> A method for producing the thin film transistor according to claim 1.
< 8 > After the step of forming the source electrode and the drain electrode, any one of <1> to <7>, wherein a voltage is applied between the source electrode and the drain electrode to crystallize at least a part of the amorphous oxide semiconductor layer A method for producing the thin film transistor according to claim 1.
< 9 > A crystalline oxide semiconductor including a crystal phase having a composition represented by InGaO ₃ (ZnO) _m (where m is 1 or more and 3 or less) and having a layered crystal phase and a grain-like crystal phase A crystalline oxide semiconductor film, wherein the grain-like crystal has a size exceeding 10 nm .
< 10 > forming an amorphous oxide semiconductor film containing at least one element selected from In, Ga, Zn, and Sn;
A voltage is applied to the amorphous oxide semiconductor film so that the current density is 6.7 × 10 ⁻⁴ A / cm ² or more to crystallize at least a part of the amorphous oxide semiconductor film , and then post-annealing is performed. Process,
A method for producing a crystalline oxide semiconductor film containing
< 11 > A thin film transistor comprising the crystalline oxide semiconductor film according to < 9 > as an active layer.
< 12 > A display device comprising the thin film transistor according to < 11 >.
< 13 > X-ray sensor provided with the thin-film transistor as described in < 11 >.

According to the present invention, an amorphous oxide semiconductor such as a-InGaZnO is crystallized at a low temperature, and a method for producing an electrically stable crystalline oxide semiconductor film and an amorphous oxide semiconductor are crystallized at a low temperature. A method of manufacturing a thin film transistor having a stable active layer is provided.
In addition, according to the present invention, an electrically stable thin film transistor, a display device, and an X-ray sensor that can be manufactured at a low temperature are provided.

It is sectional drawing which shows typically four structures about the thin-film transistor which can be manufactured by this invention. It is a figure which shows an example of the process of manufacturing a thin-film transistor in the manufacturing process of an electronic device. It is a figure which shows an example of the process after manufacturing a thin-film transistor in the manufacturing process of an electronic device. It is a schematic sectional drawing which shows a part of liquid crystal display device of embodiment. It is a schematic block diagram of the electrical wiring of the liquid crystal display device of FIG. It is a schematic sectional drawing which shows a part of organic EL display apparatus of embodiment. It is a schematic block diagram of the electrical wiring of the organic electroluminescent display apparatus of FIG. It is a schematic sectional drawing which shows a part of X-ray sensor array of embodiment. It is a schematic block diagram of the electrical wiring of the X-ray sensor array of FIG. It is a schematic diagram of the sample produced in the voltage application experiment. It is a figure which shows the application method of the pulse current in an Example. It is a figure which shows the relationship between voltage application time and a voltage value. 4 is a TEM image showing the cross section of the voltage application region of the oxide semiconductor layer in Example 1 with a different magnification. 6 is a TEM image showing a cross section of a voltage application region of an oxide semiconductor layer in Example 2. FIG. 6 is a TEM image showing a cross section of an oxide semiconductor layer in Comparative Example 1. FIG. 4 is a diagram showing an electron diffraction pattern of an oxide semiconductor layer in Example 3. FIG. 7 is a diagram illustrating an electron diffraction pattern of an oxide semiconductor layer in Comparative Example 2. FIG. It is a cross-sectional TEM image at the time of crystallizing InGaZnO amorphous oxide semiconductor by annealing.

  Hereinafter, the present invention will be specifically described with reference to the accompanying drawings. In the drawings, members (components) having the same or corresponding functions are denoted by the same reference numerals, and description thereof is omitted as appropriate. Moreover, in the following description, the range represented using “to” represents a range including both upper and lower limit numerical values.

  A method of manufacturing a thin film transistor (TFT) according to the present invention includes a step of forming a gate electrode, a step of forming a gate insulating film, and an amorphous oxide semiconductor containing at least one element selected from In, Ga, Zn, and Sn. Forming an active layer obtained by crystallizing at least a part of the amorphous oxide semiconductor layer by applying a voltage to the amorphous oxide semiconductor layer, and forming a source electrode and a drain electrode. And.

Usually, high-temperature annealing is required to crystallize the amorphous oxide semiconductor as described above. However, in the present invention, electrical energy is applied to the amorphous oxide semiconductor, not thermal energy. Causes crystallization. Although there is a possibility that electrical energy is locally changed to thermal energy by Joule heat, in principle, it is possible to crystallize an amorphous oxide semiconductor even when the substrate temperature is room temperature.
Hereinafter, a method for manufacturing a thin film transistor according to the present invention will be described together with the structure of the thin film transistor.

  First, the element structure of a TFT manufactured according to the present invention will be described. The TFT manufactured according to the present invention may be either a so-called bottom gate type (also referred to as an inverted staggered structure) or a top gate type (also referred to as a staggered structure) based on the position of the gate electrode. The top gate type is a form in which a gate electrode is disposed on the upper side of the gate insulating film and an active layer is formed on the lower side of the gate insulating film when the substrate on which the TFT is formed is the lowermost layer. The bottom gate type is a form in which a gate electrode is disposed below the gate insulating film and an active layer is formed above the gate insulating film.

Further, based on the contact portion between the active layer and the source and drain electrodes (referred to as “source / drain electrodes” as appropriate), either a so-called top contact type or bottom contact type may be used. The bottom contact type is a mode in which the source / drain electrodes are formed before the active layer and the lower surface of the active layer is in contact with the source / drain electrodes. The top contact type is a mode in which the active layer is more than the source / drain electrodes. In this embodiment, the upper surface of the active layer is in contact with the source / drain electrodes.
In addition to the above, the TFT according to the present invention can have various configurations, and may appropriately have a configuration including a protective layer on the active layer and an insulating layer on the substrate.

1A to 1D are cross-sectional views schematically showing the configuration of thin film transistors according to first to fourth embodiments of the present invention. In each thin-film transistor 1, 2, 3, and 4 of FIG. 1 (A)-(D), the same code | symbol is attached | subjected to the common element.
The thin film transistors 1, 2, 3, and 4 according to the embodiment of the present invention all have an oxide semiconductor layer (active layer) 12, a source electrode 13, a drain electrode 14, and a gate insulating film 15 on a substrate 11. And a gate electrode 16.

The thin film transistor 1 of the first embodiment shown in FIG. 1A is a top gate-top contact type transistor, and the thin film transistor 2 of the second embodiment shown in FIG. 1B is a top gate-bottom contact. The thin film transistor 3 of the third embodiment shown in FIG. 1C is a bottom gate-top contact type transistor, and the thin film transistor 4 of the fourth embodiment shown in FIG. A bottom-gate / bottom-contact transistor.
In the embodiment shown in FIGS. 1A to 1D, the arrangement of the gate electrode 16, the source electrode 13, and the drain electrode 14 with respect to the oxide semiconductor layer 12 is different, but the function of each element given the same reference numeral Are the same and similar materials can be applied. Hereinafter, each component and manufacturing process will be described in detail with reference to the TFT 1 shown in FIG.

(substrate)
There is no restriction | limiting in particular about the shape of the board | substrate 11 for forming the thin-film transistor 1, a structure, a magnitude | size, It can select suitably according to the objective.
The structure of the substrate 11 may be a single layer structure or a laminated structure.
As the substrate 11, a substrate made of glass, an inorganic material such as YSZ (Yttria-Stabilized Zirconia), a resin, a resin composite material, or the like can be used. Among these, a substrate made of a resin or a resin composite material is preferable in terms of light weight and flexibility. Specifically, polybutylene terephthalate, polyethylene terephthalate, polyethylene naphthalate, polybutylene naphthalate, polystyrene, polycarbonate, polysulfone, polyethersulfone, polyarylate, allyl diglycol carbonate, polyamide, polyimide, polyamideimide, polyetherimide, Fluorine resin such as polybenzazole, polyphenylene sulfide, polycycloolefin, norbornene resin, polychlorotrifluoroethylene, liquid crystal polymer, acrylic resin, epoxy resin, silicone resin, ionomer resin, cyanate resin, crosslinked fumaric acid diester, cyclic polyolefin, Substrates made of synthetic resins such as aromatic ethers, maleimide-olefins, cellulose, episulfide compounds, A substrate composed of a composite plastic material of the above-mentioned synthetic resin and the like and silicon oxide particles, a substrate composed of a composite plastic material of the above-described synthetic resin and the like and metal nanoparticles, inorganic oxide nanoparticles or inorganic nitride nanoparticles, A substrate made of a composite plastic material of the aforementioned synthetic resin, etc. and carbon fiber or carbon nanotube, a substrate made of a composite plastic material of the aforementioned synthetic resin, etc., and glass fake, glass fiber or glass bead, the aforementioned synthesis A substrate made of a composite plastic material of a resin or the like and particles having a clay mineral or a mica-derived crystal structure, a laminated plastic substrate having at least one bonding interface between a thin glass and any of the aforementioned synthetic resins, inorganic By alternately laminating layers and organic layers (the aforementioned synthetic resins), at least one contact Insulating the surface by subjecting a substrate made of a composite material having a barrier property having an interface, a stainless steel substrate, a metal multilayer substrate in which stainless steel and a dissimilar metal are laminated, an aluminum substrate or a surface to an oxidation treatment (for example, anodization treatment). An aluminum substrate with an improved oxide film can be used.

  The resin substrate is preferably excellent in heat resistance, dimensional stability, solvent resistance, electrical insulation, workability, low air permeability, and low moisture absorption. The resin substrate may include a gas barrier layer for preventing permeation of moisture and oxygen, an undercoat layer for improving the flatness of the resin substrate and adhesion with the lower electrode, and the like.

  The thickness of the substrate 11 is preferably 50 μm or more and 500 μm or less. When the thickness of the substrate 11 is 50 μm or more, the flatness of the substrate itself is further improved. When the thickness of the substrate 11 is 500 μm or less, the flexibility of the substrate itself is further improved and the use as a substrate for a flexible device becomes easier. Since the thickness having sufficient flatness and flexibility differs depending on the material constituting the substrate 11, it is necessary to set the thickness according to the substrate material, but the range is generally in the range of 50 μm to 500 μm. .

In the case of using a single crystal substrate (ZnO, YSZ, etc.) that can be lattice-matched with an InGaZnO-based amorphous oxide semiconductor, an epitaxial film in which the amorphous oxide semiconductor and the substrate crystal plane are aligned at the substrate interface can be expected.
On the other hand, since the crystallization process of the present invention can be applied at room temperature in principle, it is generally flexible when using a flexible resin that easily exhibits thermal expansion / contraction even at about 200 ° C. A thin film transistor and an electronic device including the thin film transistor can be manufactured.

(Active layer)
The active layer 12 is composed of a crystalline oxide semiconductor film containing at least one element selected from In, Ga, Zn, and Sn. The active layer 12 includes a step of forming an amorphous oxide semiconductor layer containing at least one element selected from In, Ga, Zn, and Sn, and an amorphous oxide semiconductor layer by applying a voltage to the amorphous oxide semiconductor layer. And an active layer obtained by crystallizing at least a part of the active layer. Hereinafter, each process for producing the active layer 12 will be described in detail.

-Amorphous oxide semiconductor layer formation process-
First, an amorphous oxide semiconductor film containing at least one element selected from In, Ga, Zn, and Sn is formed over the substrate 11. The amorphous oxide semiconductor film preferably includes at least one of In, Ga, and Zn, more preferably includes In, Ga, and Zn, and further includes an oxide semiconductor film that is crystallized by a crystallization process that will be described later. It is desirable that the (active layer) includes a crystal phase having a composition represented by (In _1-x Ga _x ) ₂ O ₃ (ZnO) _m (where 0 ≦ x ≦ 1, m is 1 or more and 5 or less), In particular, it is desirable that the crystal phase has a composition represented by InGaO ₃ (ZnO) _m and that m is 1 or more and 5 or less. According to the experiments by the present inventors, there is a situation in which a smaller value of _{m in} the composition of InGaO ₃ (ZnO) _m tends to be crystallized, and a particularly good crystal phase is obtained at m = 1. 1 is more preferable. If m is 5 or less, crystallization is easy with a large grain size, and if m is 1, a particularly good crystal phase can be obtained.
In addition, in the InGaZnO system, the higher the In content, the easier it is to obtain high mobility as a semiconductor film. Therefore, from the viewpoint of mobility, m is preferably 5 or less.

  In the case where the amorphous oxide semiconductor film contains Zn, light irradiation stability accompanying an increase in the optical band gap can be imparted by doping part of Zn with element ions having a wider band gap. Specifically, the band gap of the film can be increased by doping Mg.

  For example, a blue light emitting layer used in an organic EL (organic electroluminescence) element exhibits a broad light emission having a peak at a wavelength of λ = 450 nm, so that the optical band gap of the InGaZnO film is relatively narrow, and there is no optical in that region. In the case of absorption, there arises a problem that the threshold shift of the transistor occurs. Therefore, it is preferable that the material used for the active layer (channel layer) has a larger band gap, particularly for a thin film transistor used for driving an organic EL.

  The carrier density of the oxide semiconductor layer can be arbitrarily controlled by cation doping. In order to increase the carrier density, a material (Ti, Zr, Hf, Ta, etc.) that tends to be a cation having a relatively large valence may be doped. However, when doping a cation having a large valence, the number of constituent elements of the oxide semiconductor film increases, which is disadvantageous in terms of simplifying the film formation process and reducing the cost. ) To control the carrier density.

As a method for forming an amorphous oxide semiconductor film, a printing method, a wet method such as a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a chemical method such as CVD or a plasma CVD method, etc. The film may be formed according to a method appropriately selected in consideration of suitability with the material to be used. Note that the sputtering method is preferable from the viewpoint of forming a film at a low temperature.
The film thickness (total film thickness) of the amorphous oxide semiconductor film to be the active layer 12 is preferably about 10 nm to 200 nm.

  After forming the amorphous oxide semiconductor film, the amorphous oxide semiconductor film is patterned into the shape of the active layer 12. Patterning can be performed by photolithography and etching. Specifically, a resist pattern is formed on the remaining portion by photolithography, and a pattern that becomes the active layer 12 is formed by etching with an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, or a mixed solution of phosphoric acid, nitric acid, and acetic acid. Form.

-Crystallization process-
After forming an amorphous oxide semiconductor layer containing at least one element selected from In, Ga, Zn, and Sn, a voltage is applied to the amorphous oxide semiconductor layer to form at least a part of the amorphous oxide semiconductor layer. Crystallize.

  A method for applying a voltage to the amorphous oxide semiconductor layer is not particularly limited as long as at least a part of the amorphous oxide semiconductor can be crystallized. For example, a voltage may be applied through the electrode in a state where an electrode connected to the amorphous oxide semiconductor layer is formed, or a voltage may be applied by directly contacting the amorphous oxide semiconductor layer with an end needle or the like. You may do it.

The step of crystallizing by applying a voltage to the amorphous oxide semiconductor layer may be performed at any stage after the step of forming the amorphous oxide semiconductor layer. Such a signal may be applied to the oxide semiconductor layer to cause crystallization, or an electrical signal may be applied after forming the source / drain electrodes. A voltage can be applied between the source and drain electrodes to crystallize the amorphous oxide semiconductor layer.
As a method for giving an electrical signal, a voltage may be applied constantly, or a signal modulated in time, such as a pulse, may be sent.

In the crystallization step, the current density when a voltage is applied to the amorphous oxide semiconductor layer is desirably 6.7 × 10 ⁻⁴ A / cm ² or more. This is because energy is high and a larger current is more likely to cause crystallization. However, the current density when a voltage is applied to the amorphous oxide semiconductor layer is 1 × from the viewpoint of preventing excessive heat generation due to Joule heat and deterioration of characteristics of the active layer due to large current (due to generation of lattice defects, traps, etc.). It is desirable that it is 10 ⁻¹ A / cm ² or less.

In addition, when a voltage is applied to the amorphous oxide semiconductor layer, it is desirable to crystallize the active layer while controlling the temperature of the amorphous oxide semiconductor layer between room temperature (20 ° C.) and a crystallization temperature or less. It is further desirable to control the temperature of the physical semiconductor layer between room temperature and 250 ° C. For example, in the case of an InGaZnO-based amorphous oxide semiconductor layer, the crystallization temperature is about 600 ° C.
By controlling the temperature of the amorphous oxide semiconductor layer, the electrical conductivity of the oxide semiconductor layer can be changed. For example, if electric conductivity higher than electric conductivity at room temperature is given (if the electric resistance is lowered), it becomes easier to apply a voltage. When the temperature is 250 ° C. or lower, the amorphous oxide semiconductor layer can be crystallized even on a substrate that requires a low-temperature process such as a flexible substrate.

For example, in the case of an oxide semiconductor film such as InGaZnO, by controlling the temperature of the oxide semiconductor film from room temperature to 250 ° C., moisture in the film is desorbed and deep deep gap levels are reduced. The resistance value is greatly reduced by an order of magnitude. An effect of increasing the resistance value is seen at a temperature exceeding 250 ° C., and converges to a certain resistance value at 300 ° C. or higher. Therefore, from the viewpoint of controlling electrical conductivity, it is desirable to control the temperature of the oxide semiconductor layer from room temperature to 250 ° C. or less.
In the present invention, heating when applying a voltage to the amorphous oxide semiconductor layer does not cause direct crystallization, but it is presumed to have an effect of promoting crystallization by thermal energy. .

  When applying a voltage to the amorphous oxide semiconductor layer, the temperature control method of the amorphous oxide semiconductor layer is not particularly limited. For example, a technique for controlling the temperature of the entire substrate such as a hot plate may be used. A technique of increasing the temperature from the surface of the amorphous oxide semiconductor layer by heating, radiation, or the like may be used.

The active layer 12 is a crystalline oxide semiconductor film containing at least one element of In, Ga, Zn, and Sn formed as a result of the crystallization process described above, and has different crystal phases in the active layer 12. It preferably has a layered crystal phase and a grain-like (granular) crystal phase.
Whether or not the oxide semiconductor layer is in a crystalline phase or whether or not the oxide semiconductor layer is crystallized in the method for manufacturing a thin film transistor of the present invention can be confirmed by X-ray diffraction measurement. That is, if a clear peak indicating a crystal structure is detected by X-ray diffraction measurement, it can be confirmed that the oxide semiconductor layer is in a crystalline phase.
Further, whether or not different crystal phases are present in the oxide semiconductor layer can be confirmed, for example, by performing cross-sectional TEM measurement. It is also possible to obtain information on the lattice state by acquiring an electron diffraction pattern.

  In the method for manufacturing a thin film transistor according to the present invention, control of the carrier concentration of the oxide semiconductor layer is also important. The carrier concentration of the oxide semiconductor layer can be controlled not only by modulation of the composition of the metal element but also by oxygen partial pressure control during film formation.

  The oxygen concentration can be controlled by controlling the oxygen partial pressure during the formation of the oxide semiconductor film. If the oxygen partial pressure at the time of film formation is increased, the carrier concentration can be reduced, and a reduction in off-current can be expected accordingly. On the other hand, if the oxygen partial pressure during film formation is lowered, the carrier concentration can be increased, and accordingly, the field effect mobility can be expected to increase. Further, for example, by performing treatment with irradiation with oxygen radicals or ozone after the formation of the oxide semiconductor film, the oxidation of the film can be promoted and the amount of oxygen vacancies in the film can be reduced.

  In the thin film transistor manufacturing method of the present invention, a heat treatment step (post-annealing process) may be added separately from the crystallization step of the amorphous oxide semiconductor layer. When the heat treatment temperature is 400 ° C. or higher, the light irradiation stability can be made extremely high. For example, the absolute value of the threshold shift amount for light irradiation of 420 nm | ΔVth | ≦ 0.5 V, and further | ΔVth | ≦ 0.3V can also be achieved.

In the heat treatment step, it is desirable to anneal in a dry atmosphere in which the moisture content contained in the whole atmosphere is −36 ° C. or less (absolute humidity 0.21 g / m ⁻³ or less) in terms of dew point temperature. By performing the annealing in a dry atmosphere, the light stability can be improved as compared with the case of performing the annealing in a humid atmosphere (such as in the air).

(Source / drain electrodes)
The source electrode 13 and the drain electrode 14 are not particularly limited as long as they have high conductivity, and metals such as Al, Mo, Cr, Ta, Ti, Au, and Ag, Al—Nd, tin oxide, zinc oxide, A metal oxide conductive film such as indium oxide, indium tin oxide (ITO), or zinc indium oxide (IZO) can be used as a single layer or a stacked structure of two or more layers.

  Each of the source electrode 13 and the drain electrode 14 includes a printing method, a wet method such as a coating method, a physical method such as a vacuum deposition method, a sputtering method, an ion plating method, a chemical method such as a CVD method and a plasma CVD method. The film may be formed according to a method appropriately selected in consideration of suitability with the material to be used.

  When the source electrode 13 and the drain electrode 14 are made of the above metal, the thickness is preferably set to 10 nm or more and 1000 nm or less in consideration of the film forming property, the patterning property by etching or lift-off method, and the conductivity. 50 nm or more and 100 nm or less is more preferable.

(Gate insulation film)
The gate insulating film 15 disposed between the active layer 12 and the gate electrode 16 is preferably one having high insulating properties, such as SiO ₂ , SiNx, SiON, Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O. ₅ , an insulating film such as HfO _2, or an insulating film containing at least two of these compounds.

  The gate insulating film 15 is a material used from a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method or an ion plating method, or a chemical method such as a CVD or plasma CVD method. The film may be formed according to a method appropriately selected in consideration of the suitability of

  The gate insulating film 15 needs to have a sufficient thickness for reducing the leakage current and improving the voltage resistance. On the other hand, if the thickness is too large, the driving voltage is increased. Although depending on the material, the thickness of the gate insulating film 15 is preferably 10 nm to 10 μm, more preferably 50 nm to 1000 nm, and particularly preferably 100 nm to 400 nm.

(Gate electrode)
The gate electrode 16 is not particularly limited as long as it has high conductivity, and is a metal such as Al, Mo, Cr, Ta, Ti, Au, and Ag, Al—Nd, tin oxide, zinc oxide, indium oxide, and oxide. A metal oxide conductive film such as indium tin (ITO) or zinc indium oxide (IZO) can be used as a single layer or a stacked structure of two or more layers.

  The gate electrode 16 is made of a material used from a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method or an ion plating method, or a chemical method such as a CVD or plasma CVD method. The film may be formed according to a method appropriately selected in consideration of the suitability of the above.

  When the gate electrode 16 is made of the above metal, the thickness is preferably 10 nm or more and 1000 nm or less in consideration of film forming properties, patterning properties by etching or lift-off methods, conductivity, and the like, preferably 50 nm or more, More preferably, it is 200 nm or less.

  Next, an example of a method for manufacturing an electronic device including a bottom gate-top contact type thin film transistor according to the present invention will be described with reference to FIGS. In addition, the constituent material, thickness, etc. of each part are as above-mentioned, and it abbreviate | omits suitably in the following description.

  A substrate 11 is prepared, and after cleaning and drying the substrate 11 (FIG. 2A), a gate electrode 16 is formed. Specifically, after the electrode film 16A is formed (FIG. 2B), it is patterned into a predetermined shape of the gate electrode 16 by etching or a lift-off method (FIG. 2C). At this time, it is preferable to pattern the gate electrode 16 and the gate wiring (not shown) at the same time.

Next, a gate insulating film 15A, an amorphous oxide semiconductor film (a-InGaZnO) 12A, and an etching stopper film 17A are successively formed (FIG. 2D). Here, the etching stopper film 17A is basically an insulating film, and desirably has a low insulating property, water vapor, and oxygen permeability. Specifically, a metal oxide or metal nitride such as SiO ₂ or SiN _x is desirable.

  Thereafter, the etching stopper film 17A is patterned to expose the regions to be the source / drain electrodes on the oxide semiconductor film 12A, and the etch stopper layer 17 is formed so as to cover only the portion directly above the portion to be the channel (FIG. 2 (E)).

  Next, the amorphous oxide semiconductor film 12A is patterned into the shape of the active layer 12 that enables conduction between the source and drain electrodes described later (FIG. 2F). Here, the patterning of the amorphous oxide semiconductor film 12A can be performed by photolithography and etching. Specifically, a resist pattern is formed on the remaining portion by photolithography, and the pattern is formed by etching with an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, or a mixed solution of phosphoric acid, nitric acid and acetic acid.

  Further, the gate insulating film 15A is patterned (FIG. 2G).

  Next, after forming a metal film 18 for forming the source / drain electrodes (FIG. 2H), the metal film 18 is patterned into a predetermined shape by etching or a lift-off method (FIG. 2I). As a result, source / drain electrodes 13 and 14 which can be conducted through the active layer 12 are formed. At this time, it is preferable to pattern the source / drain electrodes 13 and 14 and the wiring connected to these electrodes 13 and 14 simultaneously.

  After forming the source / drain electrodes 13, 14, a channel protective film may be further formed on the etch stopper layer 17.

Thereafter, an interlayer insulating film 20A is formed (FIG. 3A), and the contact hole 19 is formed by patterning the interlayer insulating film 20 (FIG. 3B).
A pixel electrode layer 21A is formed over the interlayer insulating film 20 (FIG. 3C), and the pixel electrode 21 is formed by patterning the pixel electrode layer 21A (FIG. 3D).

  A thin film transistor having an oxide semiconductor as the active layer 12 is finally obtained by post-annealing (FIG. 3E).

  When a thin film transistor is manufactured through the above steps, the voltage application process which is a crystallization process of the oxide semiconductor layer may be performed at any timing after the amorphous oxide semiconductor layer 12 is formed. It is preferable to apply a voltage via the electrodes 13 and 14. After forming the source / drain electrodes (FIG. 2 (I)), a voltage may be applied between the source / drain electrodes, after forming the contact holes (FIG. 3 (B)), after forming the pixel electrodes (FIG. 3 (C)). )), Or after post-annealing (FIG. 3D). In order to make the in-plane characteristics of the TFT array uniform by post-annealing, it is desirable to perform post-annealing after the crystallization process.

The crystallization process of the amorphous oxide semiconductor layer is preferably performed in an atmosphere containing oxygen because the semiconductor layer is an oxide semiconductor. In particular, it is possible to reduce lattice defects in the oxide semiconductor layer without significantly increasing oxygen defects in the oxide semiconductor layer by performing in air, and by partially incorporating moisture in the air into the film. is there.
In addition, by performing the process in the air, it is not necessary to introduce dedicated equipment that requires atmospheric control, and the cost can be reduced.

  In addition, in the case of an oxide semiconductor, the film resistance greatly changes by digits due to moisture desorption in the film accompanying heating. An advantage is that a sufficient current flows for crystallization without turning on the channel region by applying a gate voltage.

Although the use of the thin film transistor manufactured by the present invention is not particularly limited, for example, a drive element in a display device (liquid crystal display device, organic EL (Electro Luminescence) display device, inorganic EL display device, etc.) as an electro-optical device. It is suitable as.
Further, the thin film transistor manufactured according to the present invention includes a device such as a flexible display that can be manufactured by a low temperature process using a resin substrate, an image sensor such as a charge coupled device (CCD) and a complementary metal oxide semiconductor (CMOS), and an X-ray sensor. It is suitably used as a drive element (drive circuit) in various electronic devices such as various sensors such as MEMS (Micro Electro Mechanical System).
Both the display device and the sensor of the present invention using the thin film transistor of the present invention exhibit good characteristics due to low power consumption. The “characteristic” referred to here is a display characteristic in the case of a display device, and a sensitivity characteristic in the case of a sensor.

<Liquid crystal display device>
FIG. 4 shows a schematic sectional view of a part of a liquid crystal display device which is an embodiment of a display device including a thin film transistor manufactured according to the present invention, and FIG. 5 shows a schematic configuration diagram of its electric wiring.

  As shown in FIG. 4, the liquid crystal display device 5 of this embodiment includes a top gate-bottom contact type thin film transistor 1, a pixel lower electrode 55 on a gate electrode 16 protected by a passivation layer 54 of the thin film transistor 1, and a counter electrode thereof. A liquid crystal layer 57 sandwiched between the upper electrodes 56 and an RGB color filter 58 for developing different colors corresponding to each pixel are provided, and polarizing plates 59a and 59b are provided on the substrate 11 side of the TFT 1 and the color filter 58, respectively. It is the structure provided with.

  Further, as shown in FIG. 5, the liquid crystal display device 5 of the present embodiment includes a plurality of gate lines 51 that are parallel to each other and data lines 52 that are parallel to each other and intersect the gate lines 51. Here, the gate wiring 51 and the data wiring 52 are electrically insulated. The thin film transistor 1 is provided in the vicinity of the intersection between the gate line 51 and the data line 52.

  The gate electrode 16 of the thin film transistor 1 is connected to the gate wiring 51, and the source electrode 13 of the thin film transistor 1 is connected to the data wiring 52. The drain electrode 14 of the thin film transistor 1 is electrically connected to the pixel lower electrode 55 through a contact hole 19 provided in the gate insulating film 15 (a conductor is embedded in the contact hole 19). The pixel lower electrode 55 and the grounded counter electrode 56 constitute a capacitor 53.

  In the liquid crystal device of this embodiment shown in FIG. 4, the top gate type thin film transistor 1 is provided. However, the thin film transistor used in the liquid crystal device which is the display device of the present invention is not limited to the top gate type. A bottom-gate thin film transistor may also be used.

Since the thin film transistor manufactured according to the present invention has high mobility, high-definition display such as high definition, high-speed response, and high contrast is possible in a liquid crystal display device, which is suitable for a large screen. In addition, since the active layer (oxide semiconductor layer) 12 crystallized at a low temperature by voltage application has few characteristic shifts, the gate voltage can be reduced and thus the power consumption of the display device can be reduced.
Further, according to the present invention, the amorphous oxide semiconductor layer containing at least one element selected from In, Ga, Zn, and Sn constituting the active layer 12 can be formed at a relatively low temperature. Since it can be crystallized at a low temperature by application, a resin substrate (plastic substrate) can be used as the substrate. Therefore, according to the present invention, it is possible to provide a flexible liquid crystal display device having excellent display quality.

<Organic EL display device>
FIG. 6 shows a schematic sectional view of a part of an active matrix organic EL display device as an embodiment of a display device including a TFT manufactured according to the present invention, and FIG. 7 shows a schematic configuration diagram of electrical wiring. Show.
There are two types of driving methods for organic EL display devices: a simple matrix method and an active matrix method. The simple matrix method has an advantage that it can be manufactured at low cost. However, since the pixels are emitted by selecting one scanning line at a time, the number of scanning lines and the light emission time per scanning line are inversely proportional. Therefore, it is difficult to increase the definition and increase the screen size. The active matrix method has a high manufacturing cost because a transistor and a capacitor are formed for each pixel. However, since there is no problem that the number of scanning lines cannot be increased unlike the simple matrix method, it is suitable for high definition and large screen.

  In the active matrix organic EL display device 6 of the present embodiment, a top gate-top contact type thin film transistor is provided as a driving TFT 1a and a switching TFT 1b on a substrate 60 provided with a passivation layer 61a. On the thin film transistors 1a and 1b, an organic light emitting element 65 comprising an organic light emitting layer 64 sandwiched between a lower electrode 62 and an upper electrode 63 is provided, and the upper surface is also protected by a passivation layer 61b.

  As shown in FIG. 6, the organic EL display device 6 according to the present embodiment includes a plurality of gate lines 66 parallel to each other, and data lines 67 and drive lines 68 that intersect the gate lines 66 and are parallel to each other. ing. Here, the gate wiring 66, the data wiring 67, and the driving wiring 68 are electrically insulated. The gate electrode 16 b of the switching thin film transistor 1 b is connected to the gate line 66, and the source electrode 13 b of the switching thin film transistor 1 b is connected to the data line 67. The drain electrode 14b of the switching thin film transistor 1b is connected to the gate electrode 16a of the driving thin film transistor 1a, and the driving thin film transistor 1a is kept on by using the capacitor 69. The source electrode 13 a of the driving thin film transistor 1 a is connected to the driving wiring 68, and the drain electrode 14 a is connected to the organic EL light emitting element 65.

  The organic EL device of this embodiment shown in FIG. 6 is also provided with the top gate type thin film transistors 1a and 1b. However, the thin film transistor used in the organic EL device which is the display device of the present invention is a top gate type. Without limitation, a bottom-gate thin film transistor may be used.

  Since the thin film transistor manufactured according to the present invention has high mobility, low power consumption and high quality display can be achieved. Further, according to the present invention, the amorphous oxide semiconductor layer containing at least one element selected from In, Ga, Zn, and Sn constituting the active layer can be formed at a relatively low temperature, and voltage application can be performed. Therefore, a resin substrate (plastic substrate) can be used as the substrate. Therefore, according to the present invention, a flexible organic EL display device having excellent display quality can be provided.

  In the organic EL display device shown in FIG. 6, the upper electrode 63 may be a top emission type with a transparent electrode, or the lower electrode 62 and each electrode of the TFTs 1a and 1b may be a transparent electrode. Good.

<X-ray sensor>
FIG. 8 shows a schematic sectional view of a part of an X-ray sensor which is an embodiment of the sensor of the present invention, and FIG. 9 shows a schematic configuration diagram of its electric wiring.
The X-ray sensor 7 of this embodiment includes a thin film transistor 1 and a capacitor 70 formed on a substrate 11, a charge collection electrode 71 formed on the capacitor 70, an X-ray conversion layer 72, and an upper electrode 73. Configured. A passivation film 75 is provided on the thin film transistor 1.

  The capacitor 70 has a structure in which an insulating film 78 is sandwiched between a capacitor lower electrode 76 and a capacitor upper electrode 77. The capacitor upper electrode 77 is connected to one of the source electrode 13 and the drain electrode 14 (the drain electrode 14 in FIG. 8) of the thin film transistor 1 through a contact hole 79 provided in the insulating film 78.

  The charge collection electrode 71 is provided on the capacitor upper electrode 77 in the capacitor 70 and is in contact with the capacitor upper electrode 77. The X-ray conversion layer 72 is a layer made of amorphous selenium and is provided so as to cover the thin film transistor 1 and the capacitor 70. The upper electrode 73 is provided on the X-ray conversion layer 72 and is in contact with the X-ray conversion layer 72.

  As shown in FIG. 9, the X-ray sensor 7 of this embodiment includes a plurality of gate wirings 81 that are parallel to each other and a plurality of data wirings 82 that intersect with the gate wirings 81 and are parallel to each other. Here, the gate wiring 81 and the data wiring 82 are electrically insulated. The thin film transistor 1 is provided in the vicinity of the intersection between the gate wiring 81 and the data wiring 82.

  The gate electrode 16 of the thin film transistor 1 is connected to the gate wiring 81, and the source electrode 13 of the thin film transistor 1 is connected to the data wiring 82. The drain electrode 14 of the thin film transistor 1 is connected to a charge collecting electrode 71, and the charge collecting electrode 71 constitutes a capacitor 70 together with a grounded counter electrode 76.

  In the X-ray sensor 7 of this configuration, X-rays are irradiated from the upper part (upper electrode 73 side) in FIG. 8, and electron-hole pairs are generated in the X-ray conversion layer 72. By applying a high electric field to the X-ray conversion layer 72 by the upper electrode 73, the generated charges are accumulated in the capacitor 70 and read out by sequentially scanning the thin film transistor 1.

Since the X-ray sensor of the present invention includes the thin film transistor 1 having a high on-current and excellent reliability, the S / N is high and the sensitivity characteristic is excellent. Therefore, the X-ray sensor has a wide dynamic when used in an X-ray digital imaging apparatus. A range image is obtained.
In particular, the X-ray digital imaging apparatus of the present invention is suitable not only for still image shooting but also for an X-ray digital imaging apparatus that can perform fluoroscopy with a moving image and still image shooting.

The amorphous oxide semiconductor layer containing at least one element selected from In, Ga, Zn, and Sn constituting the active layer 12 can be formed at a relatively low temperature, and can be crystallized at a low temperature by applying a voltage. Therefore, a flexible X-ray sensor using a resin substrate can be obtained.
In the X-ray sensor of this embodiment shown in FIG. 8, the top gate type thin film transistor is provided. However, the thin film transistor used in the sensor of the present invention is not limited to the top gate type, and the bottom gate type. A thin film transistor may be used.

Examples will be described below, but the present invention is not limited to these examples.
The present inventors have demonstrated that the amorphous oxide semiconductor layer is crystallized by applying a voltage by conducting the following experiment.

<Crystallization by voltage application of oxide semiconductor layer>
A sample (evaluation TFT) having the configuration shown in FIG. 10 was produced by the following process.
An Au electrode having an electrode interval of 500 μm and an electrode width of 1 mm was formed on the single crystal YSZ substrate 111 to form electrodes 113 and 114 for voltage application. An InGaZnO film 112 was formed thereon by sputtering with a thickness of 150 nm. The film formation pressure during sputtering film formation was 0.42 Pa, and the oxygen / argon partial pressure was 0.05 / 30. The composition was In: Ga: Zn = 1: 1: 1 (Example 1) and 1: 1: 5 (Example 2). This corresponds to the case of m = 1 and 5 when InGaZnO when crystallized is described as InGaO ₃ (ZnO) _m .

Next, a constant current was passed through the sample to attempt crystallization. Using Keithley's SMU-237 (source measure unit) as a current source and voltmeter, a pulse current of ± 100 mA (corresponding to a current density of 6.7 × 10 ⁻⁴ A / cm ² ) as shown in FIG. Application was at a pulse interval of 200 ms. The interval between pulses was 1 s.
As described above, the pulse current was measured once every 10 seconds while the voltage was applied, and the change in the state of the oxide semiconductor was detected. The result is shown in FIG. From FIG. 12, in the case of Example 1 (In: Ga: Zn = 1: 1: 1, m = 1), about 2000 s after voltage application, Example 2 (In: Ga: Zn = 1: 1: 5). , M = 5), it can be seen that the inflection point of the voltage value occurs in about 10000 s.

After such a change in voltage value that seems to be a change in the state of the oxide semiconductor layer occurred, the voltage application was stopped and a cross-sectional TEM image was measured. A TEM image of Example 1 is shown in FIG. 13, and a TEM image of Example 2 is shown in FIG.
Further, FIG. 15 shows a cross-sectional TEM image in which the same sample as in Example 1 was prepared and no voltage was applied (Comparative Example 1).

As shown in FIGS. 13 and 14, it can be seen that a clear crystallized region is formed by applying a voltage.
In Examples 1 and 2, a lattice image in which the entire active layer was considered to be crystallized was observed. Since it was observed that the grain size was large and crystallization was more uniform, it was found that a crystallized film with higher uniformity can be obtained when m = 1 with the Zn content decreased. When m = 5, the film contains microcrystals having a smaller crystal grain size. It can also be seen that when m = 1, a layered crystal phase exists on the surface and a grain-shaped crystal phase exists inside.

On the other hand, in Comparative Example 1 in which no current was applied, no lattice image was observed, and it was found to be in an amorphous state.
From the above experiments, it has been clarified that crystallization can be caused without applying thermal energy by applying a current to the amorphous oxide semiconductor film.

  In order to evaluate in detail the crystal state of the films of Example 1 and Comparative Example 1, electron beam diffraction patterns were obtained. The results are shown in FIGS. 16 and 17, respectively. FIG. 16 shows that in Example 1, the surface crystal phase and the relatively uniform crystal phase portion in the central portion are crystals having different lattice spacings. On the other hand, as shown in FIG. 17, in Comparative Example 1, no crystalline diffraction pattern was observed. That is, it has been shown that the film obtained by crystallization by such voltage application is composed of a mixture of different crystal phases such as a surface layer crystal and an inner grain crystal.

<Electrical characteristic evaluation of InGaZnO-TFT in which oxide semiconductor layer is formed by vapor deposition method>
A high-concentration p-type doped Si substrate was prepared as the substrate. The substrate is coated with 100 nm of thermally oxidized SiO _2, and the substrate itself functions as a gate electrode and the thermally oxidized SiO ₂ film functions as a gate insulating film. On top of this, an InGaZnO film having the following metal composition was formed to a thickness of 50 nm by sputtering. The film forming conditions were as follows: film forming pressure 0.4 Pa, argon partial pressure / oxygen partial pressure = 30 / 0.15.
Thereafter, a Ti / Au (10 nm / 40 nm) electrode was formed by a sputtering method through a metal mask. This produced a TFT for evaluation.

After TFT fabrication, Keithley's SMU-237 (source measure unit) is used as a current source and voltmeter, and a pulse current of ± 100 V (corresponding to a current density of 6.7 × 10 ⁻⁴ A / cm ² ) is applied to a pulse of 200 ms. The active layer was crystallized by applying at intervals. The interval between pulses was 1 s.

  Next, a post-annealing treatment was performed under the conditions shown in Table 2 using a muffle furnace for annealing in the atmosphere and an oxygen partial pressure control tubular furnace for annealing in dry oxygen.

  For evaluation of electrical characteristics, a semiconductor parameter analyzer 4156C (manufactured by Agilent Technologies) was used, and transistor characteristics (Vg-Id characteristics) and mobility μ were measured.

  Vg-Id characteristics are measured by fixing the drain voltage (Vd) to 10 V, sweeping the gate voltage (Vg) within the range of -30 V to +30 V, and measuring the drain current (Id) at each gate voltage (Vg). I went to do it.

  Regarding the mobility, the linear mobility was determined from the Vg-Id characteristic in the saturation region measured by sweeping the gate voltage (Vg) in the range of -30V to + 30V with the drain voltage (Vd) fixed at 10V. Calculated.

  Regarding the driving stability, the gate voltage was fixed at 15 V and the drain voltage was fixed at 10 V, and after applying a current driving stress for 1 hour, the transistor characteristics were measured, and the threshold shift amount from the initial characteristics was calculated.

The light stability ΔVth was evaluated by irradiating the TFT with monochromatic light having an intensity of 420 nm and 10 μW / cm ² for 10 minutes, and similarly calculating the threshold shift amount from the initial characteristics.

The above evaluation was performed on the oxide semiconductor in which the Zn composition or post-annealing conditions were changed.
Further, as a comparative example, the same evaluation was performed on a sample that was not crystallized and a sample that was crystallized by annealing.
The evaluation results are shown in Table 2.

First, it can be seen from the comparison between Example 3 and Comparative Example 2 that driving stability can be greatly increased by introducing a crystallization step by voltage application.
Further, from the comparison of Examples 3, 4 and 5, it was observed that the mobility was lowered when m was large (Zn content was large). This is because, in InGaZnO, the main conduction is in the 5s orbital of In, and when m is large, crystal grains with small grain size (less than 10 nm) are generated and grain boundary sites increase, resulting in a decrease in electrical conductivity. It is expected that That is, from the viewpoint of mobility, m is preferably 3 or less .
Further, when the post-annealing temperature is set to 400 ° C. or more as in Examples 6 and 7, the light stability can be improved, and the effect of improving the light stability is in dry oxygen having a relative humidity of 1% or less. Greater if done.
Note that the TFT of Comparative Example 3 crystallized by annealing has good electrical characteristics, but since annealing is performed at 600 ° C., a substrate having low heat resistance such as a resin substrate cannot be used.
When the active layer is crystallized in the InGaZnO system, the crystal phase is expressed as follows.
_{(In 1-x Ga x)} 2 O 3 (ZnO) m
In and Ga are both trivalent in InGaZnO, and the ratio can be changed in the same crystal structure. For example, Examples 8 and 9 correspond to the cases of x = 0.4 and 0.6, respectively, but even in this case, crystallization is caused by current application, and excellent characteristic stability is obtained while having high electric characteristics. You can see that Therefore, if the present invention has a crystal phase according to the above composition formula, high electrical characteristics and good characteristic stability can be realized.

<Evaluation of InZnO-based coated TFT>
A TFT in the case where the active layer was coated InZnO was manufactured by the following method.
First, a high concentration p-type doping Si substrate was prepared as a substrate. The substrate is coated with 100 nm of thermally oxidized SiO _2, and the substrate itself functions as a gate electrode and the thermally oxidized SiO ₂ film functions as a gate insulating film. An oxide semiconductor layer was formed thereon by the following method.

  1.32 g of zinc acetate dihydrate and 5.79 g of indium isopropoxy were weighed and stirred at a temperature of 150 ° C. in 100 mL of diethylethanolamine to prepare a pale yellow metal alkoxide raw material liquid (metal composition when formed into a film). The ratio was In: Zn = 7: 2.

An oxide precursor film having a film thickness of 70 nm is obtained by repeating the process of spin-coating a metal alkoxide raw material solution on a p-type silicon substrate with a thermal oxide film at a rotational speed of 3000 rpm and then naturally drying for 5 minutes twice. Was made.
The obtained oxide precursor film was heat-treated at 450 ° C. for 1 hour in a box furnace. Due to the firing of the oxide precursor film, the final thickness of the oxide semiconductor layer was approximately 50 nm.
Thereafter, Ti / Au (10 nm / 40 nm) was formed into a metal mask using an electron beam vapor deposition apparatus to form source / drain electrodes.
As described above, a bottom-gate thin film transistor having a channel length of 180 μm and a channel width of 1 mm using an InZnO layer formed by a coating method as an active layer was obtained.

  The electrical characteristics and the driving stability were evaluated in Example 10 for the TFT that had been crystallized in the same manner as described above, and in Comparative Example 4 for the TFT that had not been crystallized. The results are shown in Table 3 below.

  As shown in Table 3, also in the case of an InZnO-based TFT, when the active layer is crystallized by applying a voltage, it is understood that the electrical characteristics are superior to those when it is not crystallized.

<Evaluation of crystal state of oxide semiconductor layer crystallized by annealing>
FIG. 18 shows a cross-sectional TEM image when annealing (1000 ° C., 1 hour) is performed on the amorphous InGaZnO layer. In this case, only grain-like polycrystals are formed, and it can be seen that the gap between grains is large.

  On the other hand, in the method of crystallizing an amorphous oxide semiconductor layer by applying a voltage, as shown in FIGS. 13 and 14, a crystalline semiconductor composed of a layered crystal phase and a grained crystal phase is in principle at room temperature. As a result, a dense film having almost no voids between grains is formed. When the method of the present invention is used, current concentrates on the substrate in the horizontal direction in the region having high electrical conductivity in the active layer, so that the region having high electrical conductivity is selectively crystallized in layers (+ It is speculated that other parts of the grain) can be made. There is no clear grain boundary as shown in FIG. 18 in the layered crystallized portion, and it is presumed that if the layered region is the region responsible for the main conduction (even after polycrystallization), high conductive properties can be maintained. The

  In the above description, the case where an In—Ga—Zn—O-based or In—Zn—O-based oxide semiconductor layer is formed is mainly described; however, the present invention is not limited thereto, and In—Ga—O, In— The present invention can also be applied to the case where an oxide semiconductor layer such as Sn—O, In—Sn—Zn—O, In—Ga—Sn—O, or In—O is formed.

1, 2, 3, 4 Thin film transistor 11 Substrate 12 Active layer (oxide semiconductor layer)
13 Source electrode 14 Drain electrode 15 Gate insulating film 16 Gate electrode 17 Etching stopper layer 18 Source / drain electrode film 19 Interlayer insulating film 20 Contact hole 21 Pixel electrode

Claims (13)

Forming a gate electrode;
Forming a gate insulating film;
Forming an amorphous oxide semiconductor layer containing at least one element selected from In, Ga, Zn, and Sn;
A voltage is applied to the amorphous oxide semiconductor layer so that the current density is 6.7 × 10 ⁻⁴ A / cm ² or more to crystallize at least a part of the amorphous oxide semiconductor layer, followed by post-annealing. Performing an active layer to perform ,
Forming a source electrode and a drain electrode;
A method of manufacturing a thin film transistor including:   The method for manufacturing a thin film transistor according to claim 1, wherein the amorphous oxide semiconductor layer contains at least one element selected from In, Ga, and Zn.   The method for manufacturing a thin film transistor according to claim 2, wherein the amorphous oxide semiconductor layer contains In, Ga, and Zn. The active layer includes a crystal phase having a composition represented by (In _1-x Ga _x ) ₂ O ₃ (ZnO) _m (where 0 ≦ x ≦ 1, m is 1 or more and 5 or less). The manufacturing method of the thin-film transistor as described in any one of Claims 3. 4. The method of manufacturing a thin film transistor according to claim 1, wherein the active layer includes a crystal phase having a composition represented by InGaO ₃ (ZnO) _m (where m is 1 or more and 5 or less). 5. .   6. The method according to claim 1, wherein when applying a voltage to the amorphous oxide semiconductor layer, the amorphous oxide semiconductor layer is crystallized while controlling a temperature of the amorphous oxide semiconductor layer to a room temperature to a crystallization temperature. The manufacturing method of the thin-film transistor as described in any one. When a voltage is applied to the amorphous oxide semiconductor layer, any of claims 1 to 5 for crystallizing the amorphous oxide semiconductor layer while controlling the temperature of the amorphous oxide semiconductor layer 250 ° C. or less than room temperature A method for producing the thin film transistor according to claim 1. After the step of forming the source electrode and the drain electrode, one of the claims 1 to 7 for crystallizing at least part of the amorphous oxide semiconductor layer by applying a voltage between the source and drain electrodes A method for producing the thin film transistor according to claim 1. An In GaO ₃ composition represented by _{(ZnO) m} (where, m is 1 to 3) comprises a crystalline phase, met crystalline oxide semiconductor film having a crystal phase of layered, and a grain-like crystalline phase A crystalline oxide semiconductor film in which the grain-like crystal has a size exceeding 10 nm . Forming an amorphous oxide semiconductor film containing at least one element selected from In, Ga, Zn, and Sn;
A voltage is applied to the amorphous oxide semiconductor film so that the current density is 6.7 × 10 ⁻⁴ A / cm ² or more to crystallize at least a part of the amorphous oxide semiconductor film , and then post-annealing is performed. A process of performing
A method for producing a crystalline oxide semiconductor film containing A thin film transistor comprising the crystalline oxide semiconductor film according to claim 9 as an active layer. A display device comprising the thin film transistor according to claim 11 . An X-ray sensor comprising the thin film transistor according to claim 11 .