JP5998908B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which a semiconductor device is mounted on a metal base.

  As a conventional semiconductor device, for example, one disclosed in Patent Document 1 is known. This semiconductor device includes a field effect transistor as a semiconductor device, and a lead frame is connected to the electrode. A spiral coil portion having a spiral coil shape is provided between the gate electrode and the lead frame, and the lead frame is connected to the gate electrode via the spiral coil portion and a bonding wire. In such a semiconductor device, the spiral coil portion has a high reactance particularly with respect to high-frequency noise, and as a result, propagation of noise to the field effect transistor is hindered.

  As a conventional semiconductor device, a semiconductor device and a lead frame connected to the semiconductor device are mounted on a metal base with an insulator mainly for the purpose of ensuring rigidity and heat dissipation. Yes.

Japanese Patent No. 3130809

  In the semiconductor device in which the semiconductor device is mounted on the metal base described above, it was discovered that there is noise that enters the semiconductor device from the metal base in addition to the noise that directly enters the semiconductor device from its terminal via the lead frame. . Specifically, semiconductor devices of semiconductor devices, signal wiring, power supply wiring, etc. are usually provided on a metal base via an insulator, but in reality, when a high voltage is generated due to, for example, electrostatic discharge In addition, current may enter the semiconductor device as noise via the parasitic capacitance between each wiring and the metal base, the metal base, and the parasitic capacitance between the metal base and the semiconductor device. In addition, external noise such as electromagnetic noise from the outside of the semiconductor device may enter the metal base and enter the semiconductor device via the metal base and parasitic capacitance.

  On the other hand, in the semiconductor device according to the above-mentioned patent document, the noise that tries to enter directly from the terminal of the semiconductor device is attenuated by the spiral coil portion provided in the lead frame, but the semiconductor device is provided on the metal base. In this case, since it is defenseless against noise entering from the metal base side, the noise entering from the metal base side may cause a malfunction such as malfunction in the semiconductor device.

  The present invention has been made in order to solve the above-described problems. In a semiconductor device in which a semiconductor device is provided on a metal base, it is more resistant to noise from the base side. An object of the present invention is to provide a semiconductor device that operates stably.

In order to achieve the above object, a semiconductor device according to claim 1 includes a metal base, an insulator provided on the base, and a semiconductor device mounted on the base via the insulator. A semiconductor device comprising the base and an external connection terminal provided on the base in a state of being insulated from the base, from the base via a parasitic capacitance between the base and the semiconductor device An impedance structure portion that is attached to the base portion between the base portion and the semiconductor device so as to be positioned in an intrusion path of noise that enters the semiconductor device, and exhibits high impedance to the noise , and the impedance structure The portion has at least one first coil for preventing the noise from entering the semiconductor device, Also one end, characterized in that it is surrounded by the insulator.

  According to this semiconductor device, the impedance structure portion is provided that exhibits high impedance against noise that tends to enter a semiconductor device mounted on a metal base portion via an insulator. The impedance structure portion is attached to the base portion between the base portion and the semiconductor device, and is located in a base and a noise intrusion path that enters through the parasitic capacitance between the base portion and the semiconductor device. This prevents noise from entering the semiconductor device from the base portion from entering the semiconductor device. Therefore, problems such as malfunction of the semiconductor device due to noise entering from the base side can be suppressed, and a semiconductor device having better noise resistance can be obtained.

  A semiconductor device according to a second aspect is the semiconductor device according to the first aspect, wherein a housing portion for housing the impedance structure portion is formed in the base portion, and at least a part of the impedance structure portion is It is accommodated in the accommodating part.

  According to this semiconductor device, since at least a part of the impedance structure portion is housed in the housing portion of the base portion, it is possible to improve the resistance of the semiconductor device against noise from the base portion while suppressing an increase in size of the semiconductor device. it can.

  A semiconductor device according to a third aspect is the semiconductor device according to the first or second aspect, further comprising an external connection terminal provided in the base portion in a state of being insulated from the base portion.

  According to this semiconductor device, the noise that enters the base portion from the external connection terminal via the parasitic capacitance and further enters the semiconductor device is caused by the high impedance structure portion provided so as to be located in the intrusion path. Intrusion into the semiconductor device is prevented. Thereby, the tolerance of the semiconductor device against noise from the external connection terminal can be improved.

The semiconductor device according to claim 4 is the semiconductor device according to any one of claims 1 to 3, at least a portion of the pre-Symbol first coil is equal to or in contact with the base.

  According to this semiconductor device, since at least a part of the first coil is in contact with the base, noise that attempts to enter the semiconductor device from the base is guided to the first coil that is at least partially in contact with the base. . As a result, the noise propagates through the coil, so that the intrusion of the noise can be reliably prevented by the inductance of the coil.

  A semiconductor device according to a fifth aspect is the semiconductor device according to the fourth aspect, wherein the first coil has a plurality of spiral structure portions formed in line symmetry with each other.

  According to this semiconductor device, since the spiral structure portions of the first coil are formed in line symmetry with each other, mutual inductance is suppressed between the symmetrical spiral structure portions. Thereby, since the higher effective inductance can be ensured with respect to the self-inductance of the first coil, that is, the noise, the noise can be effectively prevented.

The semiconductor device according to claim 6 is provided before Symbol accommodating portion, said insulator further comprises the device support portions semiconductor device is mounted through the impedance structure section, the device and the supporting part It is comprised by the spacer which has the said 1st coil interposed between the bases and electrically connected to the said base and the said device support part, It is characterized by the above-mentioned.

  According to this semiconductor device, the spacer is interposed in the gap between the device support portion and the storage portion housed in the housing portion of the base portion, and is provided in this spacer and is electrically connected to the device support portion and the base portion. Noise is reduced by the made first coil. Thus, since it is comprised so that the noise which tries to penetrate | invade into a semiconductor device from a base may pass a spacer, the penetration | invasion of noise can be prevented reliably by the inductance of a 1st coil.

  A semiconductor device according to a seventh aspect is the semiconductor device according to the first aspect, wherein the high impedance structure portion is attached to a surface of the base portion.

  According to this semiconductor device, the high-impedance structure attached to the surface of the base prevents the noise from entering the semiconductor device by exhibiting a high impedance to the noise that attempts to enter the semiconductor device from the base. Can do. Thus, since the impedance structure part is provided separately from the base part, the impedance structure part can be easily attached to the base part.

The semiconductor device according to claim 8, before Symbol impedance structure, characterized in that it comprises at least one second coil of the order to Ru hinder penetration into the semiconductor device of the noise.

  According to this semiconductor device, similarly to the semiconductor device according to the above-described fourth aspect, while the noise that is about to enter the semiconductor device propagates through the second coil, the inductance reliably prevents the noise from entering. it can.

  The semiconductor device according to claim 9 is the semiconductor device according to claim 8, wherein the impedance structure portion further includes a first insulating structure portion for insulating the semiconductor device and the base portion. Two coils are provided between the first insulating structure and the base, and at least one between the first insulating structure and the semiconductor device.

  According to this semiconductor device, the second coil provided between the first insulating structure portion and the base portion of the impedance structure portion and at least one between the first insulating structure portion of the impedance structure portion and the semiconductor device. This prevents the intrusion of noise. Thus, by arranging the second coil on the noise propagation path between the base and the semiconductor device, the second coil can reliably prevent noise from entering.

  A semiconductor device according to a tenth aspect is the semiconductor device according to the ninth aspect, wherein the first insulating structure portion has a recess that is open toward the base portion and is formed toward the semiconductor device. The two coils extend in a spiral shape along the inner surface of the recess from the base side end of the recess toward the semiconductor device.

  According to this semiconductor device, noise from the base portion enters the second coil provided in the recess opening toward the base portion of the first insulating structure portion from the vicinity of the end portion on the base side closer to the base portion. And it propagates along the 2nd coil formed in spiral along the inner surface of a crevice.

  According to the above configuration, one end of the spiral second coil can be disposed closer to the base than the other part of the second coil, so that the base is electrically connected more strongly than the other part. Can be made. Thereby, the noise from the base can be caused to enter the second coil from the vicinity of the end on the base side of the second coil, and the propagation distance of the noise in the second coil becomes longer. The impedance can be made higher, and the effect of preventing the intrusion of noise can be improved.

  A semiconductor device according to an eleventh aspect is the semiconductor device according to the ninth aspect, wherein the impedance structure portion further includes a second insulating structure portion for insulating the semiconductor device and the base portion. Two coils are incorporated in the second insulating structure.

  According to this semiconductor device, noise that tends to enter the semiconductor device from the base is blocked by the impedance structure having the second insulating structure having the second coil built therein. As described above, by incorporating the second coil in the insulating structure portion arranged in the noise propagation path from the base portion to the semiconductor device, the noise can be reliably prevented by the inductance of the second coil.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment. FIG. 2 is a plan view showing an impedance structure portion of the semiconductor device of FIG. 1. FIG. 2 is a diagram schematically showing the semiconductor device of FIG. 1. It is a figure which shows the voltage which arises between the terminals of the capacitor provided in the semiconductor device when a voltage is applied to the semiconductor device of FIG. 1 according to the inductance of an impedance structure part. FIG. 6 is a plan view showing an impedance structure portion of a first modification of the semiconductor device of FIG. 1. FIG. 10 is a plan view showing an impedance structure portion of a second modification of the semiconductor device of FIG. 1. It is sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment. FIG. 8 is a perspective view showing an impedance structure portion of the semiconductor device of FIG. 7. It is sectional drawing which shows the semiconductor device which concerns on 3rd Embodiment. FIG. 10A is a plan view showing an impedance structure portion of the semiconductor device in FIG. 9 and a cross-sectional view along line CC in FIG. 9B. It is sectional drawing which shows the semiconductor device which concerns on 4th Embodiment. It is a top view (A) which shows the impedance structure part of the semiconductor device of FIG. 11, and sectional drawing (B) which follows the line DD of the figure. It is sectional drawing which shows the semiconductor device which concerns on 5th Embodiment. It is sectional drawing which shows the semiconductor device which concerns on a comparative example.

  The semiconductor device according to the first embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 1, the semiconductor device 1 according to the present embodiment includes a substrate 2 (base), an insulator 3, a semiconductor device 10 mounted on the substrate 2 via the insulator 3, and an electrical connection to the semiconductor device 10. Connected lead frames 4a and 4b (external connection terminals) and the like. Hereinafter, for convenience, the semiconductor device 10 side will be described as the “upper” side of the semiconductor device 1 and the substrate 2 side will be described as the “lower” side.

  The board | substrate 2 is provided as a base material for attaching the semiconductor device 10, and is comprised with the metal mainly in order to ensure rigidity and heat dissipation. The insulator 3 is an insulating adhesive, whereby the semiconductor device 10 is provided in a state of being electrically insulated from the substrate 2. The semiconductor device 10 is obtained by forming semiconductor elements such as capacitors, transistors, and diodes on a semiconductor wafer, and includes a wafer substrate 10a, an element forming portion 10b on which the semiconductor elements are formed, and terminals provided on the element forming portion 10b. 10c, 10d, etc.

  The lead frames 4 a and 4 b are provided on the substrate 2 in a state of being insulated from the substrate 2 by the insulator 3 as in the semiconductor device 10. The lead frames 4a and 4b are connected to the terminals 10c and 10d by bonding wires 5 in order to supply power to the semiconductor device 10 and input / output signals through the terminals 10c and 10d, respectively.

  The substrate 2 has a recess 2a (accommodating portion). The recess 2a is open above the substrate 2 and has a square planar shape and a predetermined depth. The recess 2a is formed to have a size larger than that of the semiconductor device 10 when viewed from above. The recess 2a is attached with the impedance structure 20 accommodated therein. The impedance structure 20 is formed in a block shape with substantially the same shape and size as the recess 2a, and is accommodated in the recess 2a with almost no gap between the impedance structure 20 and the substrate 2.

  Moreover, the impedance structure part 20 has the coil 21 (1st coil) shown with the hatching in FIG. The coil 21 is composed of a strip-shaped conducting wire that is wide in the vertical direction, and is formed symmetrically with respect to the symmetrical centerline A. The coil 21 has spiral portions 21a and 21a formed by winding a conducting wire in a spiral shape on both sides of the symmetrical center line A. In addition, convex portions 21b protruding toward the substrate 2 are provided integrally with the spiral portions 21a on the side surfaces of the outer edge portions facing the concave portions 2a of the spiral portions 21a, and these are in contact with the substrate 2 respectively. Yes.

  The insulator 22 is provided so as to fill a gap between the conductive wires constituting the coil 21. The insulator 22 is made of an insulating material whose thermal expansion coefficient (hereinafter referred to as “CTE”) is close to that of the substrate 2. Further, when the impedance structure 20 is accommodated in the recess 2a, an insulator 22 is also formed on the lower side of the coil 22 so that the coil 22 does not contact the bottom surface of the recess 2a. The convex portions 21b and 21b are in contact with the substrate 2 only. Further, the semiconductor device 10 is disposed at a position indicated by a two-dot chain line in FIG. 2, that is, immediately above the impedance structure portion 20, and is mounted on the substrate 2 via the impedance structure portion 20, and the coil 21 of the impedance structure portion 20. Covered from below.

  In addition, the following are mentioned as a combination of the material which comprises the board | substrate 2, the coil 21, and the insulator 22. FIG. For example, the substrate 2 has a CTE of 4.8 to 5.2, the coil 21 has a CTE of 4.8 to 5.2, and the insulator 22 has a CTE of 3.4 to 6.0. Each is made of hard glass. Alternatively, the substrate 2 is a copper-tungsten alloy having a CTE of 6.5 to 8.3, the coil 21 is a copper clad material using a 42 alloy core designed to have a CTE of about 8, and the insulator 22 is a CTE. Consists of 8.5-9.0 soda glass. Alternatively, the substrate 2 is made of SUS304 having a CTE of 17.2, the coil 21 is made of phosphor bronze having a CTE of 17.8 to 18.2, and the insulator 22 is made of polyphenylene oxide having a CTE of 22. As described above, as the materials of the substrate 2, the coil 21, and the insulator 22, materials having similar thermal expansion coefficients are employed.

  Further, as another material of the substrate 2, any of 42 alloy, copper clad material using Invar core or 42 alloy core, Cu-W alloy, 50 alloy, 476 alloy, Al-SiC (mixed fired product), etc. It may be used. Further, as the other material of the coil 21, any of 42 alloy, copper clad material using Invar core, Permalloy B, SUS430, Permalloy C, pure copper, and aluminum may be used. Further, as the other material of the insulator 22, any one of alumina, epoxy (filler added), and polyphenylene oxide mixed with glass fiber may be used.

  The material constituting the substrate 2, the coil 21 and the insulator 22 is based on the above materials, taking into consideration the thermal expansion coefficient, the magnetic permeability of the coil 21, the manufacturing cost, and the like. Each is determined so as to ensure the impedance. Moreover, in order to suppress the influence by the difference in a thermal expansion coefficient, it is desirable to form the thickness of the conducting wire of the coil 21 thinner. Further, it is desirable to use a material having higher magnetic permeability for the coil 21.

  FIG. 14 shows a semiconductor device 100 according to a comparative example of the semiconductor device 1 described above. In the semiconductor device 100 of this comparative example, the impedance structure 20 is omitted from the semiconductor device 1, and in this semiconductor device 100, there is a path for noise to enter the semiconductor device 10 from the substrate 2. Specifically, various wirings provided on the substrate 2 such as the lead frames 4a and 4b and the substrate 2 are electrically connected via a parasitic capacitance, and the substrate 2 and the semiconductor device 10 also have a parasitic capacitance. As a result, a noise intrusion path is formed by a path indicated by a broken line in FIG. Further, for example, even when the electromagnetic noise N directly enters the substrate 2, the intrusion route as described above is configured.

  On the other hand, according to the semiconductor device 1, noise that has entered the substrate 2 from the lead frames 4 a and 4 b through the parasitic capacitance between the substrate 2 and the impedance structure 20 between the semiconductor device 10 and the substrate 2. Since the convex portions 21b and 21b of the coil 21 are in contact with the substrate 2, the coil 21 is guided to the coil 21 through the convex portions 21b and 21b. Then, the noise propagates through the coil 21, and the inductance prevents the noise from entering the semiconductor device 10.

  FIG. 3 is a model schematically showing the semiconductor device 1 described above. As shown in the figure, in the semiconductor device 10, a capacitor 11 and an ESD diode 12 are formed as semiconductor elements of the element forming portion 10b. A lead frame 4 a is connected to one terminal of the capacitor 11. Further, for example, an ESD protection diode 12 formed of a Zener diode is used to prevent a high voltage (hereinafter referred to as “ESD voltage”) resulting from electrostatic discharge from entering the capacitor 11 through the lead frame 4a. However, the anode side is grounded and the cathode side is connected to the lead frame 4a via the pad 12a.

  The capacitor C represents a parasitic capacitance between the lead frame 4a and the semiconductor device 10 in the noise intrusion path, and the resistor R1 (for example, 35 kΩ) represents the resistance of the bonding wire 5 and the resistor R2 (for example, 1E9Ω). ) Represents, for example, the resistance of a housing that houses the semiconductor device 1.

  When the simulation using the above model was performed, the following results were obtained. FIG. 4 shows a voltage generated between the terminals of the capacitor 11 when a predetermined voltage (for example, 15 kV) is applied to the lead frame 4a instantaneously (for example, 40 psec) as an ESD voltage. As shown in the figure, when the impedance value of the impedance structure unit 20 is 0, that is, when the present invention is not applied and the impedance structure unit 20 is not provided, the voltage between the terminals of the capacitor 11 instantaneously becomes 956V. Rose.

  This is because the current due to the ESD voltage applied to the lead frame 4a does not escape through the ESD protection diode 12, but enters the capacitor 11 through the intrusion route via the substrate 2 and increases the voltage between the terminals. Is shown. On the other hand, when the impedance structure 20 is provided by applying the present invention, the voltage between the terminals is reduced according to the impedance value.

  Specifically, when the impedance value is set to 1 nH, the voltage value between the terminals is reduced to 830 V, and the influence of noise entering the capacitor 11 via the substrate 2 is reduced by the impedance structure unit 20. It was confirmed that Further, when the impedance value of the impedance structure unit 20 is set to a larger value of 10 nH, the voltage between the terminals is further reduced to approximately 400 V, and the fluctuation of the voltage between the terminals is suppressed as the impedance is set to a larger value. confirmed. In particular, when the impedance value was increased to 1 μH, it was confirmed that the fluctuation range of the inter-terminal voltage was suppressed to about 8 V, and that the influence of noise from the substrate 2 side almost disappeared. In the present embodiment, a high impedance is shown with respect to noise that has entered the substrate 2 from terminals and wiring on the substrate 2 such as the lead frames 4a and 4b, and electromagnetic noise that has entered the substrate 2, that is, the noise of these noises. The impedance of the impedance structure unit 20 is set so that entry into the semiconductor device 10 is prevented.

  As described above, according to the semiconductor device 1 according to the present embodiment, when the semiconductor device 10 is mounted on the metal substrate 2, the impedance structure portion is on the noise intrusion path from the substrate 2 into the semiconductor device 10. 20, even if noise caused by electrostatic discharge or the like attempts to enter from the substrate 2 side, the impedance structure portion 20 exhibits a high impedance to the noise, thereby preventing the noise from entering the semiconductor device 10. It is done. As described above, since the impedance structure portion 20 provides stronger resistance to noise from the substrate 2 side, the semiconductor device 1 in which the semiconductor device 10 operates more stably can be obtained.

  In addition, since the semiconductor device 10 is disposed immediately above the impedance structure portion 20 and mounted on the substrate 2 with the impedance structure portion 20 interposed, noise that is about to enter from the substrate 2 side is always generated. 20 is passed. Therefore, the impedance structure 20 can reliably prevent noise from entering. Further, since the coil 21 has the same spiral portion 21a on both sides of the symmetrical centerline A, the mutual inductance between the spiral portions 21a and 21a is suppressed, so that the self-inductance of the coil 21, that is, noise can be reduced. The effective inductance can be kept high. As a result, the impedance structure unit 20 can prevent noise by exhibiting high impedance with respect to noise.

  Moreover, since the impedance structure part 20 is accommodated in the accommodating part 2a provided in the board | substrate 2, and the semiconductor device 10 is arrange | positioned just on it, the size as the whole semiconductor device 1 containing both 10 and 20 increases. The semiconductor device 10 can be stably operated while being suppressed. Further, since the protrusions 21 b and 21 b of the coil 21 are in contact with the substrate 2, noise that has entered the substrate 2 is reliably guided to the coil 21, so that the noise can be reliably prevented by the inductance of the coil 21. .

  Next, a first modification of the semiconductor device 1 according to the first embodiment described above will be described. FIG. 5 shows the substrate 2 and the impedance structure portion 20a of the semiconductor device according to this modification. In this semiconductor device, a concave portion 2b (accommodating portion) having a circular planar shape is formed in the substrate 2, and a cylindrical impedance structure portion 20a is accommodated in the concave portion 2b.

  Instead of the coil 21 having the two spiral portions 21a and 21a of the first embodiment, the impedance structure portion 20a is provided with a coil 23 (first coil) having a single spiral structure and an insulation for sealing the coil 23. It has a body 22a. Similarly to the coil 21, convex portions 23 a and 23 a provided at the peripheral edge of the coil 23 facing the concave portion 2 b are in contact with the substrate 2. Further, the semiconductor device 10 is arranged at a position indicated by a two-dot chain line in FIG. 5, that is, immediately above the impedance structure portion 20a. Other configurations are the same as those of the first embodiment described above.

  According to the semiconductor device according to the first modified example having the above configuration, the noise that has entered the coil 23 from the substrate 2 side via the convex portion 23a propagates through the coil 23, and the noise semiconductor device 10 is generated by the inductance. Intrusion into is prevented. As described above, the impedance structure 20a exhibits impedance with respect to noise, so that the operation of the semiconductor device 10 can be further stabilized as in the semiconductor device 1 according to the first embodiment. In addition, since the coil 23 having a simpler configuration is used, the semiconductor device 1 can be manufactured at a lower cost than the semiconductor device 1 of the first embodiment.

  FIG. 6 shows the substrate 2 and the impedance structure 20b of the semiconductor device according to the second modification. In this semiconductor device, the impedance structure portion 20b includes a coil 24 instead of the coil 21 of the first embodiment. The coil 24 has two subcoil portions 24a and 24a (spiral structure portions) formed symmetrically with respect to the symmetry center line B. Each subcoil portion 24a includes two spiral portions arranged in parallel. Each has. Moreover, the convex part 24b is formed in the side surface facing the recessed part 2a of each subcoil part 24a, and each subcoil part 24a is contacting the board | substrate 2 via the convex part 24b.

  Further, as indicated by a two-dot chain line in FIG. 6, the semiconductor device 10 is mounted on the substrate 2 so that the region 10 e of the semiconductor device 10 in which a circuit that requires protection from noise is disposed is located immediately above the coil 24. Thus, the region 10e is covered from below by the impedance structure 20b. Other configurations are the same as those of the first embodiment described above.

  According to the semiconductor device according to the second modified example having the above-described configuration, the noise that has entered the coil 24 from the substrate 2 via the convex portion 24b is the same as in the first embodiment and the first modified example. The inductance of 24 prevents entry into the semiconductor device 10. Accordingly, at least the region 10e of the semiconductor device 10 is protected from noise entering from the substrate 2 side. Further, since the sub-coil portions 24a and 24a are configured symmetrically with each other, the mutual inductance is suppressed as in the first embodiment, so that a larger effective inductance of the coil 24 can be ensured. As described above, also in the semiconductor device according to the second modification, the semiconductor device 10 can be stably operated when the impedance structure portion 20b exhibits impedance with respect to noise.

  Next, a semiconductor device according to the second embodiment will be described focusing on differences from the semiconductor device 1 of the first embodiment described above. As shown in FIG. 7, in the semiconductor device 1 a of this embodiment, a block-shaped device support 6 is accommodated in the recess 2 a of the substrate 2. The device support 6 is made of the same metal as the substrate 2 and is smaller in size than the recess 2a so that a gap is formed between the device support 6 and the recess 2a. The device support portion 6 is provided in the gap between the concave portion 2a and is accommodated in the concave portion 2a via an insulating sealing material 7 made of an insulating material. In addition, a semiconductor device 10 is mounted on the upper surface of the device support 6 via an insulator 3.

  In addition, a plurality of spacers 30 (impedance structure portions) are also provided in the gap between the recess 2 a and the device support portion 6. As shown in FIG. 8, each spacer 30 is formed in a cylindrical shape by a solenoid coil 31 (first coil) composed of a conductor and an insulating material 32 for sealing the solenoid coil 31. Further, both end portions 31 a and 31 a of the solenoid coil 31 protrude from the insulating material 32. Further, the length of the spacer 30 excluding both end portions 31 a and 31 a is set to be approximately the same as the width of the gap between the recess 2 a and the device support portion 6.

  Such a spacer 30 is disposed between the side surface of the device support 6 and the side surface of the recess 2a, and is disposed between the lower surface of the device support 6 and the bottom surface of the recess 2a. Further, one end 31 a of the solenoid coil 31 is in contact with the device support portion 6, and the other end 31 a is in contact with the substrate 2. As a result, the solenoid coil 31 is electrically connected to the substrate 2 and the device support 6. Other configurations are the same as those of the first embodiment described above.

  According to the semiconductor device 1a according to the second embodiment having the above configuration, when the noise that has entered the substrate 2 tries to pass through the solenoid coil 31 of the spacer 30 accommodated in the recess 2a, the spacer 30 is Impedance for noise is indicated by the inductance of the noise, thereby preventing noise from entering. Therefore, as in the first embodiment described above, it is possible to obtain a semiconductor device 1a that has a higher resistance to noise and can operate the semiconductor device 10 more stably while suppressing an increase in size of the semiconductor device 1a. it can. When a plurality of spacers 30 are provided, it is desirable that the number of the spacers 30 be small because a plurality of inductances may be paralleled to reduce the impedance against noise.

  Next, a semiconductor device according to the third embodiment will be described focusing on differences from the semiconductor device 1 of the first embodiment. As shown in FIG. 9, in the semiconductor device 1 b according to the present embodiment, the impedance structure portion 40 is attached to one surface of the substrate 2 via the insulator 3. The semiconductor device 10 is mounted on the substrate 2 with the insulator 3 and the impedance structure portion 40 interposed between the semiconductor device 10 and the substrate 2.

  FIG. 10A shows the impedance structure 40 from below. As shown in FIG. 10A, the impedance structure 40 includes a device support 41 (first insulating structure) and a plurality of coils 42 (second Coil). The device support portion 41 is formed in a block shape with an insulating material such as hard glass, for example, and is set so that its CTE is a value approximately between the CTEs of the semiconductor device 10 and the substrate 2. Further, for example, four concave portions 41 a are formed at the lower end portion of the device support portion 41. As shown in FIG. 10B, each recess 41a is open to the lower substrate 2 side, and is formed in a tapered shape toward the upper semiconductor device 10 side.

  The coil 42 is made of a conductor and is provided on the inner surface of each recess 41a. The coil 42 extends in a spiral shape from the lower end of the recess 41a along the inner surface toward the upper semiconductor device 10, and the upper semiconductor device 10 is almost covered from below by the total of four coils 42. Yes. Further, the lower end portion of the coil 42 is in contact with the insulator 3 between the device support portion 41 and the substrate 2.

  The impedance structure section 40 as described above can be obtained, for example, by attaching a semiconductor wafer on which a plurality of semiconductor devices 10 are formed to glass constituting the device support section 41 and cutting it for each semiconductor device 10. The device support 40 may be made of silicon, for example. In that case, the recess 42a having a required taper can be easily formed by etching with alkali. Moreover, you may comprise the device support part 40 with the ceramic material for ceramic substrates. In that case, the impedance structure part 40 can be easily formed by forming the coil 42 with, for example, silver paste in a semi-cured state of the ceramic material and firing them. Other configurations are the same as those of the first embodiment described above.

  According to the semiconductor device 1 b having the above configuration, the noise that has entered the substrate 2 enters the impedance structure portion 40 via the parasitic capacitance between the substrate 2 and the impedance structure portion 40. At this time, as described above, the lower end portion of the coil 42 is in contact with the insulator 3 at a position closer to the substrate 2 than other portions, and is more electrically connected to the substrate 2 than other portions. Therefore, noise easily enters the coil 42 from the vicinity of the lower end portion of the coil 42. Therefore, a longer propagation path of noise from the vicinity of the lower end of the coil 42 to the upper end is ensured. Noise entering the coil 42 from near the lower end is prevented from entering the semiconductor device 10 due to the inductance of the coil 42 while propagating through the coil 42 toward the upper semiconductor device 10 side.

  As described above, according to the semiconductor device 1b according to the third embodiment, the impedance structure section 40 is interposed between the semiconductor device 40 outside the substrate 2, and thereby the impedance structure section 40 is attached to the substrate 2. Easy to install. Further, since the coil 42 is provided along the inner surface of the tapered concave portion 41a and is configured so that noise is likely to enter from the vicinity of the lower end portion thereof, a longer propagation path of noise is provided. By ensuring, the intrusion of noise can be more effectively prevented by the inductance of the coil 42. The recess 41a may be formed in, for example, a step shape toward the semiconductor device 10, and the coil 42 may be provided so as to extend spirally along the inner surface. Even in this case, the same effect as that obtained when the tapered concave portion 41a is provided can be obtained.

  Next, a semiconductor device according to the fourth embodiment will be described focusing on differences from the semiconductor device 1b of the third embodiment described above. As shown in FIG. 11, in the semiconductor device 1c according to the present embodiment, the impedance structure unit 50 is attached to one surface of the substrate 2 via the insulator 3, as in the third embodiment. The semiconductor device 10 is mounted on the substrate 2 via an insulator 3 provided between the semiconductor device 10 and the impedance structure unit 50.

  As shown in FIGS. 12A and 12B, the impedance structure section 50 is built in the device support section 51 (second insulation structure section) in which a plurality of insulating layers 51a are stacked, and the device support section 51. For example, four coils 52 are provided. Each insulating layer 51a is made of, for example, low-temperature fired ceramics, and has a CTE that is closer to the CTE of the semiconductor device 10 than the printed wiring board.

Each coil 52 is provided between the insulating layers 51a and has a conductor layer made of, for example, ferrite. Specifically, the coil 52 includes a lowermost insulating layer 51a, a first layer 52a provided between the lowermost insulating layer 51a and the second and third insulating layers 51a. has a second layer 52b which is provided, a third layer 52 c provided between the third layer and the fourth layer of the insulating layer 51a in between.

  The first layer 52a constitutes the lower end of the coil 52, and is located at the center of the coil 52 when viewed from above. The second layer 52b extends so as to surround the first layer 52c so as not to overlap the first layer 52b in the vertical direction. The end of the first layer 52a and the end of the second layer 52b are two layers. The vias (not shown) provided in the through holes (not shown) formed in the insulating layer 51a of the eye are electrically connected to each other. Further, the third layer 52c extends so as to surround the second layer 52b so as not to overlap the first and second layers 52a and 52b in the vertical direction, and the end portion of the second layer 52b and the third layer 52c. Are connected to each other by a via 52d provided in a penetrating term 51b formed in the third insulating layer 51a. The coil 52 is formed in a spiral shape by the first to third layers 52a to 52c as described above. Other configurations are the same as those of the third embodiment described above.

  According to the semiconductor device 1 c having the above configuration, the noise that has entered the substrate 2 enters the coil 52 of the impedance structure unit 50 via the parasitic capacitance between the substrate 2 and the impedance structure unit 50. Then, noise propagates to the semiconductor device 10 due to the inductance of the coil 52 while propagating through the second layer 52b and the third layer 52c sequentially from the first layer 52a at the lower end of the coil 52 toward the upper semiconductor device 10. Is prevented from entering. As described above, according to the semiconductor device 1c according to the fourth embodiment, the same effects as those of the semiconductor device 1b according to the third embodiment described above can be obtained.

  Next, a semiconductor device according to the fifth embodiment will be described focusing on differences from the above-described third embodiment. As shown in FIG. 13, in the semiconductor device 1d according to the present embodiment, the impedance structure section 60 is attached to the substrate 2 via the insulator 3 as in the third embodiment. These are mounted on the substrate 2 via an insulator 3 provided between the impedance structure 60 and the impedance structure 60.

  The impedance structure section 60 includes a device support section 61 (first insulating structure section) disposed on the substrate 2 side and a plurality of coils 62 (second coils) disposed on the semiconductor device 10 side. The device support part 61 is formed in a block shape by an insulating material such as hard glass, for example, and insulates the substrate 2 and the semiconductor device 10. The plurality of coils 62 are arranged in parallel on the entire upper surface of the device support portion 61 and are arranged so as to cover the semiconductor device 10 from below. Note that a single coil may be provided on the entire top surface of the device support 61.

  According to the semiconductor device 1d having the above configuration, the noise that has entered the substrate 2 enters the coil 62 through the parasitic capacitance between the substrate 2 and the coil 62, and the inductance prevents the noise from entering the semiconductor device 10. It is done. Therefore, also in the semiconductor device 1d of this embodiment, the semiconductor device 10 can be operated more stably.

  In the above-described first embodiment, its modification, and the second embodiment, it has been described that any one of the impedance structures 20, 20a, 20b, 30 is accommodated in the recess 2a formed in the substrate 2. Instead of the recess 2a, a through hole penetrating the substrate 2 that is easier to process may be formed, and the impedance structure portion 20 and the like may be accommodated in the through hole.

  Further, for example, by providing the coil 62 of the fifth embodiment described above between the semiconductor device support portion and the semiconductor device in the third and fourth embodiments, both the substrate side and the semiconductor device side of the device support portion are provided. You may make it arrange | position a coil to.

  Further, the shape and number of coils of the impedance structure portion are not limited to those described in the above-described embodiments and modifications, and the entire semiconductor device or a region including at least a circuit that requires protection from noise in the semiconductor device. As long as it can be covered from the substrate 2 side. In addition, it is possible to appropriately change the detailed configuration within the scope of the gist of the present invention.

1, 1a to 1d Semiconductor device 2 Substrate (base)
3 Insulator 10 Semiconductor device 20, 20a, 20b Impedance structure 30 Spacer (impedance structure)
40 Impedance structure 50 Impedance structure 60 Impedance structure

Claims (11)

A metal base (2);
A semiconductor device (10) mounted on the base;
An insulator (3) interposed between the base and the semiconductor device;
A semiconductor device (1, 1a to 1d) comprising:
The base is attached to the base between the base and the semiconductor device so as to be located in an intrusion path of noise entering the semiconductor device via a parasitic capacitance between the base and the semiconductor device, An impedance structure (20, 20a, 20b, 30, 40, 50, 60) showing high impedance to the noise ,
The impedance structure has at least one first coil (21, 23, 24, 31) for preventing the noise from entering the semiconductor device;
At least one end of the first coil is surrounded by the insulator . The base is formed with an accommodating portion (2a) for accommodating the impedance structure portion (20, 20a, 20b, 30),
The semiconductor device according to claim 1, wherein at least a part of the impedance structure portion is accommodated in the accommodation portion.   The semiconductor device according to claim 1, further comprising an external connection terminal (4 a, 4 b) provided on the base portion in a state of being insulated from the base portion. At least a portion (21b, 23a, 24b, 31a ) is a semiconductor device according to any one of claims 1 to 3, characterized in that in contact with the base of the front Symbol first coil.   The semiconductor device according to claim 4, wherein the first coil (21, 24) has a plurality of spiral structure portions (21a, 24a) formed in line symmetry with each other. A metal base (2);
A semiconductor device (10) mounted on the base;
An insulator (3) interposed between the base and the semiconductor device;
A semiconductor device (1a) comprising:
The base is attached to the base between the base and the semiconductor device so as to be located in an intrusion path of noise entering the semiconductor device via a parasitic capacitance between the base and the semiconductor device, A plurality of impedance structures (30) exhibiting high impedance to the noise,
The base is formed with an accommodating portion (2a) for accommodating the impedance structure portion,
The impedance structure has a first coil (31) for preventing the noise from entering the semiconductor device,
At least a portion (31a) of the first coil is in contact with the base,
A device supporting part (6) provided in the housing part, to which the semiconductor device is attached via the insulator;
The impedance structure part (30) is a spacer (30) having the first coil (31) interposed between the device support part and the base part and electrically connected to the base part and the device support part. Configured ,
At least one of the plurality of spacers (30) is disposed between a side surface of the device support portion and a side surface of the housing portion, and at least one other is a lower surface of the device support portion. semi conductor arrangement you being disposed between the bottom surface of the accommodating portion and.   The semiconductor device according to claim 1, wherein the impedance structure portion (40, 50, 60) is attached to a surface of the base portion. A metal base (2);
A semiconductor device (10) mounted on the base;
An insulator (3, 41, 51a) interposed between the base and the semiconductor device;
A semiconductor device (1b-1d) comprising:
The base is attached to the base between the base and the semiconductor device so as to be located in an intrusion path of noise entering the semiconductor device via a parasitic capacitance between the base and the semiconductor device, An impedance structure (40, 50, 60) showing a high impedance to the noise,
The impedance structure (40, 50, 60) is attached to the surface of the base,
The impedance structure has at least one second coil (42, 52, 62) for preventing the noise from entering the semiconductor device ;
Wherein at least one end of the second coil, the insulator semiconductors devices characterized in that it is surrounded by (3,41,51a). The impedance structure (40, 60) further includes a first insulating structure (41, 61) for insulating the semiconductor device and the base.
9. The second coil according to claim 8, wherein the second coil is provided between at least one of the first insulating structure and the base and between the first insulating structure and the semiconductor device. The semiconductor device described. The first insulating structure (41) has a recess (41a) that opens toward the base and is formed toward the semiconductor device;
The said 2nd coil (42) is extended in the spiral form along the inner surface of the said recessed part toward the said semiconductor device from the edge part by the side of the said base of the said recessed part. Semiconductor device. The impedance structure (50) further includes a second insulating structure (51) for insulating the semiconductor device and the base.
The semiconductor device according to claim 8, wherein the second coil (52) is built in the second insulating structure.

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