JP6000682B2 - Chip type multilayer capacitor - Google Patents

Description

  The present invention relates to a chip-type multilayer capacitor that can be reduced in size and increased in capacity and can reduce acoustic noise generated between internal electrodes when a power supply is applied.

  Along with the downsizing and multi-functionalization of electronic products, there is also a demand for downsizing and increasing the capacity of chip type multilayer capacitors built in the electronic products.

  In order to reduce the size and increase the capacity of the chip type multilayer capacitor, it is necessary to use a ferroelectric material such as barium titanate as a ceramic material for forming the dielectric layer. However, when a DC and AC voltage is applied to a chip-type multilayer capacitor having a dielectric layer made of a ferroelectric material, a piezoelectric phenomenon and vibration occur between the internal electrodes.

  The vibration tends to become more prominent when the shape of the chip is relatively large based on the same capacitance as the dielectric constant of the dielectric layer is higher. The vibration is transmitted from an external electrode of the chip multilayer capacitor to a circuit board on which the chip multilayer capacitor is mounted. At this time, resonance occurs while the circuit board vibrates.

  That is, when resonance due to vibration of the circuit board is included in an audible frequency (20 to 20000 Hz) region, the vibration sound gives an unpleasant feeling to humans, and such vibration sound is referred to as acoustic noise.

  As described above, the acoustic noise caused by the piezoelectric phenomenon of a multilayer ceramic capacitor using a ferroelectric material is a serious problem in some electronic devices.

  Such vibration noise causes noise generation in an electronic device on which the multilayer ceramic capacitor is mounted.

  An object of the present invention is to provide a chip type multilayer capacitor capable of reducing acoustic noise even when the dielectric constant of a dielectric layer is lowered and the thickness is significantly reduced.

  In one aspect of the present invention, a chip-type multilayer capacitor according to an embodiment of the present invention includes a ceramic body including a dielectric layer formed with a thickness of not less than 10 times the average grain size and not more than 3 μm, and the ceramic. First and second external electrodes formed on both end faces in the length direction of the main body, and extending from the first and second external electrodes to the LW plane on the inner side in the length direction of the ceramic main body. First and second band portions having different lengths formed, and different lengths formed by extending from the first and second external electrodes on the LT plane on the inner side in the length direction of the ceramic body. And third and fourth band portions having a thickness.

In a chip type multilayer capacitor according to an embodiment of the present invention, fifth and sixth band portions are formed on one surface of the ceramic body on which the first and second band portions are formed and on the other surface corresponding to the stacking direction. The seventh and eighth band portions are formed on one surface of the ceramic body on which the third and fourth band portions are formed and on the other surface corresponding to the width direction, and the following conditions (1) to (4) ) Can be satisfied.

  Here, BWave1 is an average value of the lengths of the first and second band portions, and BWave1 = (A1 + A2) / 2, and BWave2 is an average value of the lengths of the third and fourth band portions. BWave2 = (B1 + B2) / 2, BWave3 is the average value of the lengths of the fifth and sixth band portions, and BWave3 = (C1 + C2) / 2, and BWave4 is the seventh and eighth The average value of the length of the band part is BWave4 = (D1 + D2) / 2, A1 is the length of the first band part, A2 is the length of the second band part, and B1 is The length of the third band part, B2 is the length of the fourth band part, C1 is the length of the fifth band part, and C2 is the length of the sixth band part. D1 is the length of the seventh band part, and D2 is the eighth Of the command part is the length.

In the chip type multilayer capacitor according to an embodiment of the present invention, an absolute value of a difference in length of the band portion on one surface of the ceramic body and the BWave1 to BWave4 are at least one of the following conditions (5) to (8): Can be satisfied.

  Here, A1 is the length of the first band part, A2 is the length of the second band part, B1 is the length of the third band part, and B2 is the fourth band part. C1 is the length of the fifth band portion, C2 is the length of the sixth band portion, and D1 is the length of the seventh band portion. , D2 is the length of the eighth band portion, and C1 ≠ C2 and D1 ≠ D2.

  In another aspect of the present invention, a chip-type multilayer capacitor according to an embodiment of the present invention includes first and second external electrodes formed at both ends in the length direction of a hexahedral ceramic body, and the first The first and third surfaces on the LW plane and the second and fourth surfaces on the L-T plane face each other in the longitudinal direction from the second external electrode. First to eighth band portions to be formed, and the length of at least one of the first to fourth surfaces is different and is the same as at least one of the first to fourth surfaces. The lengths of the band portions on the other surface that are continuous in polarity can be different.

  In the chip multilayer capacitor according to the embodiment of the present invention, the length of the first band portion of the first surface may be different from the length of the third band portion of the second surface.

  In the chip type multilayer capacitor according to an embodiment of the present invention, the lengths of the band portions of the first to fourth surfaces facing each other with the same polarity may be the same or different.

  In the chip multilayer capacitor according to the embodiment of the present invention, at least one of the first to fourth surfaces may have a difference in height between the band portions facing each other.

  In the chip type multilayer capacitor according to an embodiment of the present invention, the dielectric layer may have a thickness of 3 μm or less, and may be 10 times or more the average grain size of the grains in the dielectric layer.

In the chip multilayer capacitor according to the embodiment of the present invention, the first to eighth band portions can satisfy at least one of the following conditions (1) to (4).

  Here, BWave1 is an average value of the lengths of the first and second band portions, and BWave1 = (A1 + A2) / 2, and BWave2 is an average value of the lengths of the third and fourth band portions. BWave2 = (B1 + B2) / 2, BWave3 is the average value of the lengths of the fifth and sixth band portions, and BWave3 = (C1 + C2) / 2, and BWave4 is the seventh and eighth The average value of the length of the band part is BWave4 = (D1 + D2) / 2, A1 is the length of the first band part, A2 is the length of the second band part, and B1 is The length of the third band part, B2 is the length of the fourth band part, C1 is the length of the fifth band part, and C2 is the length of the sixth band part. D1 is the length of the seventh band part, and D2 is the eighth Of the command part is the length.

In the chip type multilayer capacitor according to an embodiment of the present invention, an absolute value of a difference in length of the band portion on one surface of the ceramic body and the BWave1 to BWave4 are at least one of the following conditions (5) to (8): Can be satisfied.

  Here, A1 is the length of the first band part, A2 is the length of the second band part, B1 is the length of the third band part, and B2 is the fourth band part. C1 is the length of the fifth band portion, C2 is the length of the sixth band portion, and D1 is the length of the seventh band portion. , D2 is the length of the eighth band portion, and C1 ≠ C2 and D1 ≠ D2.

In still another aspect of the present invention, a chip multilayer capacitor according to an embodiment of the present invention includes a ceramic body including first and second internal electrodes disposed via a dielectric layer having a thickness of 3 μm or less. And first and second external electrodes formed at both ends in the length direction of the ceramic body and connected to the first and second internal electrodes, respectively, and the first and second internal electrodes The number of grains disposed between the electrodes is 10 or more in the thickness direction of the dielectric layer, and extends inward in the length direction from both ends in the length direction of the ceramic body. 1st to 8th band portions formed opposite to each other on the first surface, the third surface, and the second and fourth surfaces on the LT plane. The length of the band part of at least one surface of the Matter (1) can be satisfied at least one - (4).

  Here, BWave1 is an average value of the lengths of the first and second band portions, and BWave1 = (A1 + A2) / 2, and BWave2 is an average value of the lengths of the third and fourth band portions. BWave2 = (B1 + B2) / 2, BWave3 is the average value of the lengths of the fifth and sixth band portions, and BWave3 = (C1 + C2) / 2, and BWave4 is the seventh and eighth The average value of the length of the band part is BWave4 = (D1 + D2) / 2, A1 is the length of the first band part, A2 is the length of the second band part, and B1 is The length of the third band part, B2 is the length of the fourth band part, C1 is the length of the fifth band part, and C2 is the length of the sixth band part. D1 is the length of the seventh band part, and D2 is the eighth Of the command part is the length.

In the chip type multilayer capacitor according to an embodiment of the present invention, an absolute value of a difference in length of the band portion on one surface of the ceramic body and the BWave1 to BWave4 are at least one of the following conditions (5) to (8): Can be satisfied.

  Here, A1 is the length of the first band part, A2 is the length of the second band part, B1 is the length of the third band part, and B2 is the fourth band part. C1 is the length of the fifth band portion, C2 is the length of the sixth band portion, and D1 is the length of the seventh band portion. , D2 is the length of the eighth band portion, and C1 ≠ C2 and D1 ≠ D2.

  According to the chip type multilayer capacitor and its mounting circuit board according to an embodiment of the present invention, acoustic noise is significantly reduced even in a small and high capacity chip type multilayer capacitor having a dielectric thickness of 3 μm or less.

1 is a schematic partial cutaway perspective view of a chip-type multilayer capacitor according to an embodiment of the present invention. It is the schematic of the cross section which follows the II-II 'line | wire of FIG. (A)-(d) is a schematic plan view which shows the length of the band part of the external electrode formed in the external surface of the chip type multilayer capacitor of FIG. (A) And (b) is a schematic perspective view which expands and shows A and B of FIG. It is a schematic sectional drawing which expands and shows the aspect of the band part of an external electrode. It is a schematic sectional drawing for the measurement of the length of the band part of this invention.

  Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings. However, the idea of the present invention is not limited to the presented embodiments, and those skilled in the art who understand the idea of the present invention can step back by adding, changing, or deleting other components within the scope of the same idea. Although other embodiments included in the scope of the idea of the present invention and the present invention can be easily proposed, these are also included in the scope of the concept of the present invention.

  In addition, the component of the same function on drawing is attached | subjected and shown with the same or similar code | symbol.

Chip Multilayer Ceramic Capacitor FIG. 1 is a schematic partial cutaway perspective view of a chip multilayer capacitor according to an embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view taken along line II-II ′ of FIG. 3A to 3D are schematic plan views showing the lengths of the band portions of the external electrodes formed on the external surface of the chip multilayer capacitor of FIG.

  Referring to FIGS. 1 to 3, the chip-type multilayer capacitor 10 includes a ceramic body 12, first and second external electrodes 14 and 16, band portions 142, 144, 146 148, 162, 164, 166, 168.

  The ceramic body 12 is manufactured by applying a conductive paste so as to form the internal electrode 20 on the ceramic green sheet, laminating the ceramic green sheet on which the internal electrode 20 is formed, and then firing the laminate. be able to. The ceramic body 12 may be formed by repeatedly laminating a number of dielectric layers 40 and internal electrodes 20.

  The ceramic body 12 may have a hexahedral shape. The ceramic body 12 is not a hexahedron having a complete straight line due to the firing shrinkage of the ceramic powder when the chip is fired, but can be substantially a hexahedron.

  In the embodiment of the present invention, L, W, and T in FIG. 1 are referred to as a length direction, a width direction, and a thickness direction, respectively, in defining the hexahedral direction. Here, the thickness direction is a stacking direction in which the dielectric layers are stacked.

  The chip multilayer capacitor 10 shown in FIG. 1 has a rectangular parallelepiped shape whose length direction is larger than the width direction or the thickness direction.

As the material of the dielectric layer 40, ceramic powder having a high dielectric constant can be used to increase the capacity. Examples of the ceramic powder include barium titanate (BaTiO ₃ ) -based powder and strontium titanate (SrTiO ₃ ) -based powder, but are not limited thereto.

  Further, if the grain size is reduced after firing with a ferroelectric ceramic powder having a small average particle size, the dielectric constant of the ferroelectric can be reduced. The present invention is not limited by the dielectric constant of the dielectric layer 40.

  The dielectric layer 40 according to the present embodiment has a thickness td of 3 μm or less, and the average grain size of the ceramic grains 42 forming the dielectric layer 40 can be 0.3 μm or less. That is, the thickness of the dielectric layer 40 may be 10 times or more the average grain size of the grains 42 included in one dielectric layer 40 of the fired chip multilayer capacitor 10.

  Here, the thickness td of the dielectric layer 40 means an average thickness of one dielectric layer 40 disposed between the internal electrodes 20.

  As shown in FIG. 2, the thickness of the dielectric layer 40 can be measured by image-scanning the longitudinal cross section of the ceramic body 12 with a scanning electron microscope (SEM, Scanning Electron Microscope). . For example, as shown in FIG. 2, an arbitrary image taken from an image obtained by scanning a length direction and a thickness direction (LT) section along the center portion of the ceramic body 12 in the width direction W with a scanning electron microscope. By measuring the thickness of the dielectric layer 40 at 30 equally spaced intervals in the length direction, the average value can be obtained. The 30 equally spaced locations can be measured by a capacity forming portion that means a region where the first and second internal electrodes 22 and 24 overlap. In addition, when such an average value measurement is extended to 10 or more dielectric layers 40, the thickness of the dielectric layers can be more generalized.

  The thickness of the dielectric layer 40 can be measured from an image obtained by scanning a cross section in the width direction and the thickness direction (WT) along the central portion in the length direction L with a scanning electron microscope.

  Here, the central portion of the ceramic body 12 in the width direction W or the length direction L is 30% of the width or length of the ceramic body 12 from the center point in the width direction W or the length direction L of the ceramic body 12. Within range.

  Note that the average size of the grains 42 of the dielectric layer 40 can be measured by analyzing a cross-sectional photograph of the dielectric layer taken from an image scanned with a scanning electron microscope. For example, the average size of the grains 42 of the dielectric layer 40 can be measured using grain size measurement software that supports an average grain size standard measurement method defined by ASTM (American Society for Testing and Materials) E112.

  According to an embodiment of the present invention, the dielectric constant of the ceramic can be reduced by reducing the average size of the grain 42. Further, by setting the thickness of the dielectric layer 40 to 3 μm or less, it is possible to make multiple layers of the dielectric layer 40 on the same size chip. Therefore, it is possible to reduce the size and increase the capacity of the chip.

  The internal electrode 20 includes a first internal electrode 22 and a second internal electrode 24, and the first and second internal electrodes 22, 24 are connected to the first and second external electrodes 14, 16, respectively. It can be electrically connected.

  By reducing the thickness td of the dielectric layer 40 to reduce acoustic noise and reducing the average size of the grains 42 in the dielectric layer 40, the dielectric constant can be reduced.

  Thus, when the thickness td of the dielectric layer 40 and the average size of the grains are reduced to reduce the dielectric constant of the multilayer ceramic capacitor 10, acoustic noise is reduced.

  However, the distance between the first and second internal electrodes 20 and 22 in the ceramic body 12, that is, the thickness of the dielectric layer 40 is 3 μm or less, and the number of grains in the dielectric layer 40 is ten. In the multilayer ceramic capacitor 10 described above, the acoustic noise reduction effect was significantly reduced.

  This can be seen more clearly from Table 1 below.

  Here, the sample to be tested was manufactured as follows.

First, a plurality of ceramic greens manufactured to a thickness required for various experimental conditions by applying and drying a slurry containing a powder such as barium titanate (BaTiO ₃ ) on a carrier film. A sheet was prepared, and a dielectric layer was formed from the ceramic green sheet.

  Thereafter, an internal electrode is formed from the conductive paste for nickel internal electrode on the ceramic green sheet using a screen, and then laminated to 370 layers, and the ceramic laminate is formed while varying the thickness of the cover layer from 10 μm to 100 μm. Manufactured.

Next, the ceramic laminate was isostatic pressing at 85 ° C. under a pressure condition of 1000 kgf / cm ² .

Next, the ceramic laminate after the press bonding was cut into individual chips, and the binder was removed by maintaining the cut chips at 230 ° C. for 60 hours in an air atmosphere. Subsequently, firing was performed in a reducing atmosphere having an oxygen partial pressure of 10 ⁻¹¹ to 10 ⁻¹⁰ atm lower than the equilibrium oxygen partial pressure of Ni / NiO so that the internal electrode was not oxidized at 1200 ° C. The size of the chip after firing is 3.2 mm × 1.6 mm × 1.6 mm (L × W × T), and the thickness td of the dielectric layer and the grain size Dc are as shown in Table 1 above. .

  Referring to Table 1, as shown in Samples 1 to 4, when the dielectric thickness is 4.3 μm and the grain size is reduced to reduce the dielectric constant, the size of the vibration sound is significantly reduced. I understand that However, as shown in samples 5 to 12, when the dielectric thickness is about 3 μm or less and the grain size is reduced to reduce the dielectric constant, td / Dc, that is, relative to the thickness of the dielectric It can be seen that even if the grain size ratio is 1/10 or less, the effect of reducing vibration noise is small.

  Therefore, when the dielectric is thin, it can be understood that the effect of reducing the vibration noise can be increased only by adding another condition in addition to the reduction of the grain size.

  According to an embodiment of the present invention, as shown in FIG. 3, the first and second external electrodes 14 and 16 formed at both ends in the length direction of the ceramic body 12 are first to eighth. The band part can be included.

  The first and second external electrodes 14 and 16 may be formed at both ends in the length direction of the rectangular parallelepiped ceramic body 12. The first and second external electrodes 14 and 16 have different polarities and are electrically connected to the first internal electrode 22 and the second internal electrode 24 facing each other through the dielectric layer 42. Can.

  In FIG. 3, the first band portion 142 and the second band portion 162 formed on the first surface 126, and the third band portion 144 and the fourth band formed on the second surface 125 are shown. Portion 164, fifth band portion 146 and sixth band portion 166 formed on the third surface 128, and seventh band portion 148 and eighth band portion 168 formed on the fourth surface 127. It is shown.

  The first to eighth band portions 142, 144, 146, 148, 162, 164, 166, 168 extend from the first and second outer electrodes 14, 16 to the inside in the length direction L, and L− The first surface 126 and the third surface 128 on the W plane and the second surface 125 and the fourth surface 127 on the LT plane can be formed to face each other. Here, the first surface 126 and the third surface 128 correspond to each other in the stacking direction, and the second surface 125 and the fourth surface 127 correspond to each other in the width direction.

  The lengths of the band portions 142 and 162 of at least one surface 126 of the first to fourth surfaces 126, 125, 127, and 128 can be different.

  Further, the lengths of the band portions 142 and 144 of the other one surface 125 that are continuous with the same polarity as at least one surface 126 of the first to fourth surfaces 126, 125, 127, and 128 can be different.

  Hereinafter, a method for measuring the lengths A1 and A2 of the band portions 142 and 162 will be described with reference to FIG.

  FIG. 6 is a cross-sectional view schematically showing a cross section in the length direction and the thickness direction (LT) along the center portion in the width direction W of the ceramic body 12 as shown in FIG.

  Referring to a cross section in the LT direction of the ceramic body 12, the length A1 of the first band portion 142 of the first external electrode 14 is the upper and lower end surfaces 126 and 128 in the thickness direction of the ceramic body 12. A distance from an imaginary line XX ′ extending perpendicular to the thickness direction with reference to a center line C connecting the center points Cp1 and Cp2 between the first band portion 142 and the innermost L direction. it can.

  The length A2 of the second band portion 162 is from a virtual line YY ′ extending perpendicular to the thickness direction with respect to the center line C to the innermost side in the L direction of the second band portion 162. Can be a distance.

  Further, the lengths of the band portions 144, 146, 148, 164, and 166 other than the first band portion 142 and the second band portion 162 can be measured in the same manner as described above.

  The reason for using such a measurement method is that it is difficult for each side of the hexahedron of the ceramic body 12 to have an accurate linear shape by firing.

According to the embodiment of the present invention, the first to eighth band portions of the chip-type multilayer ceramic capacitor 10 are configured under the following conditions (1) in order to realize miniaturization and high capacity and reduce acoustic noise. ) To (4) can be satisfied.

  Here, BWave1 is an average value of the lengths of the first and second band portions, and BWave1 = (A1 + A2) / 2, and BWave2 is an average value of the lengths of the third and fourth band portions. BWave2 = (B1 + B2) / 2, BWave3 is the average value of the lengths of the fifth and sixth band portions, and BWave3 = (C1 + C2) / 2, and BWave4 is the seventh and eighth The average value of the length of the band part is BWave4 = (D1 + D2) / 2, A1 is the length of the first band part, A2 is the length of the second band part, and B1 is The length of the third band part, B2 is the length of the fourth band part, C1 is the length of the fifth band part, and C2 is the length of the sixth band part. D1 is the length of the seventh band part, and D2 is the eighth Of the command part is the length.

  If each of the BWave1 / L, BWave2 / L, BWave3 / L, and BWave4 / L is less than 3%, the strength of fixing the chip-type multilayer ceramic capacitor 10 to the circuit board may be reduced, resulting in poor mounting. If it exceeds 40%, mounting failure may occur due to a short circuit between both terminals during mounting.

In one embodiment of the present invention, the absolute value of the difference in length of the band portion on one surface of the ceramic body 12 and the BWave1 to BWave4 satisfy at least one of the following conditions (5) to (8): Can be satisfied.

  Here, A1 is the length of the first band part, A2 is the length of the second band part, B1 is the length of the third band part, and B2 is the fourth band part. C1 is the length of the fifth band portion, C2 is the length of the sixth band portion, and D1 is the length of the seventh band portion. , D2 is the length of the eighth band portion, and C1 ≠ C2 and D1 ≠ D2.

  According to the above formulas (5) to (8) showing the relationship between the absolute value of the difference in length of the band part on one surface of the ceramic body 12 and the BWave1 to BWave4, the asymmetry rate of the band width part is defined. Can do.

  As the asymmetry ratio of the respective bandwidth portions increases, vibration transmission to the substrate decreases due to force variation, so that vibration noise is significantly reduced.

  When at least one of the asymmetry ratios of the respective bandwidth portions is less than 5%, the vibration noise is too high, and when it exceeds 20%, a tombstone mounting defect in which the chip rises on the circuit board occurs.

  Hereinafter, embodiments of the present invention will be described more specifically with reference to experimental data of examples and comparative examples of the present invention.

Experimental Example Multilayer ceramic capacitors according to examples and comparative examples of the present invention were manufactured as follows.

First, a plurality of ceramic green sheets manufactured to a thickness of 3.9 μm are prepared by applying and drying a slurry formed containing a powder such as barium titanate (BaTiO ₃ ) on a carrier film. did.

  Thereafter, an internal electrode was formed by applying a conductive paste for nickel internal electrode using a screen for forming a marginal asymmetric pattern on the ceramic green sheet.

Next, the ceramic green sheets were laminated in 370 layers, and the laminated body was subjected to isostatic pressing at 85 ° C. under a pressure condition of 1000 kgf / cm ² .

  Next, the ceramic laminate after the press bonding was cut into individual chips, and the binder was removed by maintaining the cut chips at 230 ° C. for 60 hours in an air atmosphere.

Subsequently, firing was performed in a reducing atmosphere having an oxygen partial pressure of 10 ⁻¹¹ to 10 ⁻¹⁰ atm lower than the equilibrium oxygen partial pressure of Ni / NiO so that the internal electrode was not oxidized at 1200 ° C. The thickness of the dielectric layer after firing is 2.7 μm, the average grain size of the dielectric layer after firing is 0.27 μm, and the size of the chip after firing is 3.2 mm × 1. It was 6 mm × 1.6 mm (L × W × T).

  Thereafter, a multilayer ceramic capacitor was manufactured through an external electrode forming process, a plating process, and the like.

  Here, various samples of the multilayer ceramic capacitor were manufactured according to the asymmetry rate of the band portion of the external electrode.

  Tables 2 and 3 below compare the vibration noise due to the asymmetry rate of the band portion of the external electrode and the mounting defect rate. The vibration sound was measured directly in an anechoic chamber by applying a 3Vpp pulse wave to a DC voltage corresponding to 1/2 of the rated voltage, and the mounting failure rate was tested for 100 samples. This is done by judging the presence / absence of a defect based on the presence / absence of appearance defects, fixing strength, electrical characteristics, and the like.

※＊：比較例、Ａ１〜Ｄ２：第１から第８のバンド部の長さ、Ｘ１：ＢＷａｖｅ１／Ｌ、Ｘ２：ＢＷａｖｅ２／Ｌ、Ｘ３：ＢＷａｖｅ３／Ｌ、Ｘ４：ＢＷａｖｅ４／Ｌ、ＢＷａｖｅ：バンド幅部の平均値を示す関数、Ｌ：外部電極を除いたセラミック本体の長さ方向の両端部間の距離

**: Comparative example, A1 to D2: Length of first to eighth band portions, X1: BWave1 / L, X2: BWave2 / L, X3: BWave3 / L, X4: BWave4 / L, BWave: Band width A function indicating the average value of the part, L: distance between both ends in the length direction of the ceramic body excluding the external electrode

  Samples 1 and 6 are comparative examples, and samples 2 to 5 are examples.

  In the samples 2 to 5 of the embodiment of the present invention, when at least one of the above-described X1 to X4 satisfies the range of 3 to 40%, a low vibration sound of 36 dB or less is generated, and the mounting failure on the circuit board is completely eliminated. Disappear.

  On the other hand, in the case of the sample 1 in which the asymmetry ratios X1 to X4 of the band part are less than 3%, there is a problem that the vibration sound becomes larger than 40 dB, and in the case of the sample 6 exceeding 40%, the vibration sound is reduced. Is effective, but a mounting defect is remarkably generated.

  From the above, it can be seen that the embodiment of the present invention can significantly reduce the vibration noise and reduce the mounting defect rate as compared with the comparative example.

  Samples 1, 2, 7 and 8 are comparative examples, and samples 3 to 6 are examples.

  In Samples 3 to 6 of the examples of the present invention, at least one of Y1 to Y4 indicating the asymmetry rate of the band portion in terms of the absolute value of the difference in length of the band portion and the average of the band width portion is 5 to 20 When the range of% is satisfied, a low vibration noise of 35 dB or less is generated, and mounting defects on the circuit board are completely eliminated.

  On the other hand, in the case of samples 1 and 2 in which the asymmetry ratios Y1 to Y4 of the band part are less than 5%, there is a problem that the vibration noise is increased to 40 dB or more, and in the case of samples 7 and 8 exceeding 20%, Although effective in reducing vibration noise, poor tombstone mounting occurs significantly.

  From the above, it can be seen that the embodiment of the present invention can significantly reduce the vibration noise and reduce the mounting defect rate as compared with the comparative example.

Modified Example FIG. 4 (a) and (b) is a schematic perspective view showing an enlarged A and B in FIG. 1, FIG. 5 is a schematic sectional view showing an enlarged manner of the band portion of the external electrode It is.

  In the embodiment shown in FIGS. 4 and 5, a difference in height is set in addition to the difference in length between the band portions 142 and 162 of the external electrode.

  The heights of the band portions 142 and 162 of the external electrode are measured by measuring the distance between the horizontal imaginary line of the highest points hmax1 and hmax2 of the band portions 142 and 162 of the external electrode and the horizontal phantom line of the one surface 126 of the ceramic body 12. It is decided by doing.

  From the above, it is possible to reduce vibration noise due to variations in the height of the band portions 142, 162 and to reduce vibration noise due to variations in the length of the band portions 142, 162.

10 Chip Multilayer Capacitors 14, 16 First and Second External Electrode 20 Internal Electrode 40 Dielectric Layer 42 Grain

Claims (9)

A ceramic body including a dielectric layer formed with a thickness of not less than 10 times the average grain size and not more than 3 μm;
First and second external electrodes formed on both end faces of the ceramic body in the length direction;
First and second band portions extending from the first and second external electrodes on the lengthwise inner side in the longitudinal direction of the ceramic body × width plane, and having different lengths,
Third and fourth band portions extending from the first and second external electrodes on the lengthwise inner side of the ceramic body × thickness plane and having different lengths,
Including
The lengths of the first band part and the third band part that are continuous with the same polarity are different, or the lengths of the second band part and the fourth band part that are continuous with the same polarity are different. And
Fifth and sixth band portions are formed on one surface of the ceramic body on which the first and second band portions are formed and on the other surface corresponding to the stacking direction,
Seventh and eighth band portions are formed on one surface of the ceramic body on which the third and fourth band portions are formed and on the other surface corresponding to the width direction,
A chip-type multilayer capacitor that satisfies at least one of the following conditions (1) to (4) .

Here, BWave1 is an average value of the lengths A1 and A2 of the first and second band portions, and BWave1 = (A1 + A2) / 2, and BWave2 is the length of the third and fourth band portions. The average value of B1 and B2 is BWave2 = (B1 + B2) / 2, and BWave3 is the average value of the lengths C1 and C2 of the fifth and sixth band portions, and BWave3 = (C1 + C2) / 2, and BWave4 Is the average value of the lengths D1 and D2 of the seventh and eighth band portions, and BWave4 = (D1 + D2) / 2, and L is between the lengthwise ends of the ceramic body excluding the external electrodes The distance, A1 is the length of the first band part, A2 is the length of the second band part, B1 is the length of the third band part, and B2 is the fourth band part. The length of the band part, C1 is the fifth band The length of the section, C2 is the length of the band portion of the 6, D1 is the length of the band portion of the 7, D2 is the length of the band portion of the eighth. 2. The chip type according to claim 1 , wherein an absolute value of a difference in length of the band portion on one surface of the ceramic body and the BWave1 to BWave4 satisfy at least one of the following conditions (5) to (8). Multilayer capacitor.

Here, A1 is the length of the first band part, A2 is the length of the second band part, B1 is the length of the third band part, and B2 is the fourth band part. C1 is the length of the fifth band portion, C2 is the length of the sixth band portion, and D1 is the length of the seventh band portion. , D2 is the length of the eighth band portion, and C1 ≠ C2 and D1 ≠ D2. Including a dielectric layer formed with a thickness of 10 μm or more and 3 μm or less of the average grain size of grains, and a hexahedral ceramic body ;
First and second external electrodes formed at both ends in the length direction of the ceramic body ;
First and second band portions formed to extend from the first and second external electrodes on the length × width plane of the ceramic body in the longitudinal direction;
Third and fourth band portions formed to extend from the first and second external electrodes on a length × thickness plane inside the length direction of the ceramic body,
Including
Fifth and sixth band portions are formed on one surface of the ceramic body on which the first and second band portions are formed and on the other surface corresponding to the stacking direction,
Seventh and eighth band portions are formed on one surface of the ceramic body on which the third and fourth band portions are formed and on the other surface corresponding to the width direction,
At least one of the first to fourth surfaces is different in the length of opposing band portions on the same surface and is continuous with the same polarity as the band portion of at least one surface of the first to fourth surfaces. The length of the band part of the
A chip-type multilayer capacitor that satisfies at least one of the following conditions (1) to (4) .

Here, BWave1 is an average value of the lengths A1 and A2 of the first and second band portions, and BWave1 = (A1 + A2) / 2, and BWave2 is the length of the third and fourth band portions. The average value of B1 and B2 is BWave2 = (B1 + B2) / 2, and BWave3 is the average value of the lengths C1 and C2 of the fifth and sixth band portions, and BWave3 = (C1 + C2) / 2, and BWave4 Is the average value of the lengths D1 and D2 of the seventh and eighth band portions, and BWave4 = (D1 + D2) / 2, and L is between the lengthwise ends of the ceramic body excluding the external electrodes The distance, A1 is the length of the first band part, A2 is the length of the second band part, B1 is the length of the third band part, and B2 is the fourth band part. The length of the band part, C1 is the fifth band The length of the section, C2 is the length of the band portion of the 6, D1 is the length of the band portion of the 7, D2 is the length of the band portion of the eighth. The chip-type multilayer capacitor according to claim 3 , wherein the first band portion of the first surface and the third band portion of the second surface are different in length. 4. The chip type multilayer capacitor according to claim 3 , wherein the lengths of the band portions of the first to fourth surfaces facing each other with the same polarity are the same or different. 5. 4. The chip multilayer capacitor according to claim 3 , wherein at least one of the first to fourth surfaces has a difference in height between opposing band portions on the same surface. 5. 4. The chip type according to claim 3 , wherein an absolute value of a difference in length of the band portion on one surface of the ceramic body and the BWave1 to BWave4 satisfy at least one of the following conditions (5) to (8). Multilayer capacitor.

Here, A1 is the length of the first band part, A2 is the length of the second band part, B1 is the length of the third band part, and B2 is the fourth band part. C1 is the length of the fifth band portion, C2 is the length of the sixth band portion, and D1 is the length of the seventh band portion. , D2 is the length of the eighth band portion, and C1 ≠ C2 and D1 ≠ D2. A ceramic body including first and second internal electrodes disposed via a dielectric layer having a thickness of 3 μm or less;
First and second external electrodes formed at both ends in the length direction of the ceramic body and connected to the first and second internal electrodes, respectively;
Including
The number of grains disposed between the first and second internal electrodes is 10 or more in the thickness direction of the dielectric layer,
First and second band portions formed to extend from the first and second external electrodes on the length × width plane of the ceramic body in the longitudinal direction;
Third and fourth band portions formed to extend from the first and second external electrodes on a length × thickness plane inside the length direction of the ceramic body,
Including
Fifth and sixth band portions are formed on one surface of the ceramic body on which the first and second band portions are formed and on the other surface corresponding to the stacking direction,
Seventh and eighth band portions are formed on one surface of the ceramic body on which the third and fourth band portions are formed and on the other surface corresponding to the width direction,
At least one of the first to fourth surfaces is different in the length of opposing band portions on the same surface and is continuous with the same polarity as the band portion of at least one surface of the first to fourth surfaces. The chip-type multilayer capacitor has different band lengths and satisfies at least one of the following conditions (1) to (4).

Here, L is the distance between both ends in the length direction of the ceramic body excluding the external electrode, BWave1 is the average value of the lengths of the first and second band portions, and BWave1 = (A1 + A2) / 2 BWave2 is an average value of the lengths of the third and fourth band portions, and BWave2 = (B1 + B2) / 2, and BWave3 is an average value of the lengths of the fifth and sixth band portions. BWave3 = (C1 + C2) / 2, and BWave4 is an average value of the lengths of the seventh and eighth band portions, and BWave4 = (D1 + D2) / 2. 9. The chip type according to claim 8 , wherein an absolute value of a difference in length of the band portion on one surface of the ceramic body and the BWave1 to BWave4 satisfy at least one of the following conditions (5) to (8). Multilayer capacitor.

Here, A1 is the length of the first band part, A2 is the length of the second band part, B1 is the length of the third band part, and B2 is the fourth band part. C1 is the length of the fifth band portion, C2 is the length of the sixth band portion, and D1 is the length of the seventh band portion. , D2 is the length of the eighth band portion, and C1 ≠ C2 and D1 ≠ D2.

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