JP6003136B2 - Data relay device - Google Patents

Description

  The present invention relates to a data relay device that relays data between devices.

  PCI (Peripheral Component Interconnect) Express (hereinafter abbreviated as “PCIe”), which is a standard for local buses, is widely known as a standard for high-speed data transfer buses used in communications within PCs, servers, and embedded devices. ing. For example, Patent Document 1 shows that the structure of the PCIe standard includes three layers: a physical layer, a data link layer, and a transaction layer.

  The transaction layer receives a request (read / write request) issued from the CPU or device, converts it to a transaction layer packet (transaction layer packet, hereinafter referred to as TLP) including a header, data, and ECRC, and transfers it to the data link layer To do. The data link layer has a function of maintaining data integrity in order to reliably transmit packets via the PCIe link, and adds a sequence number and LCRC to the TLP received from the transaction layer. A link layer packet (Datalink Layer Packet, hereinafter referred to as DLLP) is created and transferred to the physical layer. The sequence number is used to confirm whether or not all the packets have arrived, and the LCRC confirms whether or not the contents of the packets have changed in the data link layer on the packet receiving side. The physical layer has a function of adding a framing symbol to the beginning and end of the DLLP received from the data link layer and transferring the packet as serial data.

  A conventional operation concept of PCIe having the three-layer structure as described above will be described. In FIG. 17, in the data relay device 100, a PCIe circuit 100a that is located on the left side in the figure and connected to an upstream device, and a PCIe circuit 100b that is located on the right side in the figure and is connected to a downstream device. And have. A case where the TLP is received from the PCIe circuit 100a and relayed to the PCIe circuit 100b will be described below.

  When the TLP from the transmission source device arrives at the reception port RX of the PCIe circuit 100a, the error detection unit 101a refers to a CRC (Cyclic Redundancy Check) value to determine whether or not an error is included in the TLP. Do. When it is determined that there is no TLP error, the error detection unit 101a transfers an ACK packet to the transmission port TX of the PCIe circuit 100a. On the other hand, if it is determined that there is a TLP error, the error detection unit 101a transfers the Nak packet to the transmission port TX of the PCIe circuit 100a and discards the received TLP.

  When no TLP error is detected, the TLP is converted into a command and data (memory write, read, data, etc.) for the port arbitration circuit 103 and stored in the reception buffer 102a. When the transfer of the TLP command and data to the port arbitration circuit 103 is completed, the reception flow control unit 104a has a space in the reception buffer 102a. The packet is transmitted to the transmission port TX of the Pice circuit 100a.

  The port arbitration circuit 103 stores the TLP command and data received from the PCIe circuit 100a in the transmission buffer 105b of the PCIe circuit 100b. The transmission flow control unit 106b determines whether or not the capacity of the storage buffer (not shown) of the downstream device is empty, and transmits from the transmission port TX of the PICE circuit 100b only when the storage buffer is empty. The TLP stored in the buffer 105b is output. The free space in the storage buffer of the downstream device is managed based on the credit information notified by the data flow control (FC) packet from the downstream device. The FC packet is received from the reception port RX of the Pice circuit 100b, and the credit information extracted by the credit detection unit 107b is notified to the transmission flow control unit 106b of the Pice circuit 100b.

  The retransmission buffer 108b duplicates and stores the output TLP in order to perform retransmission when there is an error such as a missing TLP output from the transmission port TX. Thereafter, whether or not the TLP is normally received from the downstream device is notified by an ACK (Acknowledge) packet or a Nak (Negative Acknowledgment) packet. The ACK / Nak detection unit 109b confirms the notified ACK packet and Nak packet, and notifies the retransmission buffer control unit 110b which packet of ACK or Nak has been received. When the ACK is notified, the retransmission buffer control unit 110b instructs that the TLP copy stored in the retransmission buffer 108b be discarded and the Nak is notified because the TLP has normally reached the downstream device. If the TLP is received, the TLP stored in the retransmission buffer 108b is instructed to be transmitted again.

  Data relaying is performed by performing the above-described packet transfer bidirectionally and simultaneously in parallel between the PCIe circuits 100a and 100b. In the high-speed serial system based on packet transfer, a transmission buffer, a reception buffer, and a retransmission buffer are provided to perform data transfer, data guarantee by retransmission when an error occurs, and flow control.

  Next, the configuration and operation of the reception buffers 102a and 102b will be described with reference to FIG. The reception buffers 102a and 102b are composed of a total of six buffers in which three types of buffers P: Posted, NP: Non-Posted, and Cpl: Completion are each divided into a header area and a data area.

  P stores a request (memory write or the like) that does not expect a response from the destination device, NP stores a request (memory read or the like) that expects a response from the destination device, and Cpl responds to the NP request A packet (such as memory read data responded to a memory read request) is stored.

  The reception buffers 102a and 102b receive the TLP transferred from the data link layer, and convert the TLP into a command and data format to the port arbitration circuit 103 and transfer it when output. Whether the TLP input to the reception buffers 102a and 102b corresponds to P, NP, or Cpl is determined from the header information and stored in the corresponding buffer area. In FIG. 17, P packet 1, NP packet 2, and Cpl packet 3 are input in this order, and each packet is stored in a corresponding buffer. The packet stored in the corresponding buffer is output to the port arbitration circuit 103 for each TLP type (P, NP, Cpl), with header information as a command from the transaction layer and data as data from the transaction layer. .

  The reception buffers 102 a and 102 b output credit information corresponding to the consumed capacity when the header and data are stored in the buffer, while the header and data are output to the port arbitration circuit 103. The credit information corresponding to the increased capacity due to the empty space is output. The reception flow control units 104a and 104b transfer credit information as FC packets.

  Next, the configuration and operation of the transmission buffers 105a and 105b will be described with reference to FIG. Similarly to the reception buffers 102a and 102b, the transmission buffers 105a and 105b are composed of a total of six buffers in which three types of buffers P: Posted, NP: Non-Posted, and Cpl: Completion are each divided into a header area and a data area. ing.

  Commands and data transmitted from the port arbitration circuit 103 to the transaction layer are input to the transmission buffers 105a and 105b. The command is stored in the header buffer for each P, NP, and Cpl, and the data is stored in the transmission buffer 105a and 105b. Each is stored in a data buffer. The transmission buffers 105a and 105b output to the transmission flow control units 106a and 106b.

  The transmission flow control units 106a and 106b are notified of credit information indicating the free capacity of the storage buffer of the transmission destination device from the credit detection units 107a and 107b of the data link layer, and when the transmission destination device buffer has a free space The corresponding header and data are selected, a TLP is generated and transferred to the data link layer.

  However, in the relay device described above, the PCIe circuit requires a transaction layer in which a plurality of packet buffers and a complex flow control circuit are mounted in order to process packet relay and flow control. The circuit of the transaction layer is much larger than the data link layer, and it is necessary to mount a circuit for each type of P, NP, and Cpl packets, which increases the cost of the circuit chip. It was also.

  In addition, the operation of the transaction layer is linked to the data link layer and the flow control processing, and it is not possible to operate a circuit having a port configuration of only the physical layer and the data link by deleting only the transaction layer. It was possible. Furthermore, it is possible to reduce the circuit scale with a data relay circuit with only the physical layer without the transaction layer and data link layer, but in that case, the error detection and data retransmission functions of the data link layer are lost. As a result, there is a problem that the data transfer efficiency decreases when it takes time to transmit ACK / Nak, such as when a long cable is used.

  The present invention has been made in view of the above, and it is an object of the present invention to provide a data relay device capable of reducing the circuit scale without impairing error detection and data retransmission functions.

To solve the above problems and achieve the object, the present invention includes a first port connected to the first device, and a second port connected to the second device and connection data a relay device, a storage unit that stores data flow control packet, and data packets, the first port or the second port or we received the data flow control packet, and the data packet A write control unit that controls writing to the storage unit, the data flow control packet written to the storage unit , and the data packet are read asynchronously with the write timing, the first port, or a read control unit to be transmitted to the second port, the first device of the data packets transmitted destination, or whether it is successfully transmitted to the second device When it is determined that the data packet has been transmitted, the data packet transmitted from the storage unit is deleted, and when it is determined that the data packet has not been transmitted, the data packet is read from the storage unit and retransmitted. And a retransmission control unit for instructing.

  According to the present invention, there is an effect that the circuit scale can be reduced without impairing the error detection or data retransmission function.

FIG. 1 is a conceptual diagram of a communication system that performs information communication conforming to the PCIe cable standard between two hosts according to the embodiment. FIG. 2 is a diagram illustrating a specific configuration example of the cable connection unit of the communication system according to the embodiment. FIG. 3 shows a data flow when the first device executes data transfer that requires a communication band corresponding to 5 lanes of PCIe to the second device in the configuration of the cable connection unit of the communication system of the embodiment. It is a figure which shows an example. FIG. 4 is a diagram illustrating a configuration example of the PCIe relay circuit according to the embodiment. FIG. 5 is a diagram illustrating a packet structure of the TLP and the DLLP according to the embodiment. FIG. 6 is a conceptual diagram illustrating the configuration and operation of the retransmission buffer according to the embodiment. FIG. 7 is a diagram illustrating an operation of the PCIe relay device according to the embodiment. FIG. 8 is a diagram illustrating an operation of the PCIe relay device according to the embodiment. FIG. 9 is a diagram illustrating an operation of the PCIe relay device according to the embodiment. FIG. 10 is a diagram illustrating an operation of the PCIe relay device according to the embodiment. FIG. 11 is a diagram illustrating an operation of the PCIe relay device according to the embodiment. FIG. 12 is a diagram illustrating an operation of the PCIe relay device according to the embodiment. FIG. 13 is a diagram illustrating an operation of the PCIe relay device according to the embodiment. FIG. 14 is a flowchart illustrating a processing flow in the transmission port of the embodiment. FIG. 15 is a flowchart illustrating a processing flow in the reception port according to the embodiment. FIG. 16 is a flowchart illustrating a flow of processing in the retransmission buffer according to the embodiment. FIG. 17 is a conceptual diagram showing a configuration example of a conventional PCIe relay circuit. FIG. 18 is a conceptual diagram illustrating a configuration example of a reception buffer in a conventional PCIe relay circuit. FIG. 19 is a conceptual diagram illustrating a configuration example of a transmission buffer in a conventional PCIe relay circuit.

  Embodiments of a data relay device will be described below in detail with reference to the accompanying drawings.

  FIG. 1 is a conceptual diagram of a communication system that performs information communication based on the PCIe cable standard between two hosts. The communication system shown in FIG. 1 is a communication system in which a first device A and a second device B are communicably connected. The first device A is a host including a CPU 1a that is a control subject. The second device B is a host including a CPU 1b that is a control subject. Each of the first device A and the second device B is provided with a PCIe card slot. PCIe cable interface boards are mounted in the PCIe card slots of the first device A and the second device B. Then, the PCIe cable interface board of the first device A and the PCIe cable interface board of the second device B are connected by, for example, a multi-lane cable including a plurality of cables.

  Returning to FIG. 1, the first device A includes a PCIe relay circuit 10a. The upstream port 11a of the PCIe relay circuit 10a is connected to the root complex 2a. The downstream port 11b of the PCIe relay circuit 10a is connected to the end point 2b in the second device B.

  FIG. 2 is a diagram illustrating a specific configuration example of a cable connection unit which is a part related to data transfer via a cable of the communication system according to the present embodiment. In the communication system according to the present embodiment, the PCIe cable interface board 20a attached to the first device A and the PCIe cable interface board 20b attached to the second device B include x8 corresponding to 8 lanes of PCIe. The configuration is connected by a metal cable 21. In the present embodiment, the communication system according to the present embodiment is not limited to the x8 configuration, and can be configured to support various numbers of lanes.

  In the present specification, the suffix “a” is added to the reference symbol of the component of the first device A, and the suffix “b” is added to the reference symbol of the component of the second device B to distinguish them.

  The PCIe relay device 10 is mounted on the PCIe cable interface board 20a attached to the first device A. The PCIe relay device 10 includes an x8 upstream port 11a. The x8 upstream port 11a is connected to the x8 port of the root complex 2a via an x8 card edge connector (not shown). Further, the PCIe relay device 10 includes an x8 downstream port 11b. Each x8 port 11b is connected to eight metal cables 21 corresponding to one lane of PCIe (hereinafter referred to as “x1”). A repeater 23 a is provided between each lane of the downstream port 11 b of the PCIe relay device 10 and the metal cable 21. The repeater 23a performs electric signal amplification and shaping processing. In addition, since one lane of PCIe transmits information by differential signals using two signal lines for reception and transmission, four signal lines are required per lane. In this embodiment, one cable is used. A description will be given assuming that these four signal lines are included.

  The PCIe cable interface board 20b attached to the second device B is connected to the x8 port of the end point 2b and the eight metal cables 21. A repeater 23b is provided between each lane of the x8 port of the end point 2b and the metal cable 21. Similar to the repeater 23a, the repeater 23b performs electric signal amplification and shaping processing.

  In the example shown in FIG. 2, the first device A and the second device B are connected to the metal cable 21, but an optical cable may be used instead of the metal cable 21. When an optical cable is used instead of the metal cable 21, the repeaters 23a and 23b are replaced with optical transceivers. The optical transceiver performs conversion between an electrical signal and an optical signal.

  FIG. 3 shows a case where the first device A performs data transfer that requires a communication band corresponding to 5 lanes of PCIe to the second device B in the configuration of the cable connection unit of the communication system shown in FIG. It is a figure which shows an example of this data flow. In the example illustrated in FIG. 3, the first device A executes data transfer using five DMACs (Direct Memory Access Controllers) 24. In FIG. 3, only the first device A side of the cable connection portion is illustrated, and an arrow indicated by a broken line in the drawing indicates a data flow in the first device A.

  The first device A is equipped with five DMACs 24. Each DMAC 24 has a data transfer performance of x1. Each DMAC 24 reads data from the memory 25 provided in the first device A, divides the read data into packets, and transfers the packets to the x8 port of the root complex 2a via the internal bus. The x8 port of the route complex 2a divides the packet received from the DMAC 24 into 8 bits each and distributes it evenly over all 8 lanes, and the x8 upstream port 11a of the PCIe relay device 10 mounted on the PCIe cable interface board 20a. Forward to. The PCIe relay device 10 converts the data divided into 8 bits into each lane of the x8 upstream port 11a and converts it again into packet data, and transfers it to the x8 downstream port 1 and b. The x8 downstream port 11b again divides the received packet into 8 bits, distributes it evenly over all 8 lanes, and transfers it to the second device B side via the 8 metal cables 21.

  On the second device B side (not shown), the data transmitted after being divided into 8 bits for each x8 lane at the x8 port of the endpoint 2b is converted back into packet data again, and the second device B The data is transferred to the memory included in B.

  As described above, in the conventional communication system, even when data transfer that requires a communication band corresponding to 5 lanes of PCIe is executed, if the configuration is x8, data transfer is executed using all 8 lanes. I have to.

  Next, the configuration of the data relay apparatus will be described with reference to FIG. FIG. 4 is a conceptual diagram illustrating an example of the configuration of the two PCIe relay circuits 10a and 10b constituting the PCIe device. As shown in FIG. 3, the PCIe relay circuits 10a and 10b include two relay circuits having a two-layer structure of physical layers 30a and 30b and data link layers 40a and 40b. Between the data link layers 40a and 40b, packet retransmission buffers (storage units) 50a and 50b in which writing and reading of data operate asynchronously are logically connected.

  The physical layers 30a and 30b of the relay circuits 10a and 10b send signals to the reception port RX that receives input of signals from the first device A and the second device B, and to the first device A and the second device B. The transmission port TX is provided. The data link layers 40a and 40b of the relay circuits 10a and 10b include retransmission buffers 50a and 50b (corresponding to a storage unit), error detection units 51a and 51b, FC detection units 52a and 52b, and an ACK / Nak detection unit. 53a and 53b, and retransmission buffer controllers 54a and 54b, respectively.

  In the relay circuits 10a and 10b, a transaction layer packet (TLP) that is a data packet, a DLLLP ACK / Nak packet (hereinafter, “ACK / Nak packet”) that is an error control packet, and a DLLP that is a data flow control packet. FC packets (hereinafter “FC packets”) are transmitted and received. The TLP is a packet that handles a transaction involving data transfer with the application layer of a destination device such as memory write, memory read, and completion issued by each device.

  FIG. 5 is a conceptual diagram showing the data structure of TLP. As shown in FIG. 5A, the TLP includes a header area, a data area (payload), a PSN (Packet Sequence Number), and an LCRC (Link Cyclic Redundancy Check). The PSN is an identification number for identifying a packet, and a unique number is assigned to each packet. The PSN is used to identify which packet has an error when an error occurs during packet transfer. The LCRC is an area used for error detection, and is a result of calculating a CRC value for the header area and the data area.

  As shown in FIG. 5B, the DLLP includes a Type area indicating the type of DLLP, a data area, and a CRC. The Type area indicates which of the ACK packet, Nak packet, or FC packet is the type of DLLP. The data differs depending on the type of DLLP. For example, the ACK / Nak packet includes PSN, and the FC packet includes credit information and VC (Virtual Channel) number used for flow control. The CRC includes values calculated for the Type area and the data area.

  When the TLP or FC packet is input to one of the PCIe relay circuits 10a and 10b, the data link layers 40a and 40b transfer the packet to the other PCIe relay circuit 10a and 10b via the retransmission buffers 50a and 50b. To do. The data link layers 40a and 40b perform error control when an ACK / Nak packet is input to the PCIe relay circuits 10a and 10b.

  The error detection units 51a and 51b check the TLP and FC packets to determine whether there is an error. If there is an error, the error detection unit 51a or 51b requests the source device to retransmit the packet, If not, the packet is deleted and an ACK packet is transmitted to the transmission port TX of the transmission source device.

  Next, a specific configuration of the retransmission buffers 50a and 50b will be described with reference to FIG. FIG. 6 is a conceptual diagram conceptually showing the configuration and operation of the retransmission buffers 50a and 50b. As shown in FIG. 6, TLP and DLLP are mixedly stored in retransmission buffers 50a and 50b. The DLLP transferred to the retransmission buffers 50a and 50b is only an FC packet for flow control because an error control ACK / Nak packet is processed in the error detection units 51a and 51b. The TLP stored in the retransmission buffers 50a and 50b is stored in a format in which PSN and LCRC information added in the data link layers 40a and 40b of the PCIe relay circuits 10a and 10b on the transmission source device side are retained. . Similarly, the DLLP is stored in a format generated by the data link layers 40a and 40b of the PCIe relay circuits 10a and 10b on the transmission source device side.

  The retransmission buffers 50a and 50b receive packet inputs from the error detection units 51a and 51b of the source-side PCIe relay circuits 10a and 10b, and transmit the physical layers 30a and 30b of the destination-side PCIe relay circuits 10a and 10b. The received packet is transmitted to the port TX. The retransmission buffers 50a and 50b are in a FIFO (First in First Out) format in which packets are output in the order in which the packets are input. If the packet is a DLLP, the retransmission buffers 50a and 50b delete the packet from the buffer area after output and release the buffer area. When the packet is a TLP, the retransmission buffers 50a and 50b do not immediately release the buffer area, and are specified by the instructed PSN after receiving the TLP deletion instruction and the PSN from the retransmission buffer control units 54a and 54b described later. The buffer area in which the TLP input before the TLP to be stored is stored is released.

  On the other hand, when the retransmission buffers 50a and 50b receive the TLP retransmission instruction and the PSN from the retransmission buffer control units 54a and 54b, the retransmission buffers 50a and 50b retransmit the TLP stored in the buffer input after the instructed TLP. The retransmission buffers 50a and 50b receive the retransmission control signals (TLP deletion instruction and TLP retransmission instruction) from the retransmission buffer control units 54a and 54b provided in the packet relay PCIe relay circuits 10a and 10b as described above.

  The retransmission buffers 50a and 50b output buffer full signals to the error detection units 51a and 51b provided in the data link layers 40a and 40b of the source PCIe relay circuits 10a and 10b. The buffer full signal is output when the free space in the retransmission buffers 50a and 50b becomes a predetermined amount or less. Each time the transmission source error detection units 51a and 51b receive TLP from the transmission source device while the buffer full signal is being input, Nak is transmitted to the transmission port TX of the transmission source device regardless of the presence or absence of an error. Is output so that the capacity of the retransmission buffers 50a and 50b is not exceeded.

  Therefore, the retransmission buffers 50a and 50b can be stored in a single buffer regardless of the request type, header, and data of the packet, and no matter how many virtual channels are used, only the retransmission buffers 50a and 50b are implemented. Therefore, it is possible to process data relay with a very small circuit configuration as compared with a normal PCIe circuit mounted with a transaction layer. Note that the size of the retransmission buffers 50a and 50b can be changed according to the cable length to be used, and the retransmission buffer is only used for the time required until there is an ACK / Nak packet response from a device connected via the cable. If the size of the TLP can be stored and the size that can be stored by the TLP is mounted, it is preferable that the data transfer efficiency does not decrease.

  Next, an example of the operation of the PCIe circuit will be described in detail for each operation step using the data flow diagrams of FIGS. The numbers enclosed in “()” given in the figure indicate the flow of data and the order of processing.

  FIG. 7 shows a data flow when a TLP is received from a transmission source device and there is no error. In this figure, the device A connected to the PCIe relay circuit 10a is the transmission source, and the device B connected to the PCIe relay circuit 10b is the transmission destination. However, in the opposite case, the data flow is the same. First, (1) TLP is input from the reception port RX of the PCIe relay circuit 10a. (2) The error detection unit 51a checks the LCRC value of the input TLP and determines whether there is an error. If there is no error, the error detection unit 51a transmits an ACK packet from the transmission port TX to the transmission source device A. (3) The error detection unit 51a transfers the TLP to the retransmission buffer 50b of the PCIe relay circuit 10b and stores it in the retransmission buffer 50b. (4) The TLP stored in the retransmission buffer 50b is read out and transferred to the transmission port TX of the PCIe relay circuit 10b on the transmission destination side. At this time, the TLP remains stored without being deleted from the retransmission buffer 50b.

  FIG. 8 shows a data flow when a TLP is received from the transmission source device A and there is an error. In this figure, the device A connected to the PCIe relay circuit 10a is the transmission source, and the device B connected to the PCIe relay circuit 10b is the transmission destination. However, in the opposite case, the data flow is the same. (1) First, TLP is input from the reception port RX of the PCIe relay circuit 10a. (2) The error detection unit 51a checks the LCRC value of the input TLP and determines whether there is an error. If there is an error, the error detection unit 51a transmits the Nak packet from the transmission port TX to the transmission source device A. (3) The error detection unit 51a discards the input TLP.

  FIG. 9 shows a data flow when the TLP is received from the transmission source device A and the capacity of the retransmission buffer 50b is exceeded. In this figure, the device A connected to the PCIe relay circuit 10a is the transmission source, and the device B connected to the PCIe relay circuit 10b is the transmission destination. However, in the opposite case, the data flow is the same. (1) When the retransmission buffer 50b runs out of space or is about to run out, the retransmission buffer 50b outputs a buffer full signal to the error detection unit 51a. (2) The error detection unit 51a receives the TLP from the reception port RX connected to the transmission source device A. (3) In a state where the buffer full signal is output to the error detection unit 51a, the error detection unit 51a transmits a Nak packet connected to the transmission source device A regardless of the presence or absence of a TLP error. Output to port TX. (4) Then, the error detection unit 51a discards the received TLP. By performing the control in this way, it becomes possible to transfer packets to the PCIe relay circuits 10a and 10b without exceeding the capacity of the retransmission buffers 50a and 50b.

  FIG. 10 shows a data flow when there is no error in the transmission destination after transmitting the TLP to the transmission destination device B. In this figure, the device A connected to the PCIe relay circuit 10a is the transmission source, and the device B connected to the PCIe relay circuit 10b is the transmission destination. However, in the opposite case, the data flow is the same. First, (1) when the TLP is normally received by the destination device B, an ACK packet is input from the reception port RX of the PCIe relay circuit 10b connected to the destination device B, and the error detection unit 51b is input. Transferred. (2) The error detection unit 51b checks the CRC value of the ACK packet to determine whether there is an error. If there is no error, the error detection unit 51b transfers the ACK packet to the ACK / Nak detection unit 53b. (3) The ACK / Nak detection unit 53b checks the value of Type of the ACK packet to determine whether it is an ACK packet. If it is determined that the packet is an ACK packet, it acquires the PSN from the data area. Then, the ACK signal indicating the ACK and the PSN are transmitted to the retransmission buffer control unit 54b. (4) The retransmission buffer control unit 54b transmits a TLP deletion instruction specifying the PSN to the retransmission buffer 50b. (5) The retransmission buffer 50b releases a buffer area in which TLPs input before the designated PSN are held.

  FIG. 11 shows a data flow when an error is detected in the TLP after transmitting the TLP to the destination device B. In this figure, the device connected to the PCIe relay circuit 10a is the transmission source, and the device B connected to the PCIe relay circuit 10b is the transmission destination. First, (1) if the TLP is not normally received by the transmission destination device B, a Nak packet is input from the reception port RX of the PCIe relay circuit 10b connected to the transmission destination device B, and is sent to the error detection unit 51b. And transferred. (2) The error detection unit 51b checks the CRC value of the Nak packet to determine whether there is an error. If there is no error, the error detection unit 51b transfers the Nak packet to the ACK / Nak detection unit 53b. (3) The ACK / Nak detection unit 53b checks the value of the type of the Nak packet to determine whether it is a Nak packet. If it is determined to be a Nak packet, it acquires the PSN from the data area. Then, the Nak signal indicating the Nak packet and the PSN are transmitted to the retransmission buffer control unit 54b. (4) The retransmission buffer control unit 54b transmits a TLP retransmission instruction specifying the PSN to the retransmission buffer 50b. (5) The retransmission buffer 50b retransmits TLPs input and stored after the designated PSN in the PSN order. The TLP retransmission is repeated until the ACK packet is normally received from the transmission destination device B and the retransmission buffer 50b is released. With this operation, error-free data communication is guaranteed between the mutual devices.

  FIG. 12 shows a data flow when an FC packet is received from the device B and there is no error. In this figure, the device B connected to the PCIe relay circuit 10b is a transmission source, and the device A connected to the PCIe relay circuit 10a is a transmission destination. (1) The FC packet is input from the reception port RX of the PCIe relay circuit 10b connected to the transmission source device B and transferred to the error detection unit 51b. (2) The error detection unit 51b checks the CRC value of the FC packet to determine whether there is an error. If there is no error, the error detection unit 51b transfers the FC packet to the FC detection unit 52b. (3) The FC detection unit 52b checks the value of the Type of the FC packet to determine whether it is an FC packet, and if it is an FC packet, transfers the FC packet to the retransmission buffer 50a as it is. (4) The retransmission buffer 50a transfers the FC packet to the transmission port TX of the PCIe relay circuit 10a connected to the destination device A. (5) The retransmission buffer 50a receives the instruction from the transmission port TX and deletes the FC packet. As described above, the FC packet is directly transferred to the transmission port TX of the PCIe relay circuit 10a connected to the transmission destination device A via the retransmission buffer 50a. The retransmission buffer 50a functions as a buffer for asynchronously writing to and reading from FC packets, and does not perform retransmission control.

  FIG. 13 shows a data flow when various DLLP packets are received from the transmission source device B and there is an error in the DLLP packet. In this figure, the device B connected to the PCIe relay circuit 10b is a transmission source, and the device A connected to the PCIe relay circuit 10a is a transmission destination. (1) The DLLP is input from the reception port RX of the PCIe relay circuit 10b connected to the transmission source device B and transferred to the error detection unit 51b. This DLLP is one of an ACK packet, a Nak packet, and an FC packet. (2) The error detection unit 51b checks the CRC value of the FC packet to determine whether there is an error. If there is an error, the error detection unit 51b discards the received DLLP regardless of the type of DLLP. As for the DLLP, the contents of the ACK packet, Nak packet, and FC packet are continuously updated by the response to the next TLP, etc., and the packet is missing in the middle unlike the TLP in which the lack of request or data is not allowed. Because it is forgiven.

  Next, the operation flow on the transmission port TX side of the PCIe relay circuits 10a and 10b will be described with reference to the flowchart of FIG. As shown in FIG. 14, the transmission port TX sends an instruction to read a packet stored from the retransmission buffers 50a and 50b (step S101). When the packet is read and input to the transmission port TX, it is determined whether the packet is a TLP or FC packet at the transmission port TX (step S102). If the packet is a TLP (step S102: TLP), the transmission port TX transmits the TLP to the device A or the device B that is the transmission destination (step S103).

  On the other hand, when the packet is an FC packet (step S102: DLLP FC), the transmission port TX transmits the FC packet to the device A or device B as the transmission destination (step S104). Then, the transmission port TX sends an instruction to delete the FC packet to the retransmission buffer 50a or 50b (step S105).

  After the transmission of the packet is completed, the transmission port TX issues an instruction to change the reading position of the retransmission buffer 50a or 50b to the next position (step S106), and performs the reading process from step S101 again.

  Next, an operation flow on the reception port RX side of the PCIe relay circuits 10a and 10b will be described with reference to a flowchart of FIG. As shown in FIG. 15, in the reception port RX, the processing starts from the point where a packet is first received (step S201). Next, at the reception port RX, it is determined whether the received packet is a TLP or a DLLP (step S202). If the packet is a TLP (step S202: TLP), the error detection units 51a and 51b determine whether there is an error in the packet (step S203). Next, it is determined whether a buffer full signal is input to the error detection units 51a and 51b (step S204).

  When no error is detected and no buffer full signal is input (step S203, step S204: No), the error detection units 51a and 51b transmit the ACK packet to the transmission port TX connected to the transmission source devices A and B. (Step S205), and then instructs to write the TLP into the retransmission buffers 50a and 50b (step S206). On the other hand, when an error is detected or a buffer full signal is input (Yes in either step S203 or step S204), the error detection units 51a and 51b send the Nak packet to the transmission source devices A and B. Transmission is performed to the connected transmission port TX (step S207).

  When the received packet is a DLLP (step S202: DLLP), the error detection units 51a and 51b determine whether there is an error in the packet (step S208). When it is determined that there is no packet error (step S208: No), the ACK / Nak detection units 53a and 53b or the FC detection units 52a and 52b determine whether the packet is an FC packet or an ACK packet, and It is determined whether the packet is a Nak packet (step S209).

  When it is determined that the packet is an FC packet (step S209: FC packet), the error detection units 51a and 51b transfer the FC packet to the retransmission buffers 50a and 50b and output an instruction to record (step S210). . When it is determined that the packet is an ACK packet (step S209: ACK packet), the ACK / Nak detection units 53a and 53b transfer the ACK signal to the retransmission buffer control units 54a and 54b, and the retransmission buffer control that receives the ACK signal The units 54a and 54b output an instruction to delete the TLP from the retransmission buffers 50a and 50b (step S211). When it is determined that the packet is a Nak packet (step S209: Nak packet), the ACK / Nak detection units 53a and 53b transfer the Nak signal to the retransmission buffer control units 54a and 54b, and the retransmission buffer control that has received the Nak signal. The units 54a and 54b output an instruction to retransmit the TLP from the retransmission buffers 50a and 50b (step S212).

  When it is determined that there is a packet error (step S208: Yes), the error detection units 51a and 51b delete the packet (step S213).

  Next, the operation flow in the retransmission buffers 50a and 50b of the PCIe relay circuits 10a and 10b will be described with reference to the flowchart of FIG. First, when an instruction is input, the retransmission buffers 50a and 50b determine whether or not the instruction is a packet write instruction (step S301). When there is an instruction to write a packet (step S301: Yes), the retransmission buffers 50a and 50b store the packet in the buffer area (step S302). After receiving the packet write instruction and storing the packet, the retransmission buffers 50a and 50b determine whether or not the buffer area has a free space, specifically, whether or not the free space in the buffer area has a predetermined capacity or more. (Step S303). If there is sufficient free space in the buffer area (step S303: Yes), the process ends. On the other hand, if the free space in the buffer area is less than the predetermined capacity (step S303: No), the retransmission buffers 50a and 50b output buffer full signals to the error detection units 51a and 51b (step S304).

  When there is no instruction to write to the retransmission buffers 50a and 50b (step S301: No), the retransmission buffers 50a and 50b determine whether or not there is an instruction to read the recorded packet (step S305). When it is determined that there is an instruction to read a packet (step S305: Yes), the retransmission buffers 50a and 50b determine whether the packet to be read is a TLP or a DLLP (FC packet) (step S306). If it is determined that the packet is a TLP (step S306: TLP), the retransmission buffers 50a and 50b transfer the TLP from the buffer to the transmission port TX (step S307). When the transfer is completed, the retransmission buffers 50a and 50b receive an instruction to change the reading position of the buffer (step S308), and when received, advance the reading position by one packet (step S309).

  On the other hand, when it is determined that the received packet is an FC packet (step S306: FC packet), the retransmission buffers 50a and 50b transfer the FC packet to the transmission port TX (step S310). When the transfer is completed, the retransmission buffers 50a and 50b receive a DLLP packet deletion command (step S311), release the buffer area, and delete the FC packet (step S312).

  When there is no read instruction to the retransmission buffers 50a and 50b (step S305: No), the retransmission buffers 50a and 50b determine whether or not a control signal has been input (step S313). If a control signal is input (step S313: Yes), the retransmission buffers 50a and 50b determine whether the control signal is a TLP deletion instruction or a TLP retransmission instruction (step S314). When it is determined that the instruction is a TLP deletion instruction (step S314: TLP deletion instruction), the retransmission buffers 50a and 50b delete the TLP written before the packet specified by the PSN sent together with the TLP deletion instruction from the buffer area. (Step S315). After deleting the TLP or after deleting the DLLP in step S312, the retransmission buffers 50a and 50b determine whether or not the free capacity of the buffer area is greater than or equal to a predetermined capacity (step S316). As a result of securing the free capacity of the buffer area by deleting the packet, when it is determined that the free capacity of the buffer area is greater than or equal to the predetermined capacity (step S316: Yes), the retransmission buffers 50a and 50b indicate an error. The output of the buffer full signal being notified to the detection units 51a and 51b is stopped (step S317). On the other hand, when it is determined that the free capacity of the buffer area is less than the predetermined capacity (step S316: No), the buffer full signal is continuously output.

  When it is determined that the instruction is a TLP retransmission instruction (step S314: TLP retransmission instruction), the retransmission buffers 50a and 50b return the packet reading position to the PSN received together with the TLP retransmission instruction (step S318). If no control signal is input to the retransmission buffers 50a and 50b (step S313: No), the process is repeated from the beginning.

10a PCIe relay circuit 10b PCIe relay circuit 30a physical layer 40a data link layer 50a retransmission buffer 50b retransmission buffer 51a error detection unit 51b error detection unit 52a FC detection unit 52b FC detection unit 53a ACK / Nak detection unit 53b ACK / Nak detection unit 54a Retransmission buffer control unit 54b Retransmission buffer control unit

JP 2011-028650 A

Claims (4)

A data relay device in which a first port connected to a first device and a second port connected to a second device are connected,
A data flow control packet, and a storage unit for storing the data packet;
A write control unit that controls writing of the data flow control packet received from the first port or the second port , and writing of the data packet to the storage unit;
A read control unit that reads the data flow control packet written to the storage unit and the data packet asynchronously with the write timing, and transmits the read data packet to the first port or the second port;
It is determined whether or not the transmitted data packet is normally transmitted to the first device or the second device as a transmission destination, and when it is determined that the data packet is transmitted, the data transmitted from the storage unit When it is determined that the packet is deleted and not transmitted, a retransmission control unit that instructs to read and retransmit the data packet from the storage unit;
A data relay device comprising: The data flow control packet, and the data packet is input before the data packet is written to the storage unit, further comprising an error detection unit for detecting the presence or absence of the packet,
The storage unit transmits a buffer full signal indicating that when the free capacity is less than a predetermined capacity to the error detection unit,
The data relay device according to claim 1, wherein, when the buffer full signal is input, the error detection unit discards the input data packet. The data relay device according to claim 2, wherein the error detection unit discards the data flow control packet when detecting an abnormality of the data flow control packet. When the error detection unit detects an abnormality in the data packet, the error detection unit instructs the first device or the second device that is the transmission source of the data packet to retransmit the data packet. The data relay device according to claim 2, wherein:

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