JP6007822B2 - Fault tolerant server and its memory copy method - Google Patents

Description

  The present invention relates to a fault tolerant server, a memory copy method thereof, and a memory module for storing write address data.

  In a fault-tolerant server (hereinafter referred to as FT server) that operates by duplicating two systems, data stored in the main memory of one system when the system shifts from one system operation to dual operation Must be quickly copied to the main memory of the other system so that the data in the main memory of both systems match. Furthermore, during the copying of the memory data, it is necessary to temporarily stop the operation of the entire system in order to prevent the copy source data from being updated.

  In recent years, the main memory capacity of the system has been steadily increasing, and the pause time of the system that occurs at the time of memory copying is also increasing. Since the suspension of the system causes a big trouble in business, it is required to shorten the suspension time as much as possible.

  In Patent Documents 1 and 2, when a one-system operation is caused due to the occurrence of a failure, a write address to the main memory is stored in an address storage memory, and the system operation is changed to a duplex operation. A technique for recovering data in one main memory corresponding to the stored address at the time of recovery is disclosed.

JP 2004-46455 A Japanese Patent Laid-Open No. 10-177498

  A known FT server related to the present invention employs a configuration in which a main memory controller and a Trace memory for storing the address of the main memory are incorporated in a dedicated chip set. Then, when copying the memory data, the FT server attempts to reduce the copy time of the main memory by copying only the main memory area in which the data is updated during the one-system operation. However, in recent computer architectures, since the memory controller is built in the CPU, the Trace memory for storing the address of the main memory needs to be mounted on the motherboard.

  However, since the Trace memory has a multi-bit interface like a main memory, it is difficult to mount the Trace memory on a high-density designed motherboard. In addition, mounting of the Trace memory on the mother board leads to an increase in the memory bus path length, resulting in a problem of mounting such as a factor of signal quality deterioration.

  An object of the present invention is to provide a fault-tolerant server, a memory copy method thereof, and a write address data storage memory module that solve the above-described problems.

  In one embodiment, the fault tolerant server includes a memory slot, a main memory mounted in the memory slot, a main memory controller that controls writing or reading to the main memory via a memory bus, and the main memory. A memory copy engine that accesses the memory slot via a controller, and controls write address data storage memory for storing a write address to the main memory, and writing or reading to the write address data storage memory A write address data storage memory module is mounted in the memory slot, and the write address data storage memory controller is connected to the main memory. Write address data is stored in the memory for storing write address data, and the memory copy engine operates from the point of time when the memory controller for the write address data storage becomes a one-system operation due to a failure. The main memory controller instructs to output the write address data stored in the write address data storage memory to the memory bus between the time when the operation is terminated and the duplex operation is restored. Reads the write address output from the memory to the memory bus, reads the data stored in the main memory corresponding to the read write address, and restores the read data from the failure to the other one-system main memory To copy to.

  In another embodiment, a memory copy method of a fault tolerant server includes a memory slot, a main memory mounted in the memory slot, and a main memory that controls writing or reading to the main memory via a memory bus. A controller and a memory copy engine for accessing the memory slot via the main memory controller, provided in a fault-tolerant server, a write address data storage memory for storing a write address to the main memory, A write address data storage memory module having a write address data storage memory controller for controlling writing to or reading from the write address data storage memory. A memory controller for storing the address data stores a write address for the main memory in the memory for storing the write address data, and the memory copy engine is caused by the occurrence of a failure with respect to the memory controller for storing the write address data. Instructed to output the write address accumulated in the write address data storage memory to the memory bus from the time when the one-system operation is completed until the time when the one-system operation is terminated and the duplex operation is restored. The main memory controller reads the write address output from the write address data storage memory to the memory bus, reads the data stored in the main memory corresponding to the read write address, and reads the read data. Others recovered from the above failure To copy to one system of main memory, it is intended.

  In another embodiment, the write address data storage memory module includes a write address data storage memory for storing a write address to the main memory of the fault tolerant server, and a write or read to the write address data storage memory. And a write address data storage memory controller for controlling the write address data, and mounted in a memory slot of the fault tolerant server.

  According to the present invention, it is possible to provide a fault-tolerant server, a memory copy method thereof, and a memory module for storing write address data, which can use a memory copy time shortening function for general purposes and avoid mounting difficulties. it can.

1 is an example of a configuration diagram of a fault tolerant server according to a first embodiment; 1 is an example of a configuration diagram of a memory module according to a first embodiment; 4 is a flowchart showing a memory copy method by the fault tolerant server according to the first exemplary embodiment; It is a figure for demonstrating the principle of this invention.

  First, prior to the description of the embodiment of the present invention, the principle of the present invention will be described. As shown in FIG. 4, the fault tolerant server 300 according to the present invention controls a memory slot 305a, a main memory 313 mounted in the memory slot 305a, and writing or reading to the main memory 313 via a memory bus. At least a main memory controller 303a and a memory copy engine 306a that accesses the memory slot 305a via the main memory controller 303a are provided. Further, the fault tolerant server 300 has a memory module 400 for storing write address data mounted in the memory slot 305a.

  The write address data storage memory module 400 includes a write address data storage memory 410 that stores a write address to the main memory 313, and a write address data storage memory that controls writing to or reading from the write address data storage memory 410. And a controller 411.

  The write address data storage memory controller 411 stores a write address for the main memory 313 in the write address data storage memory 410. The memory copy engine 306a writes to the write address data storage memory controller 411 from the time when the one-system operation is caused due to the failure to the time when the one-system operation is terminated and the duplex operation is restored. An instruction is given to output the write address stored in the address data storage memory 410 to the memory bus. The main memory controller 304a reads the write address output from the write address data storage memory 410 to the memory bus, reads the data stored in the main memory 313 corresponding to the read address, and sets the read data as a fault. Copy to the main memory of another system restored from

Embodiment 1 FIG.
Embodiments of the present invention will be described below with reference to the drawings.
<Configuration>
The configuration of the FT server according to the present embodiment will be described with reference to FIG.
The FT server 100 includes a module 1a and a module 1b that operates in synchronization with the module 1a. The cross link bus 2 connects the module 1a and the module 1b. The module 1a and the module 1b monitor each other's state via the cross link bus 2. The module 1a includes a CPU 4a, a memory slot 5a, a main memory (not shown) mounted in the memory slot 5a, and a fault tolerant control chip (hereinafter referred to as FT control chip) 7a. Since the module 1b has the same configuration, detailed description thereof is omitted here.

  The CPU 4a incorporates a memory controller 3a as an example of a main memory controller that controls writing or reading to a main memory (not shown) via a memory bus. The memory slot 5a has a plurality of memory slots, and each memory slot is connected to the memory controller 3a. A main memory (not shown) and a Trace memory module 200 described later are mounted in the memory slot 5a.

  In the memory slot 5a, the main memory (not shown) may be mounted, for example, at a position closest to the memory controller 3a. When the main memory (not shown) is composed of a plurality of memories, for example, the memory controller Each memory may be mounted starting from the position closest to 3a. Further, the Trace memory module 200 may be mounted at a position farthest from the memory controller 3a, for example. The mounting positions of the main memory (not shown) and the Trace memory module 200 in the memory slot 5a are not limited to this, and may be mounted at other positions.

  The FT control chip 7a includes a memory copy engine 6a. The memory copy engine 6a is connected to the memory controller 3a and can access the memory slot 5a via the memory controller 3a. The data link bus 8 connects the CPU 4a and the CPU 4b. The CPU 4 a and the CPU 4 b perform memory copying via the data link bus 8.

With reference to FIG. 2, a configuration of a Trace memory module 200 as an example of a write address data storage module according to the present embodiment will be described.
The Trace memory module 200 as an example of a write address data storage memory module includes a memory module interface 9, a Trace memory 10 as an example of a write address data storage memory, and a Trace as an example of a write address data storage memory controller. A memory controller 11 and a switching selector 12 are provided. The Trace memory module 200 can be detachably mounted on the memory slots 5a and 5b of the modules 1a and 1b.

  The memory module interface 9 is an interface for reading commands and addresses on the memory bus. The Trace memory 10 stores the address data of the write address to the main memory with respect to the address data on the memory bus. The Trace memory controller 11 decodes a command on the memory bus and controls writing to or reading from the Trace memory 10. Further, the Trace memory controller 11 holds a start address at the start of a one-system operation and an end address at the end of the one-system operation, which will be described later, for the write address of the Trace memory 10. The switching selector 12 inputs the address data of the write address on the memory bus to the trace memory 10 and outputs the write address data stored in the trace memory 10 to the data bus on the memory bus.

FIG. 3 is a flowchart showing processing when mapping the Trace memory to the specific memory space in the FT server 100 according to the present embodiment.
First, the user turns on the power of the FT server 100 (S101). The BIOS of the FT server 100 executes POST (Power On Self Test) (S102).

  The BIOS asks the user by displaying in the BIOS setting menu whether or not to use the Trace memory function. The BIOS determines whether or not to use the Trace memory function according to the answer from the user (S103). When the BIOS does not use the Trace memory function, the BIOS activates the device (FT server 100) (S104).

  When using the Trace memory function, the BIOS sets the Trace memory function to On (S105). Then, the BIOS restarts the device (FT server 100) (S106).

  After the restart, the BIOS executes the above-described POST and maps the Trace memory 10 to a specific memory space in order to use the Trace memory function (S107). This specific memory space is a memory space that can be accessed only by the memory copy engine 6, and is allocated in advance. Finally, the BIOS activates the device (FT server 100) (S108).

  As described above, in the system that uses the Trace memory module according to the present embodiment, the necessity of using the Trace memory function and the setting thereof are incorporated into the BIOS settings. Then, the trace memory 10 is mapped to a specific memory space accessible only by the memory copy engine 6 at the time of memory mapping processing when the apparatus (FT server 100) is activated. Thereby, even when the Trace memory module 200 is mounted in the general-purpose memory slot 5a, it is possible to prevent a normal application from accessing the Trace memory.

<Operation>
Hereinafter, the operation of the FT server 100 will be described. In the following operation example, a case where a Trace memory module is mounted in the memory slot 5a will be described as an example.
First, the FT server 100 on which the Trace memory module 200 is mounted always monitors the command and address on the memory bus between the memory controller 3a of the module 1a and the memory slot 5a via the memory module interface 9 during the duplex operation. Yes.

  The Trace memory controller 11 decodes a command on the memory bus. When the decoded command is a write command to the main memory, the Trace memory controller 11 switches the selector 12 in the input direction of the Trace memory 10 to perform the write on the memory bus. The address data of the write address of the command is stored in the Trace memory 10. The trace memory controller 11 accumulates the write address to the main memory in the trace memory 10 by continuing the storage in the trace memory 10. The Trace memory controller 11 controls writing to the Trace memory 10 and increments the address pointer of the write address to the Trace memory 10 (for example, increases by 1).

  When a failure occurs during the duplication operation and any abnormality is detected in the module 1b due to the occurrence of the failure, the FT control chip 7a of the module 1a detects the abnormality of the module 1b via the cross link bus 2. . Then, the FT control chip 7a disconnects the module 1b from the system and shifts to a one-system operation of only the module 1a. The memory copy engine 6a of the FT control chip 7a notifies the memory controller 3a and the Trace memory controller 11 that the one-system operation has started. The memory copy engine 6a notifies the trace memory controller 11 via the memory controller 3a using a command indicating that the one-system operation has started.

  When the trace memory controller 11 receives a notification of the start of one-system operation, the trace memory controller 11 uses the write address to the trace memory 10 at the time of receiving the notification as the start address at the start of one-system operation. Hold on. The system continues the one-system operation until the module 1b is restored. During this time, the Trace memory controller 11 continues to store the write address to the main memory of the module 1a in the Trace memory 10.

  When the recovery of the module 1b starts, the system shifts from the single system operation to the duplex operation. At this time, the memory copy engine 6a of the FT control chip 7a uses the write address data stored in the Trace memory 10 in order to match the contents of the main memory of the module 1a and the module 1b. The operation of copying only the data in the main memory of the module 1a updated to the module 1b is started. This will be specifically described below.

  (I) First, the memory copy engine 6a of the FT control chip 7a notifies the memory controller 3a and the Trace memory controller 11 that the one-system operation has ended. The memory copy engine 6a issues a read command to the Trace memory 10 and notifies the Trace memory controller 11 via the memory controller 3a. When the trace memory controller 11 receives a read command to the trace memory 10, the trace memory controller 11 uses the write address to the trace memory 10 at the time of receiving the notification as the end address at the end of the one-system operation. Hold.

  (Ii) Then, the Trace memory controller 11 moves the address pointer of the Trace memory 10 to the held start address at the time of one-system operation, and switches the switching selector 12 in the output direction of the Trace memory 10. The Trace memory controller 11 increments the address pointer of the Trace memory 10 from the start address to the end address, and outputs the write address of the main memory stored in the Trace memory 10 to the data bus of the memory bus. Let As a result, the memory copy engine 6a causes the Trace memory controller 11 to trace memory from the time when the one-system operation is caused due to the occurrence of the failure to the time when the one-system operation is terminated and the duplex operation is restored. 10 is instructed to output the write address stored in 10 to the memory bus.

  (Iii) When the memory controller 3a of the module 1a receives the notification of the end of the one-system operation, the trace memory 10 regarding the write address of the Trace memory 10 from the start address at the start of the one-system operation to the end address at the end of the one-system operation. Is read from the data bus of the memory bus. The memory controller 3a holds the read write address in the memory copy engine 6a. When the memory controller 3a finishes reading all the write addresses, the memory controller 3a reads the data in the main memory at the write addresses, and starts memory copy from the module 1a to the module 1b. The memory controller 3a of the module 1a performs data copy through the data link bus 8 until the main memory data of the module 1a and the module 1b match.

  As described above, the FT server 100 according to the present embodiment mounts the Trace memory module 200 in the memory slot on the motherboard. Here, the Trace memory module 200 includes a Trace memory, and the Trace memory can be accessed by a memory copy engine built in the FT control chip. Then, the Trace memory module 200 stores the address data when the main memory is accessed in the FT server 100 in the Trace memory. When copying of the main memory occurs, the memory copy engine 6a takes out the write address of the Trace memory 10 and copies only the data in the area updated during the one-system operation.

  Up to now, the function of shortening the memory copy time has been realized only by adopting a dedicated chipset for the device. However, according to the present embodiment, it is not necessary to employ a dedicated chipset, so the memory copy time can be shortened. The function can be made universally available. Therefore, according to the present embodiment, it is possible to shorten the system suspension time required for memory copy.

  In addition, according to the present embodiment, since the Trace memory module 200 is mounted in the empty memory slot 5a on the motherboard, there is an advantage that the mounting area of the motherboard is not impaired. Further, by mounting the Trace memory module 200 using the memory slot 5a, it is possible to minimize the influence on the memory bus path length.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

1a, 1b module,
2 Cross link bus,
3a, 3b memory controller,
4a, 4b CPU,
5a, 5b memory slot,
6a, 6b Memory copy engine,
7a, 7b FT control chip,
8 Data link bus,
9 Memory module interface,
10 Trace memory,
11 Trace memory controller,
12 switching selector,
100 fault-tolerant server,
200 Trace memory module,
300 fault-tolerant server,
303a main memory controller,
305a memory slot,
306a memory copy engine,
313 main memory,
400 memory module for storing write address data,
410 memory for storing write address data,
411 memory controller for storing write address data;

Claims (4)

A memory slot; a main memory mounted in the memory slot; a main memory controller that controls writing or reading to the main memory via a memory bus; and a memory that accesses the memory slot via the main memory controller A copy engine,
Write address data storage memory having a write address data storage memory for storing a write address to the main memory, and a write address data storage memory controller for controlling writing to or reading from the write address data storage memory Mounting the module in the memory slot;
When the command on the memory bus is a write command to the main memory, the write address data storage memory controller stores a write address to the main memory in the write address data storage memory,
The memory copy engine notifies the write address data storage memory controller of the start of the one-system operation when the one-system operation is caused by the occurrence of a failure, and the one-system operation is changed to the duplex operation . To the write address data storage memory controller, the end of one-system operation is notified,
When the write address data storage memory controller receives the notification of the start of the one-system operation, the write address data storage using the write address to the write address data storage memory at the time of receiving the notification as the start address When the notification of the end of the one-system operation is received, the write address to the write address data storage memory is used as the end address when the notification of the end of the one-system operation is received. held inside the memory controller, until the said end address starting before Symbol start address, increasing the address pointer of the write address data storage memory, stored in the write address data storage memory the write address of the main memory Is output to the serial memory bus,
The main memory controller reads a write address output from the write address data storage memory to the memory bus, reads data stored in the main memory corresponding to the read write address, and reads the read data. Copy to the main memory of the other one system recovered from the failure,
Fault tolerant server. The memory for storing the write address data is a memory space accessible only by the memory copy engine, and is mapped to a specific memory space allocated in advance.
The fault-tolerant server according to claim 1. A memory slot; a main memory mounted in the memory slot; a main memory controller that controls writing or reading to the main memory via a memory bus; and a memory that accesses the memory slot via the main memory controller A copy engine and a fault-tolerant server
Write address data storage memory having a write address data storage memory for storing a write address to the main memory, and a write address data storage memory controller for controlling writing to or reading from the write address data storage memory A module is mounted in the memory slot;
The write address data storage memory controller, when the command on the memory bus is a write command to the main memory, stores the write address to the main memory in the write address data storage memory,
When the memory copy engine becomes a one-system operation due to the occurrence of a failure, the write address data storage memory controller is notified of the start of the one-system operation, and the one-system operation is changed to the duplex operation . To the write address data storage memory controller, the end of one-system operation is notified,
When the write address data storage memory controller receives the notification of the start of the one-system operation, the write address data storage is performed with the write address to the write address data storage memory at the time of receiving the notification as the start address When the notification of the end of the one-system operation is received, the write address to the write address data storage memory is used as the end address when the notification of the end of the one-system operation is received. held inside the memory controller, until the said end address starting before Symbol start address, increasing the address pointer of the write address data storage memory, stored in the write address data storage memory the write address of the main memory Is output to the serial memory bus,
The main memory controller reads a write address output from the write address data storage memory to the memory bus, reads data stored in the main memory corresponding to the read write address, and reads the read data. Copy to the main memory of the other one system recovered from the failure,
Memory copy method for fault tolerant servers. The memory for storing the write address data is a memory space accessible only by the memory copy engine, and is mapped to a specific memory space allocated in advance.
The memory copy method for a fault-tolerant server according to claim 3.

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