JP6010971B2 - Circuit model generation method, apparatus, and program - Google Patents

Description

  The present invention relates to a technique for generating an analog circuit model in the field of circuit simulation.

  In recent years, the scale of integrated circuits has been increasing, and more and more circuits have analog and digital on one chip. When functional verification is performed on the entire chip, the digital circuit can perform high-speed simulation using a hardware description language such as RTL (Resister Transfer Level). However, analog circuit simulation is very slow, making it difficult to verify the functionality of the entire chip system.

  Therefore, in recent years, a technique of modeling a circuit in a language called analog HDL (Hardware Description Language) and performing simulation at high speed has been actively used.

  By the way, as a circuit simulation using a circuit model, several methods are conventionally known.

  For example, an analysis model for a lower layer cell is generated from the element connection information, an analysis model for an upper layer cell is generated by referring to a circuit simulation result for the lower layer cell, and an analysis model for the upper layer cell is generated using the analysis model. A technique for executing a circuit simulation is known.

  Also, a technique is known in which a circuit simulation is performed to generate a hidden Markov model for an input / output signal for a model to be modeled by a predetermined algorithm from the value and time of the input / output signal for the module to be modeled. ing.

  Furthermore, a first delay time from the start of change of the input signal to the start of change of the output signal and a second delay time from the start of change of the input signal to the start of change of the output signal are respectively expressed as delay model equations. The method of expressing by is known.

JP 2003-58595 A JP 2010-286948 A Japanese Patent Laid-Open No. 9-319776

  In the case of modeling an analog circuit by analog HDL, conventionally, a model is manually constructed by visual inspection or manual calculation from a specification or a simulation result.

  FIG. 12 is a diagram illustrating an example of a conventional manual construction work of an analog circuit model.

  First, the worker visually checks the displayed simulation waveform, specifies the DC level of the output relative to the input, and obtains the transition time from when the input changes until the DC level stabilizes (operation OP1). Then, the worker manually calculates a model expression based on the DC level of the output corresponding to the specified input and the transition time, and generates a circuit model by coding analog HDL representing the calculated model expression (operation OP2). .

  Therefore, there is a problem that the waveform visual check (operation OP1) is likely to cause mistakes such as erroneous reading of numerical values and oversight. In addition, when the number of points to be seen in the simulation waveform increases, there is a problem that the number of work steps increases. Furthermore, manual calculation and coding of the model formula (operation OP2) has a problem that mistakes due to manual calculation are likely to enter. In addition, there is a problem that the accuracy of the model formula varies depending on the operator's manual calculation experience and skill. In addition, when the operator has little experience in analog HDL coding or lacks in skill, there is a problem that the number of work steps increases.

  From the above problems, automatic generation of an analog circuit model is strongly desired. An object of the present invention is to provide a method, an apparatus, and a program for realizing a process capable of automatically generating a circuit model from a simulation waveform of an analog circuit.

A circuit model generation method disclosed as one embodiment of the present invention is a method for generating a model of a circuit whose output is uniquely determined with respect to an input, wherein a computer receives a simulation waveform of the circuit, and a plurality of simulation waveforms the output of the DC level for each input value of the input pattern, obtains a transition time from when the output of the change by the input value of the plurality of input patterns to the start of the steady state of the DC level of the output was obtained based on the set of the plurality of the input value and DC level before SL output, to generate a first equation representing a relationship between input and output, and the transition time acquired from the first equation based to generate a second mathematical expression that associates the information of the transition time to a change in the DC level of the acquired output, generating a mathematical model including the second equation from the first equation And executes the processing.

  According to the circuit model generation method disclosed above, an analog circuit model can be automatically generated, and circuit simulation processing can be speeded up.

It is a figure which shows the block structural example of the circuit model production | generation apparatus in one Embodiment. It is a figure which shows the example of a processing flow of the circuit model production | generation apparatus in one embodiment. Is a diagram illustrating an example of the output values y _j and the transition time t _j is obtained by the process of step S2 and S3 of the processing flow in the embodiment. It is a figure which shows the example of the numerical formula model obtained in one embodiment. It is a figure which shows the example of the inclination used as the information of the transition time in one Embodiment. It is a figure for demonstrating the difference between the numerical formula model obtained by the process of step S4 of a process flow, and the numerical formula model obtained by the process of step S5 in one embodiment. In one Example, it is a figure which shows the structural example of the analog circuit used as the object of circuit model generation. In one Example, it is a figure which shows the example of an input pattern of the input waveform of a simulation waveform. It is a figure which shows the example of the circuit model by analog HDL output by the circuit model production | generation apparatus in one Example. It is a figure which shows the input of the gain control bit of each gain in a circuit simulation, the output waveform example of the circuit model which the circuit model production | generation apparatus output, and the output waveform example of the circuit model created by the conventional method. It is a figure which shows the hardware constitutions of the apparatus which implements a circuit model production | generation apparatus. It is a figure which shows the work example of the model construction of the analog circuit by the conventional manual labor.

  Hereinafter, a circuit model generation device disclosed as one embodiment of the present invention will be described.

  FIG. 1 is a diagram illustrating a block configuration example of a circuit model generation device according to an embodiment.

  The circuit model generation apparatus 1 is an apparatus that automatically generates a model of an analog circuit whose output is uniquely determined for an input. The processing target of the circuit model generation device 1 is limited to a circuit whose output is uniquely determined with respect to the input. For example, circuits such as a variable gain amplifier and a digital / analog converter (DAC) are to be processed, but, for example, a phase-locked loop (PLL) is provided with a flip-flop (FF) to hold the state. Such a circuit is not subject to processing.

  The circuit model generation device 1 includes a data reception unit 11, an output / transition time acquisition unit 13, a mathematical model construction unit 15, and a circuit model generation unit 17.

  The data receiving unit 11 receives a simulation waveform 2 of a circuit to be processed as an input.

  The output / transition time acquisition unit 13 acquires the DC level of the output for each input value and the transition time until the DC level is reached from the input / output related waveform of the simulation waveform 2 received. The transition time is the time from the change of the output due to the input value to the start of the stable state of the output, and the slope is used to eliminate the influence of the output on the previous input value. The DC level of the output is a value in a stable state, and is a voltage level or current level value.

  The mathematical expression model construction unit 15 generates a mathematical expression model indicating the relationship between the input and the output based on the set of each input value and the acquired DC level of the output. The mathematical expression model construction unit 15 obtains a function for obtaining an output DC level with respect to an unknown input value by using a function interpolation method.

  Further, the mathematical formula model construction unit 15 sets transition time information in the mathematical model based on the transition time acquired by the output / transition time acquisition unit 13.

  The circuit model generation unit 17 generates circuit model information in which a mathematical model is described in a hardware description language.

  Next, the operation of the circuit model generation device 1 will be described.

  FIG. 2 is a diagram illustrating a processing flow example of the circuit model generation device 1.

  Step S1: The data receiving unit 11 receives a simulation waveform 2 to be processed.

Step S2: The output / transition time acquisition unit 13 outputs the input value x _j (1 ≦ j ≦ i) with respect to the received simulation waveform 2 for all given input patterns (combinations of input values). DC level, that is, the voltage level or current level at which the DC level becomes stable is obtained as the output value y _j .

Step S3: The output / transition time acquisition unit 13 changes the simulation waveform 2 from when the input value x _j is changed until the DC level is stabilized (from when the input value changes to when the DC level stable state starts). Time t _j is obtained. In order to remove the influence of the previous output value y _j−1 , the output / transition time acquisition unit 13 acquires the following expression using the gradient a _j as the transition time t _j .

a _j = | y _j −y _j−1 | / t _j
FIG. 3 is a diagram illustrating an example of the output value y _j and the transition time t _j acquired by the processes of steps S2 and S3. As shown in FIG. 3, the output-transition time acquisition unit 13, from the initial value of _{x 0, x 1, x 2} , x 3, ..., for each input value _{x i,} the DC level of a stable state Output values y ₀ , y ₁ , y ₂ , y ₃ ,..., Y _i and transition times t ₁ , t ₂ , t ₃ ,..., T _i (a ₁ , a ₂ , a ₃ ,..., A _i ) And is obtained.

The steps S2 and S3 may be executed for each input value _{x j.}

Step S4: The mathematical expression model construction unit 15 uses the known function interpolation method from the set (x _j , y _j ) of the input value x _j and the output value y _j to output the value (DC) for the unknown input x ′. A function of level) y ′, y ′ = f (x ′) is obtained and used as a mathematical model. Here, the input value x _j and the output value y _j may be multidimensional.

  FIG. 4 is a diagram illustrating an example of the obtained mathematical model.

Step S5: As shown in FIG. 4, since the mathematical model showing the relationship between the input value x ′ and the output value y ′ obtained in Step S4 does not include time transition information, the mathematical model building unit 15 incorporates transition time information into the mathematical model. Mathematical expression model construction unit 15, as the transition time information, 'when changes to _k, the output value y' input is the input value x at time t _k 'inclination a transition to _{k' k} from _k-1 output value y Is calculated.

  FIG. 5 is a diagram illustrating an example of an inclination used as transition time information.

The mathematical expression model construction unit 15 uses the gradient _aj closest to the gradient between the start point and the end point of the transition at the transition from the output value y ′ _k−1 to the output value y ′ _k . The mathematical model building unit 15
|| y _j −y ′ _k || + || y _j−1 −y ′ _k−1 || (1 ≦ j ≦ i) is determined as j, and a ′ _k = a _j is obtained.

  Then, the mathematical formula model construction unit 15 outputs the following mathematical formulas (Formula 1 and Formula 2) as a mathematical model indicating the relationship between the input value x ′, the output value y ′, and the transition time t ′.

Formula 1: y ′ = f (x ′ _k )
(T−t _k ≧ | (y ′ _k −y ′ _k−1 ) ./ a ′ _k |)
Formula 2: y ′ = y ′ _k−1 + a ′ _k (t−t _k )
(T−t _k < | (y ′ _k −y ′ _k−1 ) ./ a ′ _k |)
FIG. 6 is a diagram for explaining the difference between the mathematical model obtained by the process of step S4 and the mathematical model obtained by the process of step S5.

  As shown in FIG. 6, time information (transition time) until a stable output value is expressed when the output (DC level) changes with the input change in the mathematical model by the process of step S <b> 5. You can see that

  Step S6: The circuit model generation unit 17 generates and outputs a circuit model 3 that describes the mathematical model obtained in the process of step S5 using analog HDL, which is one of the hardware description languages.

  Hereinafter, an embodiment of the circuit model generation device 1 will be described.

  In one embodiment, the circuit model generation device 1 generates a circuit model for a variable gain amplifier circuit.

  FIG. 7 is a diagram illustrating a configuration example of an analog circuit that is a target of circuit model generation. The circuit shown in FIG. 7 is a variable gain amplifier circuit having five variable gain (GA4 to 0) settings in which a signal waveform is input from IN and a signal waveform is output from OUT.

  FIG. 8 is a diagram illustrating an input pattern example of an input waveform of a simulation waveform. The input pattern of FIG. 8 is shown by a data table showing the relationship between the input (IN) and the output DC level (OUT) in all the settings of the gain control bits.

  The circuit model generation device 1 constructs a mathematical model of the variable gain amplifier circuit based on the values in the data table shown in FIG. 8 by the above-described processing, and creates a circuit model describing the constructed mathematical model.

  FIG. 9 is a diagram illustrating an example of a circuit model described by analog HDL output from the circuit model generation apparatus 1.

  FIG. 10 is a diagram showing input of gain control bits for each gain, an output waveform example of a circuit model output by the circuit model generation device 1, and an output waveform example of a circuit model created by a conventional method in circuit simulation. is there.

  As shown in FIG. 10, the output waveform of the circuit model output by the circuit model generation device 1 is substantially the same as the output waveform of the circuit model generated by the conventional method.

  On the other hand, since the processing time of the circuit model generation device 1 is much shorter than that of the conventional method, the circuit simulation time can be reduced to about 1/100 in the circuit simulation to which the circuit model generation device 1 is applied. it can.

  The circuit model generation device 1 described above includes dedicated hardware having the processing unit shown in FIG. 1 or a CPU 101, a memory 102, a storage device (hard disk) 103, an input device (keyboard) 104, and an output as shown in FIG. The present invention can be implemented by a computer 100 to which a device (display) 105 is connected via an internal network or the like.

  Furthermore, the circuit model generation device 1 can be implemented as a program that can be executed by the computer 100. In this case, the program for realizing the function of the processing unit of the circuit model generation device 1 shown in FIG. That is, the computer 100 is caused to read and execute an execution program that causes the computer to execute the functions of the data reception unit 11, the output / transition time acquisition unit 13, the mathematical model building unit 15, and the circuit model generation unit 17 illustrated in FIG. Thus, the circuit model generation device 1 can be realized.

In this case, the CPU 101 of the computer 100, for example,
The above execution program and input information (simulation waveform 2) are stored in the hard disk 103 as a file.
The execution program is started from the keyboard 104, and the started execution program is loaded into the memory 102, and the processing proceeds while reading the simulation waveform 2 from the hard disk 103 to the memory 102 as necessary.
-Finally, the output circuit model 3 is displayed on the display 105 and output in a file format.
The process is executed by such a method.

  The execution program is not only a recording medium such as a CD-ROM, CD-RW, DVD-R, DVD-RAM, DVD-RW, or flexible disk, but also other storage devices provided at the end of the communication line. It may be stored in a computer hard disk or the like.

  Note that the elements constituting the circuit model generation device 1 may be realized in any combination. A plurality of components may be realized as one member, and one component may be configured from a plurality of members. In addition, the circuit model generation device 1 is not limited to the above-described embodiment, and various improvements and changes may naturally be made without departing from the gist of the present invention.

  As described above, according to the disclosed circuit model generation device 1, although only an analog circuit whose output is uniquely determined by input, the circuit model 3 is automatically generated only by inputting the simulation waveform 2. The mistakes caused by manual work can be eliminated, and the number of work steps can be greatly reduced. Therefore, for example, it is possible to realize high-speed circuit simulation by SPICE (Simulation Program with Integrated Circuit Emphasis) or the like.

DESCRIPTION OF SYMBOLS 1 Circuit model production | generation apparatus 11 Data reception part 13 Output / transition time acquisition part 15 Formula model construction part 17 Circuit model production | generation part 2 Simulation waveform 3 Circuit model

Claims (6)

A method for generating a model of a circuit whose output is uniquely determined for an input,
Computer
Accept circuit simulation waveforms,
The output of the DC level for each input value of the plurality of input patterns of the simulated waveform, a transition time from when the output of the change by the input value of the plurality of input patterns to the start of the steady state of the DC level of the output Get
Based combination of the acquired plurality of each input value and DC level before SL output, to generate a first equation representing the relationship between the input and the output, the transition time obtained with the first equation based on bets, it generates a second mathematical expression that associates the information of the transition time to a change in the DC level of the acquired output, generating a mathematical model including the second equation from the first equation A circuit model generation method characterized by executing a process. The circuit model generation method according to claim 1, wherein a function interpolation method set in advance is used in the process of generating the first mathematical expression . As the information of the transition time of the second equation, the output value for the one input value based on the transition time to the other input values from one input value for each input value of the input pattern of the other 2. Each inclination to an output value with respect to an input value is calculated, and one calculated inclination that most closely approximates the inclination of the output value from the start point to the end point of the transition of the input pattern is used. 3. The circuit model generation method according to 2. The computer is
The circuit model generation method according to any one of claims 1 to 3, wherein a process of generating a circuit model indicating the mathematical model in a hardware description language is executed. A device that generates a model of a circuit whose output is uniquely determined for an input,
A processing unit for receiving a simulation waveform of the circuit;
The output of the DC level for each input value of the plurality of input patterns of the simulated waveform, a transition time from when the output of the change by the input value of the plurality of input patterns to the start of the steady state of the DC level of the output A processing unit for acquiring
Based combination of the acquired plurality of each input value and DC level before SL output, to generate a first equation representing the relationship between the input and the output, the transition time obtained with the first equation based on bets, to generate a second mathematical expression that associates the information of the transition time to a change in the DC level of the acquired output, generating a mathematical model including the second equation from the first equation A circuit model generation device comprising: a processing unit that performs processing. In order to generate a model of a circuit whose output is uniquely determined for the input,
On the computer,
Accept circuit simulation waveforms,
The output of the DC level for each input value of the plurality of input patterns of the simulated waveform, a transition time from when the output of the change by the input value of the plurality of input patterns to the start of the steady state of the DC level of the output Get
Based combination of the acquired plurality of each input value and DC level before SL output, to generate a first equation representing the relationship between the input and the output, the transition time obtained with the first equation based on bets, to generate a second mathematical expression that associates the information of the transition time to a change in the DC level of the acquired output, generating a mathematical model including the second equation from the first equation A circuit model generation program characterized by causing a process to be executed.

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