JP6015463B2 - Semiconductor device and method for controlling semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for controlling the semiconductor device.

  When the operation voltages of a plurality of circuit blocks provided in the semiconductor device are different from each other, the propagation delay time of the clock signal in each circuit block is different. As a result, the timing of the clock signal supplied to the flip-flop in the circuit block is shifted and a clock skew occurs. Therefore, a method has been proposed in which the clock skew between the circuit blocks is suppressed by adjusting the timing of the clock signal supplied to the circuit block according to the operating voltage of the circuit block (see, for example, Patent Document 1). .

  In addition, a technique for improving clock skew by switching the path of the clock signal in the clock distribution circuit has been proposed (see, for example, Patent Documents 2 and 3). Furthermore, a technique for suppressing clock skew by connecting a load such as a clock mesh to the clock distribution circuit has been proposed (see, for example, Patent Document 4).

Japanese Patent Laid-Open No. 2005-1000026 JP 2001-56721 A JP 2009-187104 A JP 2010-2333018 A

  However, when the clock mesh is used, the power consumption of the semiconductor device increases due to the charge / discharge current of the clock mesh. The power consumption increases as the power supply voltage increases. On the other hand, when the clock mesh is not used, for example, a hold buffer may be inserted into the data signal line in order to satisfy the hold constraint of the flip-flop. The amount of leakage energy of the hold buffer increases as the power supply voltage decreases.

  The semiconductor device disclosed herein is intended to suppress an increase in power consumption while suppressing clock skew.

  According to one aspect, a semiconductor device includes a plurality of clock signal lines for transmitting a clock signal, a load unit connectable to the plurality of clock signal lines, and a plurality of clock signal lines when a power supply voltage is a predetermined value or less. And a switching unit that disconnects the plurality of clock signal lines from the load unit when the power supply voltage is higher than a predetermined value.

  An increase in power consumption can be suppressed while suppressing clock skew.

It is a figure which shows one Embodiment of the control method of a semiconductor device and a semiconductor device. It is a figure which shows another embodiment of the semiconductor device and the control method of a semiconductor device. FIG. 3 is a diagram illustrating an example of a clock distribution unit, a switching unit, a clock mesh, and a logic circuit unit illustrated in FIG. 2. FIG. 4 is a diagram illustrating an example of the operation of the logic circuit unit illustrated in FIG. 3. It is a figure which shows the example of the method of determining the voltage information Vm shown in FIG. It is a figure which shows the example of arrangement | positioning of the clock mesh and switch shown in FIG. FIG. 3 is a diagram illustrating an example of an operation mode of the semiconductor device illustrated in FIG. 2. FIG. 3 is a diagram illustrating an example of dependency of energy consumption on a power supply voltage in the semiconductor device illustrated in FIG. 2. FIG. 3 is a diagram showing an example of operation of the semiconductor device shown in FIG. 2. It is a figure which shows another embodiment of the semiconductor device and the control method of a semiconductor device. FIG. 11 illustrates an example of operation of the semiconductor device illustrated in FIG. 10. It is a figure which shows another embodiment of the semiconductor device and the control method of a semiconductor device. It is a figure which shows another embodiment of the semiconductor device and the control method of a semiconductor device.

  Hereinafter, embodiments will be described with reference to the drawings. The same reference numerals as the signal names are used for signal lines and terminals through which signals are transmitted. Double square marks in the figure indicate external terminals. The external terminal is, for example, a pad on a semiconductor chip or a lead of a package in which the semiconductor chip is stored. For the signal supplied via the external terminal, the same symbol as the terminal name is used.

  FIG. 1 shows an embodiment of a semiconductor device and a method for controlling the semiconductor device. The semiconductor device 100 of this embodiment includes a plurality of clock signal lines CLKa1 and CLKb1 that transmit the clock signal CLK0, and a switching unit SWU that connects the clock signal lines CLKa1 and CLKb1 to the load unit LDU. For example, the load unit LDU is a clock mesh. The switching unit SWU connects the clock signal lines CLKa1 and CLKb1 to the load unit LDU when the power supply voltage VDD is equal to or lower than a predetermined value, and connects the clock signal lines CLKa1 and CLKb1 from the load unit LDU when the power supply voltage VDD is higher than the predetermined value. Separate.

  For example, the switching unit SWU includes switches SWa and SWb that connect or disconnect the clock signal lines CLKa1 and CLKb1 to the load unit LDU based on control by the control unit CNTU. The control unit CNTU determines the magnitude relationship between the power supply voltage VDD and a predetermined value, and controls the switching unit SWU based on the determination result. Note that the control unit CNTU may be disposed outside the semiconductor device 100.

  For example, the clock signals CLKa1 and CLKb1 are respectively supplied to the clock input terminals of the flip-flop FF. For example, the clock skew generated in the clock signals CLKa1 and CLKb1 is a phase shift of the clock signals CLKa1 and CLKb1 reaching the clock input terminal.

  In this embodiment, when the power supply voltage VDD is equal to or lower than a predetermined value, the clock signal lines CLKa1 and CLKb1 are connected to the common load unit LDU, so that clock skew can be suppressed. Thereby, for example, the number of hold buffers inserted to adjust the time margin for satisfying the hold constraint of the flip-flop FF to which the clock signal CLKa1 (or CLKb1) is input can be reduced as compared with the conventional case. Since the number of inserted buffers can be reduced, the amount of leakage current when the power supply voltage VDD is equal to or lower than a predetermined value can be suppressed, and the power consumption of the semiconductor device 100 can be suppressed.

  Further, when the power supply voltage VDD is higher than a predetermined value, the load unit LDU is disconnected from the clock signal lines CLKa1 and CLKb1, and therefore no charge / discharge current of the load unit LDU is generated due to the level change of the clock signals CLKa1 and CLKb1. Thereby, the power consumption of the semiconductor device 100 can be suppressed. The clock skew becomes relatively smaller as the power supply voltage VDD is higher. For this reason, even if the load unit LDU is disconnected from the clock signal lines CLKa1 and CLKb1 when the power supply voltage VDD is higher than a predetermined value, the influence on the characteristics of the semiconductor device 100 due to an increase in clock skew is small.

  As described above, in this embodiment, an increase in power consumption of the semiconductor device 100 can be suppressed while suppressing clock skew regardless of the power supply voltage VDD.

  FIG. 2 shows another embodiment of the semiconductor device and the method for controlling the semiconductor device. The semiconductor device 100A of this embodiment has, for example, a DVFS (Dynamic Voltage and Frequency Scaling) function. DVFS is a technique for dynamically changing the frequency of a power supply voltage and a clock signal supplied to a circuit according to the processing capability required for the circuit. Note that the semiconductor device 100A may generate a clock signal having a constant frequency and dynamically change the power supply voltage according to the processing capability required for the circuit.

  For example, the semiconductor device 100A is a logic LSI such as a gate array, or a CPU (Central Processing Unit) including a processor core or a system LSI (Large Scale Integration).

  The semiconductor device 100A includes a load control unit 10, a power management unit 12, a clock control unit 14, a clock distribution unit 16, a switching unit 18, and a logic circuit unit 20. The semiconductor device 100A is supplied in the form of a chip. For example, the load control unit 10, the power management unit 12, and the clock control unit 14 are different from the clock distribution unit 16, the switching unit 18, and the logic circuit unit 20. May be provided. In this case, the power supply voltage VDD, the clock signal CLK0, and the connection control signal CN are supplied from the outside of the semiconductor device 100A.

  The load control unit 10 receives load information LDINF indicating the processing capability required for the logic circuit unit 20 from the outside of the semiconductor device 100A. The load control unit 10 outputs the voltage information VINF indicating the value of the power supply voltage VDD to the power management unit 12 in order to realize the processing capability requested by the logic circuit unit 20, and the frequency indicating the frequency value of the clock signal CLK. The information FINF is output to the clock control unit 14. Note that the load control unit 10 may receive load information LDINF generated in the semiconductor device 100A. When the semiconductor device 100A generates the clock signal CLK0 having a constant frequency, for example, the load control unit 10 generates the constant frequency information FINF regardless of the load information LDINF.

  The power management unit 12 includes a voltage generation unit VGEN and an analog / digital converter ADC. The voltage generation unit VGEN generates the power supply voltage VDD indicated by the voltage information VINF using the power supply voltage VDD0 received from the outside of the semiconductor device 100A. The analog-digital converter ADC converts the value of the power supply voltage VDD into power supply voltage information VDDINF that is a digital value, and outputs the power supply voltage information VDDINF to the clock control unit 14.

  For example, the power supply voltage information VDDINF is a value obtained by encoding the value of the power supply voltage VDD in units of 10 millivolts (mV), and is represented by 7 bits. When the power supply voltage VDD is 0.5 V, the power supply voltage information VDDINF is represented by a binary number “0110010” (decimal number 50). When the power supply voltage VDD is 1.2 V, the power supply voltage information VDDINF is represented by binary “1111000” (decimal 120).

  When the value of the power supply voltage information VDDINF corresponds to the value of the voltage information VINF, the power management unit 12 may not have the analog-digital converter ADC. In this case, the voltage information VINF is supplied to the clock control unit 14 instead of the power supply voltage information VDDINF.

  The clock control unit 14 includes a ROM (Read Only Memory), a comparison unit COMP, and a clock generation unit CGEN. The ROM stores voltage information Vm indicating the switching voltage, and outputs the voltage information Vm to the comparison unit COMP. For example, the voltage information Vm is represented by 7 bits similarly to the power supply voltage information VDDINF.

  For example, the ROM is a fuse circuit. Note that when the semiconductor device 100A includes a nonvolatile memory, a part of the nonvolatile memory may be used as a ROM. Further, the ROM may be designed using a wiring pattern arranged in the semiconductor device 100A. In this case, the ROM information is included in the photomask pattern used for forming the wiring pattern in the manufacturing process of the semiconductor device 100A. For example, the bit indicating logic 1 in the voltage information Vm is connected to the power supply line VDD0, and the bit indicating logic 0 is connected to the ground line VSS.

  The comparison unit COMP compares the power supply voltage information VDDINF indicating the value of the power supply voltage VDD with the voltage information Vm, and generates a connection control signal CN according to the comparison result. By determining the magnitude relationship between the power supply voltage VDD and the predetermined value indicated by the voltage information Vm by the comparison unit COMP, the connection / disconnection of the clock mesh CMESH can be accurately controlled based on the power supply voltage VDD.

  The connection control signal CN is a logic that connects the output node of the clock distribution unit 16 to the clock mesh CMESH when the value of the power supply voltage VDD indicated by the power supply voltage information VDDINF is equal to or lower than the voltage value indicated by the voltage information Vm (for example, High level). In addition, the connection control signal CN is a logic that disconnects the output node of the clock distribution unit 16 from the clock mesh CMESH when the value of the power supply voltage VDD indicated by the power supply voltage information VDDINF is higher than the voltage value indicated by the voltage information Vm (for example, , Low level). Thus, the connection control signal CN functions as a switching signal for switching between connection and non-connection of the clock mesh CMESH.

  Instead of the comparison unit COMP, a comparison unit such as an analog comparator that compares the power supply voltage VDD and the reference voltage indicated by the voltage information Vm may be arranged. In this case, the power management unit 12 does not have the analog-digital converter ADC. The clock mesh CMESH is an example of a load unit. The high level of the connection control signal CN is an example of a connection signal, and the low level of the connection control signal CN is an example of a disconnection signal.

  The clock generation unit CGEN includes, for example, an oscillator, and generates a clock signal CLK0 having a frequency indicated by the frequency information FINF. The clock generation unit CGEN may generate a clock signal CLK0 having a frequency indicated by the frequency information FINF using an oscillation signal from a crystal oscillator or the like disposed inside or outside the semiconductor device 100A.

  Note that, when the power supply voltage VDD is changed in conjunction with the change of the frequency of the clock signal CLK0, the comparison unit COMP displays information indicating the value of the power supply voltage VDD generated corresponding to the frequency information FINF as the voltage information Vm. May be compared. Alternatively, the clock control unit 14 includes a circuit that detects the frequency of the clock signal CLK0, and generates the connection control signal CN by comparing the detected frequency with frequency information corresponding to the voltage information Vm. Good.

  The clock distribution unit 16 includes a plurality of clock buffers CBUF that branch the clock signal CLK0 and generate a plurality of clock signals CLKa1, CLKb1, CLKc1, and CLKd1. In FIG. 2, the number of branches of the clock signal CLK0 is smaller than the actual number in order to make the drawing easier to see. That is, the number of branches of the clock signal CLK0 is not limited to four in FIG.

  The switching unit 18 includes switches SW (SWa, SWb, SWc, SWd) that connect the clock signal lines CLKa1, CLKb1, CLKc1, CLKd to the clock mesh CMESH. For example, the switches SWa, SWb, SWc, SWd are turned on when the connection control signal CN is at a high level, and connect the clock signal lines CLKa1, CLKb1, CLKc1, CLKd to the clock mesh CMESH. The switches SWa, SWb, SWc, and SWd are turned off when the connection control signal CN is at a low level, and the connection between the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 and the clock mesh CMESH is released. The switches SWa, SWb, SWc, and SWd may be turned on when the connection control signal CN is at a low level and turned off when the connection control signal CN is at a high level. In this case, the determination logic of the determination unit COMP is opposite to that described above.

  The logic circuit unit 20 includes a plurality of clock buffers CBUF that receive the clock signals CLKa1, CLKb1, CLKc1, and CLKd1 and output the clock signals CLKa2, CLKb2, CLKc2, and CLKd2, respectively. The logic circuit unit 20 includes a logic circuit including a flip-flop FF that operates in response to the clock signals CLKa2, CLKb2, CLKc2, and CLKd2. The logic circuit unit 20 operates with the power supply voltage VDD generated by the power supply circuit unit 12. In practice, various combinational logic circuits exist between the flip-flops FF, but are omitted here for simplicity. Note that the logic circuit unit 20 inputs and outputs control signals and data signals other than the clock signals CLKa1, CLKb1, CLKc1, and CLKd1 inside the semiconductor device 100A, and sends the control signals and data signals to the outside of the semiconductor device 100A. Input / output may be used.

  In FIG. 2, the clock distribution unit 16, the switching unit 18, the clock mesh CMESH, and the logic circuit unit 20 are separated from each other for easy understanding, but in practice, they are overlapped in a common area. Is done.

  FIG. 3 shows an example of the clock distribution unit 16, the switching unit 18, the clock mesh CMESH, and the logic circuit unit 20 shown in FIG. For example, the switches SW (SWa, SWb) of the switching unit 18 are CMOS transmission gates in which the sources and drains of an nMOS transistor and a pMOS transistor are connected to each other. As illustrated in FIG. 6, the clock mesh CMESH is wired in a lattice pattern in the logic circuit unit 20, for example. By connecting the clock signal lines CLKa1 and CLKb1 to the clock mesh CMESH using a switch SW such as a CMOS transmission gate, connection / disconnection of the clock mesh CMESH can be controlled by the connection control signal CN that is a logical signal.

  The switches SWa and SWb are turned on when the connection control signal CN is at a high level, and connect the clock signal lines CLKa1 and CLKb1 to the clock mesh CMESH. In this case, since the clock signal lines CLKa1 and CLKb1 are short-circuited via the clock mesh CMESH, the amount of clock skew of the clock signals CLKa1 and CLKb1 is smaller than when the clock signal lines CLKa1 and CLKb1 are not short-circuited. Here, the clock skew is a shift (variation) in timing of transition edges of the clock signals CLKa1 and CLKb1.

  However, when the switches SWa and SWb are turned on, the clock signal lines CLKa1 and CLKb1 are connected to the clock mesh CMESH which is a common load. For this reason, the charge / discharge current due to the clock pulse of the clock buffer CBUF that outputs the clock signals CLKa1 and CLKb1 increases as compared with the case where the switches SWa and SWb are turned off, and the power consumption increases.

  On the other hand, the switches SWa and SWb are turned off when the connection control signal CN is at a low level, and the connection between the clock signal lines CLKa1 and CLKb1 and the clock mesh CMESH is released. In this case, since the clock signals CLKa1 and CLKb1 are generated independently without being short-circuited, the clock skew of the clock signals CLKa1 and CLKb1 becomes larger than that when the clock signal lines CLKa1 and CLKb1 are short-circuited.

  However, the clock signal lines CLKa1 and CLKb1 are disconnected from the clock mesh CMESH when the power supply voltage VDD is higher than a predetermined value indicated by the voltage information Vm. Since the clock skew becomes smaller as the power supply voltage VDD is higher, the influence of the increase in the clock skew is smaller than when the power supply voltage VDD is low.

  Further, when the switches SWa and SWb are turned off, the clock buffer CBUF that outputs the clock signals CLKa1 and CLKb1 does not drive the clock mesh CMESH. Therefore, the charge / discharge current due to the clock pulse of the clock buffer CBUF that outputs the clock signals CLKa1 and CLKb1 is reduced as compared with the case where the switches SWa and SWb are turned on, and the power consumption is reduced.

  The flip-flop FF that receives the clock signal CLKa2 latches the data signal DT0 in synchronization with the clock signal CLKa2, and outputs it as the data signal DT1. The flip-flop FF that receives the clock signal CLKb2, for example, latches the data signal DT2 obtained by delaying the data signal DT1 by the inverter IV and the hold buffer HBUF, and outputs the data signal DT3.

  As shown in FIG. 3, a hold buffer HBUF that delays the data signal DT2 is inserted between the flip-flop FF that receives the clock signal CLKa2 and the flip-flop FF that receives the clock signal CLKb2. The hold buffer HBUF will be described with reference to FIG.

  FIG. 4 shows an example of the operation of the logic circuit unit 20 shown in FIG. For example, the upper waveform in FIG. 4 shows the case where the power supply voltage VDD is set to the maximum operable value VDDmax, and the lower waveform in FIG. 4 is the minimum value VDDmin at which the power supply voltage VDD can operate. Indicates the case where it is set. The oblique lines shown in the clock signal CLKb2 indicate the range of the clock skew of the clock signal CLKb2 with respect to the clock signal CLKa2.

  When the power supply voltage VDD is high (VDDmax), the operation speed of each circuit of the logic circuit unit 20 is high, and the propagation delay time of the signal transmitted inside the logic circuit 20 is shorter than when the power supply voltage VDD is low. Become. Further, when the power supply voltage VDD is high, variations in signal propagation timing due to OCV (On Chip Variation) are less likely to occur, and variations in circuit operation speed due to variations in the power supply voltage VDD and ground voltage VSS due to noise are less likely to appear. Thereby, for example, the clock skew of the clock signal CLKb2 with respect to the clock signal CLKa2 is smaller than that when the power supply voltage VDD is low. Note that OCV refers to variations in transistor characteristics, wiring resistance, and the like in a semiconductor chip due to manufacturing processes.

  As described above, when the power supply voltage VDD is high, the hold constraint that is the specification of the time for holding the logic of the data signal DT2 from the transition edge of the clock signal CLKb2 is satisfied regardless of the magnitude of the clock skew. For example, if the hold time is zero, the clock skew allowed for the clock signal CLKb2 with respect to the clock signal CLKa2 is from the rising edge of the clock signal CLKa2 until the data signal DT2 reaches the flip-flop FF. Here, the clock skew is allowed from the rising edge of the clock signal CLKa2 to the rising edge of the clock signal CLKb2.

  On the other hand, when the power supply voltage VDD is low (VDDmin), the operation speed of each circuit of the logic circuit unit 20 is low, and the propagation delay time of the signal transmitted inside the logic circuit 20 is higher than that when the power supply voltage VDD is high. Become longer. Further, when the power supply voltage VDD is low, variations in signal propagation timing due to OCV tend to appear, and variations in circuit operation speed due to fluctuations in the power supply voltage VDD and ground voltage VSS due to noise also tend to appear. Thereby, for example, the clock skew of the clock signal CLKb2 with respect to the clock signal CLKa2 becomes larger than when the power supply voltage VDD is high.

  When the clock skew increases and the rising edge of the clock signal CLKb2 becomes later than the change timing of the data signal DT2, the time margin tM for satisfying the hold constraint of the flip-flop FF that receives the clock signal CLKb2 and the data signal DT2 becomes a negative value. . As a result, the flip-flop FF that receives the clock signal CLKb2 cannot latch the original data value D0 and may latch the data value D1 after one clock cycle.

  Actually, as shown in FIG. 3, at least one hold buffer HBUF functioning as a delay circuit is inserted in the propagation path of the data signal DT2 so that the flip-flop FF does not latch the erroneous data value D1. . Then, as shown at the bottom of FIG. 4, the hold constraint is satisfied by delaying the supply timing of the data signal DT2 to the flip-flop FF by inserting the hold buffer HBUF.

  As shown in FIG. 3, the clock skew can be reduced by connecting the clock mesh CMESH to the clock signal lines CLKa1 and CLKb1 via the switches SWa and SWb. This minimizes the number of hold buffer HBUF insertions.

  FIG. 5 shows an example of a method for determining the voltage information Vm shown in FIG. For example, the voltage information Vm is obtained by, for example, circuit simulation after designing the logic circuit unit 20 shown in FIG. The number of hold buffers HBUF shown in FIG. 2 is determined during the design of the logic circuit unit 20.

  A characteristic C1 shows the dependency of the clock skew on the power supply voltage VDD when the clock mesh CMESH is not connected to the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1. A characteristic C2 indicates the dependency of the clock skew on the power supply voltage VDD when the clock mesh CMESH is connected to the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1.

  As described with reference to FIG. 4, the clock skew is larger when the power supply voltage VDD is lower than when the power supply voltage VDD is high. As described with reference to FIG. 3, the clock skew is caused when the clock mesh CMESH is connected to the path of the clock signal CLK0 (characteristic C2) and when the clock mesh CMESH is not connected to the path of the clock signal CLK0 (characteristic C1). ) Smaller than

  A characteristic C3 indicates a clock skew allowed when the clock skew of the characteristic C2 at the minimum operation guaranteed voltage of the semiconductor device 100A is used as a reference. In the characteristics C1 and C2, the region where the clock skew is larger than the characteristic C3 does not satisfy the hold constraint, and the time margin tM for satisfying the hold constraint may be the negative value shown in FIG. On the other hand, in the characteristics C1 and C2, the region where the clock skew is smaller than that of the characteristic C3 satisfies the hold constraint.

  Therefore, in this embodiment, the voltage information Vm is set to the smallest value of the power supply voltage VDD within a range where the characteristic C1 in which the clock mesh CMESH is not connected to the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 satisfies the hold constraint. The The voltage value indicated by the voltage information Vm is within a range of the power supply voltage VDD in which the characteristic C1 satisfies the hold constraint in a state where the clock mesh CMESH is disconnected from the clock signal line (CLKa1 or the like) (for example, the power supply voltage VDD The lower side may be set. As a result, the hold constraint can be satisfied in all power supply voltages VDD between the lowest guaranteed operating voltage and the highest guaranteed operating voltage. In other words, the clock mesh CMESH can be disconnected from the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 without violating the hold constraint.

  FIG. 6 shows an example of the arrangement of the clock mesh CMESH and the switches SW (SWa, SWb, SWc, SWd) shown in FIG. In FIG. 6, the thick solid line indicates the clock mesh CMESH, the thin solid line indicates the clock signal line, and the shaded rectangle indicates the switch SW of the switching unit 18 illustrated in FIG. For example, the clock mesh CMESH, the clock distribution unit 16, and the switching unit 18 (switch SW) are arranged in the logic circuit unit 20 shown in FIG.

  For example, the clock mesh CMESH is arranged in a lattice pattern in the logic circuit unit 20. The clock mesh CMESH may be arranged in a mesh shape. For example, the clock signal CLK0 is sequentially branched from the vicinity of the center of the logic circuit unit 20 toward the outside by the clock buffer CBUF of the clock distribution unit 16, and the clock signal CLK0 is clocked through the switch SW arranged corresponding to the intersection of the lattices. Connected to mesh CMESH. That is, the switching unit 18 is arranged at the intersection of the signal lines of the clock mesh CMESH. As a result, the switches SW are distributed in the logic circuit unit 20, so that the clock skew does not depend on the position in the logic circuit unit 20 when the clock signal CLKa 1 or the like is connected to the clock mesh CMESH. Can be reduced on average.

  FIG. 7 shows an example of operation modes of the semiconductor device 100A shown in FIG. For example, the semiconductor device 100A is set to one of four operation modes MD (MD1, MD2, MD3, MD4) according to the processing capability required for the logic circuit unit 20.

  In the operation mode MD1, the frequency of the clock signal CLK0 is set to F1, and the power supply voltage VDD is set to V1. In the operation mode MD2, the frequency of the clock signal CLK0 is set to F2, and the power supply voltage VDD is set to V2. In the operation mode MD3, the frequency of the clock signal CLK0 is set to F3, and the power supply voltage VDD is set to V3. In the operation mode MD4, the frequency of the clock signal CLK0 is set to F4, and the power supply voltage VDD is set to V4.

  For example, the magnitude relationship of the frequency of the clock signal CLK0 is F1 <F2 <F3 <F4, and the magnitude relationship of the power supply voltage VDD is V1 <V2 <V3 <V4. Although not particularly limited, for example, the frequency F1 is 1 M (mega) Hz, the frequency F2 is 10 MHz, the frequency F3 is 100 MHz, and the frequency F4 is 1000 MHz (= 1 GHz). Although not particularly limited, for example, the power supply voltage V1 is 0.3V, the power supply voltage V2 is 0.5V, the power supply voltage V3 is 0.8V, and the power supply voltage V4 is 1.2V. In other words, the processing capability required for the logic circuit unit 20 of the semiconductor device 100A increases in the order of the operation modes MD1, MD2, MD3, and MD4.

  The semiconductor device 100A can move between the operation modes MD1 and MD2 and can move between the operation modes MD1 and MD3. Further, the semiconductor device 100A can move between the operation modes MD2 and MD3, can move between the operation modes MD2 and MD4, and can move between the operation modes MD3 and MD4.

  In this example, the voltage information Vm illustrated in FIG. 2 indicates a value (for example, 0.65 V) between the power supply voltage VDD2 and the power supply voltage VDD3. In the operation modes MD1 and MD2, the connection control signal CN is set to the high level H, and the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 shown in FIG. 2 are connected to the clock mesh CMESH. In the operation modes MD3 and MD4, the connection control signal CN is set to the low level L, and the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 are disconnected from the clock mesh CMESH.

  FIG. 8 shows an example of the dependency of the energy consumption on the power supply voltage VDD in the semiconductor device 100A shown in FIG. For example, energy consumption is represented by J / cycle (joule / clock cycle).

  In FIG. 8, an alternate long and short dash line C4 indicates characteristics when the clock mesh CMESH is connected to the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1. An alternate long and short dash line C5 indicates characteristics when the clock mesh CMESH is not connected to the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1. An alternate long and two short dashes line C6 indicates characteristics (semiconductor device having no clock mesh CMESH) when the hold buffer HBUF is inserted in FIG. A thick solid line shows the characteristic of energy consumption in this embodiment. The thick solid line overlaps with the characteristic C4 in a region below the power supply voltage VDD indicated by the voltage information Vm, and overlaps with the characteristic C5 in a region higher than the power supply voltage VDD indicated by the voltage information Vm.

  In this embodiment, the clock mesh CMESH is disconnected from the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 at the power supply voltage VDD (V3, V4) with a large current for charging and discharging the parasitic capacitance of the clock mesh CMESH. Thereby, the energy consumption is reduced as compared with the case where the clock mesh CMESH is connected to the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 (characteristic C4) (FIG. 8A).

  The clock mesh CMESH is connected to the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 at the power supply voltage VDD (V1, V2) in which the leakage current between the source and drain of the transistor relatively increases. As a result, the number of hold buffer HBUF insertions is reduced and the total leakage current amount of the hold buffer HBUF is reduced as compared with a semiconductor device not having the clock mesh CMESH indicated by the characteristic C6, so that energy consumption is reduced (FIG. 8 (b)).

  As described above, the operation modes MD3 and MD4 have characteristics close to the characteristic C6 without the clock mesh CMESH, and the operation modes MD1 and MD2 have characteristics close to the characteristic C4 that can minimize the number of hold buffers HBUF. As described above, in this embodiment, since the connection of the clock mesh CMESH is dynamically switched according to the operation modes MD1 to MD4, energy consumption can be reduced compared to the conventional case regardless of the power supply voltage VDD.

  FIG. 9 shows an example of the operation of the semiconductor device 100A shown in FIG. In this example, the semiconductor device 100A shifts from the operation mode MD4 to the operation mode MD2, and further shifts from the operation mode MD2 to the operation mode MD3. A code SWP indicated by shading is a transition period when the operation mode MD is switched. For example, it is a switching period until the power supply voltage VDD changes to a predetermined value.

  Reference numerals LD1, LD2, LD3, and LD4 indicated in the load information LDINF indicate the magnitude (load) of the processing capability required for the logic circuit unit 20, and the operation modes MD1, MD2, MD3, and MD4 shown in FIG. Each corresponds. That is, the load increases in the order of LD1 <LD2 <LD3 <LD4.

  For example, a change in the load information LDINF from LD4 to LD2 indicates an instruction to shift from the operation mode MD4 to the operation mode MD2, and a change in the load information LDINF from LD2 to LD3 indicates a change from the operation mode MD2 to the operation mode MD3. Indicates migration instructions. The load control unit 10 shown in FIG. 2 generates frequency information FINF indicating the frequency of the clock signal CLK0 to be set and voltage information VINF indicating the value of the power supply voltage VDD to be set based on the load information LDINF. As shown in FIG. 7, the frequency information FINF indicates any one of the frequencies F1, F2, F3, and F4, and the voltage information VINF indicates any one of the power supply voltages V1, V2, V3, and V4.

  In the operation mode MD4, the clock mesh CMESH is disconnected from the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 (FIG. 9A). When the operation mode MD4 is switched to the operation mode MD2, the comparison circuit COMP changes the connection control signal CN from the low level to the high level in response to the power supply voltage VDD being equal to or lower than the predetermined value indicated by the voltage information Vm. (FIG. 9B). Thus, the clock mesh CMESH is connected to the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 (FIG. 9C).

  When the operation mode MD2 is switched to the operation mode MD3, the comparison circuit COMP changes the connection control signal CN from the high level to the low level in response to the power supply voltage VDD becoming higher than a predetermined value indicated by the voltage information Vm. (FIG. 9 (d)). As a result, the clock mesh CMESH is disconnected from the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 (FIG. 9 (e)).

  When the power supply voltage VDD changes from the high side to the low side (for example, transition from the operation mode MD4 to the operation mode MD2), the logic circuit unit 20 can start the operation without waiting for the power supply voltage VDD to decrease. is there. In other words, the logic circuit unit 20 can start an operation in a new operation mode during the switching period SWP. On the other hand, when the power supply voltage VDD transitions from the low side to the high side (for example, transition from the operation mode MD2 to the operation mode MD3), the logic circuit unit 20 increases the power supply voltage VDD to a specified value (for example, V3). After starting the operation. In other words, when the power supply voltage VDD transitions from the low side to the high side, the logic circuit unit 20 starts the operation in the new operation mode after the switching period SWP.

  As described above, also in this embodiment, as in the embodiment shown in FIG. 1, an increase in power consumption of the semiconductor device 100A can be suppressed while suppressing clock skew regardless of the power supply voltage VDD. Further, in this embodiment, the comparison unit COMP connects / disconnects the clock mesh CMESH to the clock signal line (CLKa1, etc.) in order to determine the magnitude relationship between the power supply voltage VDD and the predetermined value indicated by the voltage information Vm. Can be accurately controlled based on the power supply voltage VDD.

  Further, as shown in FIG. 5, the voltage information Vm indicates that the power supply voltage VDD is low within the range in which the characteristic C1 in which the clock mesh CMESH is not connected to the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 satisfies the hold constraint. Set to As a result, the clock mesh CMESH can be disconnected from the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 without violating the hold constraint.

  The clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 are connected to the clock mesh CMESH using switches SWa, SWb, SWc, and SWd such as CMOS transmission gates. Thereby, the connection / disconnection of the clock mesh CMESH can be controlled by the connection control signal CN which is a logic signal.

  As shown in FIG. 6, since the switch SW is arranged at the intersection of the signal lines of the clock mesh CMESH, the switch SW is arranged in a distributed manner in the logic circuit unit 20. Thereby, when the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 are connected to the clock mesh CMESH, the clock skew can be reduced on average without depending on the position in the logic circuit unit 20.

  FIG. 10 shows another embodiment of a semiconductor device and a method for controlling the semiconductor device. Elements that are the same as or similar to the elements described in the above-described embodiment are assigned the same reference numerals, and detailed descriptions thereof are omitted. The semiconductor device 100B of this embodiment has a power management unit 12B and a clock control unit 14B instead of the power management unit 12 and the clock control unit 14 shown in FIG.

  Other configurations of the semiconductor device 100B are the same as those of the semiconductor device 100A illustrated in FIG. That is, the semiconductor device 100B has the same configuration as that of FIGS. 3 and 6, the transition of the operation mode of the semiconductor device 100B is shown in FIG. 7, and an example of the characteristics of the semiconductor device 100B is shown in FIG. .

  The power management unit 12B is the same as the power management unit 12 shown in FIG. 2 except that the power management unit 12B does not have the analog-digital converter ADC. That is, the power supply management unit 12B generates the power supply voltage VDD indicated by the voltage information VINF from the load control unit 10 using the power supply voltage VDD0 received from the outside of the semiconductor device 100B.

  The clock control unit 14B includes a mode detection unit MDDET, a switch table SWTBL, a connection control unit CNCNT, and a clock generation unit CGEN. The function of the clock generation unit CGEN is the same as that of the clock generation unit CGEN shown in FIG.

  The mode detection unit MDDET detects the operation mode MD (any one of MD1-MD4) based on the voltage information VINF and the frequency information FINF from the load control unit 10. Note that the mode detection unit MDDET may detect the operation mode MD from the voltage information VINF without using the frequency information FINF. The mode detection unit MDDET holds mode information PMD indicating the detected operation mode MD, and outputs the held mode information PMD to the connection control unit CNCNT.

  The switch table SWTBL stores information on standby time when the operation mode MD is switched. For example, the waiting time when the operation mode MD2 (previous mode) is switched to the operation mode MD3 (current mode) is T1. The waiting time when the operation mode MD1 is switched to the operation mode MD3 is T2. The waiting time when the operation mode MD2 is switched to the operation mode MD4 is T3. On the other hand, the waiting time other than the above three switching operations is zero. Note that “0 (don't Care)” shown in the standby time indicates switching of the operation mode MD in which the logic of the connection control signal CN is not changed. The switch table SWTBL outputs table information TBLINF indicating the standby time in response to a request from the connection control unit CNCNT.

  The standby times T1, T2, and T3 are set according to the magnitude of the increase value of the power supply voltage VDD when the operation mode MD is switched. For example, the power supply voltages VDD in the operation modes MD1, MD2, MD3, and MD4 are 0.3V, 0.5V, 0.8V, and 1.2V, respectively, similarly to the semiconductor device 100 illustrated in FIG. The power supply voltage VDD increases by 0.3 V when switching from the operation mode MD2 to the operation mode MD3, increases by 0.5 V when switching from the operation mode MD1 to the operation mode MD3, and changes from the operation mode MD2 to the operation mode MD4. It rises 0.7V when switching. For example, the standby times T1, T2, and T3 become longer in this order in proportion to 0.3V, 0.5V, and 0.7V.

  When the connection control unit CNCNT detects the switching of the operation mode MD based on the mode information PMD from the mode detection unit MDDET, the connection control unit CNCNT accesses the switch table SWTBL and reads the waiting time (TBLINF) when switching the operation mode MD. The connection control unit CNCNT may include a latch circuit in order to hold information on an operation mode (previous mode) before the operation mode is switched.

  When switching from the operation mode MD2 to the operation mode MD3, the connection control unit CNCNT reads the waiting time T1 in the second row from the top as the table information TBLINF in the switch table SWTBL. When switching from the operation mode MD1 to the operation mode MD3, the connection control unit CNCNT reads the waiting time T2 in the third row from the top as the table information TBLINF in the switch table SWTBL. When switching from the operation mode MD2 to the operation mode MD4, the connection control unit CNCNT reads the waiting time T3 in the fourth row from the top as the table information TBLINF in the switch table SWTBL. When the switching of the operation mode MD is accompanied by the disconnection of the clock mesh CMESH, the connection control unit CNCNT changes the connection control signal CN to a low level after a predetermined time indicated by the read standby time.

  FIG. 11 is a diagram illustrating an example of the operation of the semiconductor device 100B illustrated in FIG. Detailed description of the same or similar operations as in FIG. 9 will be omitted. Also in this example, as in FIG. 9, the semiconductor device 100B shifts from the operation mode MD4 to the operation mode MD2, and further shifts from the operation mode MD2 to the operation mode MD3. Changes in load information LDINF, frequency information FINF, voltage information VINF, and power supply voltage VDD are the same as in FIG.

  For example, when switching from the operation mode MD4 to the operation mode MD2, the connection control unit CNCNT refers to the seventh row of the switch table SWTBL shown in FIG. 10 and recognizes that the standby time is zero. Then, the connection control unit CNCNT changes the connection control signal CN from the low level to the high level in accordance with the switching timing from the operation mode MD4 to the operation mode MD2 (FIG. 11 (a)). The clock mesh CMESH is connected to the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 by the high-level connection control signal CN (FIG. 11B).

  On the other hand, when switching from the operation mode MD2 to the operation mode MD3, the connection control unit CNCNT refers to the second row of the switch table SWTBL shown in FIG. 10 and recognizes that the standby time is T1. Then, the connection control unit CNCNT changes the connection control signal CN from the high level to the low level after the standby time T1 from the switching timing from the operation mode MD2 to the operation mode MD3 (FIG. 11 (c)). The clock mesh CMESH is disconnected from the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 by the low level connection control signal CN (FIG. 11 (d)).

  In this embodiment, disconnection of the clock mesh CMESH from the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 is prohibited until the power supply voltage VDD rises to a predetermined value. Accordingly, the clock mesh CMESH is not disconnected from the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 before the power supply voltage VDD rises to a predetermined value, and the clock skew does not increase. In other words, in FIG. 5, at the power supply voltage VDD lower than the value indicated by the voltage information Vm, the clock skew does not show the characteristic C1, and the hold constraint violation can be avoided. As a result, it is possible to prevent the logic circuit unit 20 from malfunctioning.

  As described above, also in this embodiment, as in the embodiment shown in FIG. 1, an increase in power consumption of the semiconductor device 100B can be suppressed while suppressing clock skew regardless of the power supply voltage VDD. Similarly to the embodiment shown in FIG. 2, the clock mesh CMESH can be disconnected from the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 without violating the hold constraint. The connection / disconnection of the clock mesh CMESH can be controlled by the connection control signal CN which is a logic signal. By arranging the switch SW at the intersection of the signal lines of the clock mesh CMESH, the clock skew can be reduced on average when the clock signal lines CLKa1, CLKb1, CLKc1, and CLKd1 are connected to the clock mesh CMESH.

  Further, in switching from the operation mode MD with the low power supply voltage VDD to the operation mode MD with the high power supply voltage VDD, it is possible to avoid the violation of the hold constraint due to the clock skew, and to avoid the malfunction of the logic circuit unit 20. Can do.

  FIG. 12 shows another embodiment of a semiconductor device and a method for controlling the semiconductor device. Elements that are the same as or similar to those described in FIGS. 2 to 9 are given the same reference numerals, and detailed descriptions thereof are omitted.

  The semiconductor device 100C of this embodiment includes a switching unit 18C instead of the switching unit 18 illustrated in FIG. Other configurations of the semiconductor device 100C are the same as those of the semiconductor device 100A illustrated in FIG. That is, the semiconductor device 100C includes the load control unit 10, the power management unit 12, the clock control unit 14, the clock distribution unit 16, the clock mesh CMESH, and the logic circuit unit 20 illustrated in FIG. The semiconductor device 100C has the same configuration as that of FIG. 6, with the voltage information Vm determined by the same method as that of FIG. Further, the transition of the operation mode of the semiconductor device 100C is shown in FIG. An example of the characteristics of the semiconductor device 100C is shown in FIG. 8, and an example of the operation of the semiconductor device 100C is shown in FIG.

  The switching unit 18C includes two 2-input AND circuits AND1 and AND2 and one 2-input OR circuit OR for each of the clock signal lines CLKa1 and CLKb1. The AND circuit AND1 receives the connection control signal CN and the clock signal CLKa1 (or CLKb1), and supplies an output signal to one input of the OR circuit OR via the first path P1. The output of the AND circuit AND1 (that is, the first path P1) is connected to the clock mesh CMESH.

  The AND circuit AND2 receives the signal / CN obtained by inverting the connection control signal CN by the inverter IV and the clock signal CLKa1 (or CLKb1), and supplies the output signal to the other input of the OR circuit OR through the second path P2. The connection control signal CN is an example of a first control signal, and a signal / CN obtained by inverting the connection control signal CN by the inverter IV is an example of a second control signal.

  The AND circuit AND1 supplies the clock signal CLKa1 (or CLKb1) to the logic circuit unit 20 through the first path P1 connected to the clock mesh CMESH and the OR circuit OR while the connection control signal CN is at a high level. The AND circuit AND2 supplies the clock signal CLKa1 (or CLKb1) to the logic circuit unit 20 through the second path P2 and the OR circuit OR that are not connected to the clock mesh CMESH while the connection control signal CN is at the low level.

  That is, the AND circuits AND1, AND2, and the OR circuit OR function as a selector that connects the clock signal CLKa1 (or CLKb1) to the first path P1 or the second path P2 in accordance with the power supply voltage VDD. The selector connects the clock signal line to the first path P1 connected to the clock mesh CMESH when the power supply voltage VDD is equal to or less than a predetermined value, and the clock mesh CMESH connects the clock signal line when the power supply voltage VDD is higher than the predetermined value. Connect to the second path P2 that is not connected.

  The switching unit 18C has the same function as the switching unit 18 shown in FIG. However, in this embodiment, there is no resistance component by a switch such as a CMOS transmission gate between the clock mesh CMESH and the clock buffer CBUF of the logic circuit unit 20, and the clock mesh CMESH is connected to the input of the OR circuit OR. The Therefore, the clock skew can be reduced compared to the example shown in FIG.

  Further, during the period when the connection control signal CN is set to the low level, the output of the AND circuit AND1 is fixed to the low level. For this reason, the clock mesh CMESH can function as a capacitor that stabilizes the voltage of the ground line during a period in which the clock mesh CMESH is not connected to the clock signal lines CLKa1 and CLKb1. The period in which the clock mesh CMESH is not connected to the clock signal lines CLKa1 and CLKb1 is a period in which the value of the power supply voltage VDD is higher than the value indicated by the voltage information Vm (V3 or V4 shown in FIG. 7), and power supply noise is likely to occur. . In this embodiment, the noise resistance can be improved by using the clock mesh CMESH as the power supply stabilization capacitor during the operation mode MD in which the power supply voltage VDD is high.

  For example, in the evaluation by circuit simulation, when the switching unit is 18C shown in FIG. 12 in the logic circuit unit 20 having the clock distribution unit 16 shown in FIG. 6, the energy consumption (clock) when the power supply voltage VDD is V4 is shown. The mesh CMESH is detached) is 3.66 picojoules (pJ). On the other hand, when the logic circuit unit 20 having the clock distribution unit 16 shown in FIG. 6 does not have the switching unit 18 shown in FIG. 3 (connected to the clock mesh CMESH regardless of the power supply voltage VDD), the power supply voltage When VDD is V4, the energy consumption is 4.92 pJ. Therefore, for example, in the power supply voltage V4 where the charge / discharge current of the clock signal line (CLKa1 and the like) increases, the energy consumption can be reduced by about 25% by separating the clock mesh CMESH from the clock signal line by the switching unit 18C.

  Note that the switching unit 18C illustrated in FIG. 12 may be arranged instead of the switching unit 18 illustrated in FIG. In this case, similarly to the semiconductor device 100B shown in FIG. 10, in switching to the operation mode MD in which the power supply voltage VDD is high, it is possible to avoid a hold constraint being violated due to clock skew.

  As described above, also in this embodiment, the same effect as that of the embodiment shown in FIGS. 1 to 9 can be obtained. Furthermore, compared to the example shown in FIG. 3, the clock skew can be reduced, and the noise resistance can be improved by using the clock mesh CMESH as the power stabilization capacitor during the operation mode MD in which the power supply voltage VDD is high.

  FIG. 13 shows another embodiment of a semiconductor device and a method for controlling the semiconductor device. Elements that are the same as or similar to those described in FIGS. 2 to 9 are given the same reference numerals, and detailed descriptions thereof are omitted.

  The semiconductor device 100D of this embodiment includes a switching unit 18D instead of the switching unit 18 illustrated in FIG. The other configuration of the semiconductor device 100D is the same as that of the semiconductor device 100A illustrated in FIG. That is, the semiconductor device 100D includes the load control unit 10, the power management unit 12, the clock control unit 14, the clock distribution unit 16, the clock mesh CMESH, and the logic circuit unit 20 illustrated in FIG. The semiconductor device 100D has the same configuration as that of FIG. 6, with the voltage information Vm determined by the same method as that of FIG. Further, the transition of the operation mode of the semiconductor device 100D is shown in FIG. An example of the characteristics of the semiconductor device 100D is shown in FIG. 8, and an example of the operation of the semiconductor device 100D is shown in FIG.

  The switching unit 18D includes three 2-input NAND circuits NAND1, NAND2, and NAND3 for each of the clock signal lines CLKa1 and CLKb1. The NAND circuit NAND1 receives the connection control signal CN and the clock signal CLKa1 (or CLKb1), and supplies an output signal to one input of the NAND circuit NAND3 via the first path P1. The output of the NAND circuit NAND1 (that is, the first path P1) is connected to the clock mesh CMESH.

  The NAND circuit NAND2 receives the signal / CN obtained by inverting the connection control signal CN by the inverter IV and the clock signal CLKa1 (or CLKb1), and supplies the output signal to the other input of the NAND circuit NAND3 via the second path P2. The connection control signal CN is an example of a first control signal, and a signal / CN obtained by inverting the connection control signal CN by the inverter IV is an example of a second control signal.

  The NAND circuit NAND1 supplies the clock signal CLKa1 (or CLKb1) to the logic circuit unit 20 through the first path P1 connected to the clock mesh CMESH and the NAND circuit NAND3 while the connection control signal CN is at a high level. The NAND circuit NAND2 supplies the clock signal CLKa1 (or CLKb1) to the logic circuit unit 20 via the second path P2 not connected to the clock mesh CMESH and the NAND circuit NAND3 while the connection control signal CN is at the low level.

  That is, the NAND circuits NAND1, NAND2, and NAND3 function as a selector that connects the clock signal CLKa1 (or CLKb1) to the first path P1 or the second path P2 in accordance with the power supply voltage VDD. The selector connects the clock signal line to the first path P1 connected to the clock mesh CMESH when the power supply voltage VDD is equal to or less than a predetermined value, and the clock mesh CMESH connects the clock signal line when the power supply voltage VDD is higher than the predetermined value. Connect to the second path P2 that is not connected.

  The switching unit 18D has a function similar to that of the switching unit 18 illustrated in FIG. However, in this embodiment, as in FIG. 12, there is no resistance component due to a switch such as a CMOS transmission gate between the clock mesh CMESH and the clock buffer CBUF of the logic circuit unit 20, and the clock mesh CMESH is a NAND circuit. Connected to the input of NAND3. 12 includes NAND gates and inverters, and the OR circuit OR illustrated in FIG. 12 includes NOR gates and inverters. The NAND circuits NAND1, NAND2, and NAND3 may be NAND gates. For this reason, the number of stages of transistors to which the clock signals CLKa1 and CLKb1 are transmitted can be reduced as compared with FIG. 12, and the influence of OCV can be reduced as compared with FIG. As a result, the clock skew can be reduced as compared with the example shown in FIG. Further, the switching unit 18D including the NAND circuits NAND1, NAND2, and NAND3 can reduce the circuit area as compared with the switching unit 18C including the AND circuits AND1 and AND2 and the OR circuit OR illustrated in FIG.

  Further, during the period when the connection control signal CN is set to the low level, the output of the NAND circuit NAND1 is fixed to the high level. Therefore, the clock mesh CMESH can function as a capacitor that stabilizes the voltage of the power supply line during a period in which the clock mesh CMESH is not connected to the clock signal lines CLKa1 and CLKb1. The period in which the clock mesh CMESH is not connected to the clock signal lines CLKa1 and CLKb1 is a period in which the value of the power supply voltage VDD is higher than the value indicated by the voltage information Vm (V3 or V4 shown in FIG. 7), and power supply noise is likely to occur. . In this embodiment, the noise resistance can be improved by using the clock mesh CMESH as the power supply stabilization capacitor during the operation mode MD in which the power supply voltage VDD is high.

  Note that the switching unit 18D illustrated in FIG. 13 may be disposed instead of the switching unit 18 illustrated in FIG. In this case, similarly to the semiconductor device 100B shown in FIG. 10, in switching to the operation mode MD in which the power supply voltage VDD is high, it is possible to avoid a hold constraint being violated due to clock skew.

  As described above, also in this embodiment, the same effect as that of the embodiment shown in FIGS. 1 to 9 can be obtained. Further, the clock skew can be reduced as compared with the example shown in FIG. 3, and the circuit area can be reduced as compared with the example shown in FIG.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Also, any improvement and modification should be readily conceivable by those having ordinary knowledge in the art. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and appropriate modifications and equivalents included in the scope disclosed in the embodiments can be used.

  DESCRIPTION OF SYMBOLS 10 ... Load control part; 12, 12B ... Power supply management part; 14, 14B ... Clock control part; 16 ... Clock distribution part; 18, 18C, 18D ... Switching part; 20 ... Logic circuit part: 100, 100A, 100B, 100C , 100D ... Semiconductor device; ADC ... Analog-to-digital converter; AND1, AND2 ... AND circuit; CBUF ... Clock buffer; CGEN ... Clock generator; CLK0 ... Clock signal; CLKa1, CLKb1, CLKc1, CLKd1 ... Clock signal line; CLKa2, CLKb2 , CLKc2, CLKd2 ... clock signal; CMESH ... clock mesh; CN ... connection control signal; CNCNT ... connection control unit; CNTU ... control unit; COMP ... comparison unit; FF ... flip-flop; FINF ... frequency information; HBUF ... hold buffer; L INF: load information; LDU: load unit; MD1, MD2, MD3, MD4 ... operation mode; MDDET ... mode detection unit: NAND1, NAND2, NAND3 ... NAND circuit; OR ... OR circuit; P1 ... first path; SWa, SWb, SWc, SWd ... switch; SWTBL ... switch table; SWU ... switching unit; TBLINF ... table information; VINF ... voltage information; VDD, VDD0 ... power supply voltage; VDDINF ... power supply voltage information; VGEN ... voltage generation Part

Claims (10)

A plurality of clock signal lines for transmitting a clock signal;
A load section connectable to the plurality of clock signal lines;
A switching unit that connects the plurality of clock signal lines to the load unit when a power supply voltage is less than or equal to a predetermined value, and disconnects the plurality of clock signal lines from the load unit when the power supply voltage is higher than the predetermined value; A semiconductor device comprising: The power supply voltage is compared with the predetermined value, a connection signal is output to the switching unit when the power supply voltage is less than or equal to the predetermined value, and a disconnection signal is output to the switching unit when the power supply voltage is higher than the predetermined value. It has a comparator to output,
The switching unit connects the plurality of clock signal lines to the load unit based on the connection signal, and disconnects the plurality of clock signal lines from the load unit based on the disconnection signal. 1. The semiconductor device according to 1. The semiconductor device is in any one of at least one first operation mode that operates by receiving the power supply voltage equal to or lower than the predetermined value, and at least one second operation mode that operates by receiving the power supply voltage higher than the predetermined value. Set,
The semiconductor device outputs a disconnection signal after a predetermined time when the first operation mode is switched to the second operation mode, and waits for the predetermined time when the semiconductor device is switched from the second operation mode to the first operation mode. With a connection control unit that outputs connection signals without
The switching unit connects the plurality of clock signal lines to the load unit based on the connection signal, and disconnects the plurality of clock signal lines from the load unit based on the disconnection signal. 1. The semiconductor device according to 1.   The predetermined value is set to a lower side within a range of a power supply voltage that satisfies a clock skew specification of the clock signal in a state where the load unit is disconnected from the plurality of clock signal lines. The semiconductor device according to claim 1.   The switching unit connects the plurality of clock signal lines to the load unit when the power supply voltage is less than or equal to the predetermined value, and connects the plurality of clock signal lines to the load when the power supply voltage is higher than the predetermined value. The semiconductor device according to claim 1, further comprising a switch that is disconnected from the unit. The switching unit connects the plurality of clock signal lines to a first path connected to the load unit when the power supply voltage is less than or equal to the predetermined value, and the plurality of clock signal lines when the power supply voltage is higher than the predetermined value. A selector that connects the clock signal line to a second path to which the load unit is not connected,
5. The semiconductor device according to claim 1, wherein the clock signal is transmitted through the first path or the second path selected by the selector. 6. The selector corresponds to each of the plurality of clock signal lines,
A first AND circuit that receives a first control signal and the clock signal that are set to a high level when the power supply voltage is less than or equal to the predetermined value, and has an output connected to the first path;
A second AND circuit that receives a second control signal and the clock signal that are set to a high level when the power supply voltage is higher than the predetermined value, and has an output connected to the second path;
The semiconductor device according to claim 6, further comprising: an OR circuit having an input connected to an output of the first AND circuit and an output of the second AND circuit. The selector corresponds to each of the plurality of clock signal lines,
A first NAND circuit that receives a first control signal and the clock signal that are set to a high level when the power supply voltage is less than or equal to the predetermined value, and has an output connected to the first path;
A second NAND circuit that receives a second control signal and the clock signal that are set to a high level when the power supply voltage is higher than the predetermined value, and has an output connected to the second path;
The semiconductor device according to claim 6, further comprising: a third NAND circuit having an input connected to an output of the first NAND circuit and an output of the second NAND circuit. The load section includes a plurality of signal lines that are wired vertically and horizontally on the semiconductor device, and whose intersections are connected to each other.
The semiconductor device according to claim 1, wherein the switching unit is disposed at the intersection. A control method of a semiconductor device comprising a plurality of clock signal lines for transmitting a clock signal and a load unit connectable to the plurality of clock signal lines,
The plurality of clock signal lines are connected to the load section when a power supply voltage is a predetermined value or less, and the plurality of clock signal lines are disconnected from the load section when the power supply voltage is higher than the predetermined value. For controlling a semiconductor device.

Images