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JP6020358B2 - Evaluation method of silicon single crystal wafer - Google Patents
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JP6020358B2 - Evaluation method of silicon single crystal wafer - Google Patents

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JP6020358B2
JP6020358B2 JP2013117716A JP2013117716A JP6020358B2 JP 6020358 B2 JP6020358 B2 JP 6020358B2 JP 2013117716 A JP2013117716 A JP 2013117716A JP 2013117716 A JP2013117716 A JP 2013117716A JP 6020358 B2 JP6020358 B2 JP 6020358B2
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JP2014236141A (en
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史高 久米
史高 久米
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Shin Etsu Handotai Co Ltd
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Description

本発明はシリコン単結晶ウェーハの評価方法に関し、より詳しくは、水銀電極を用いてn型シリコン単結晶ウェーハのC−V測定を行う方法に関する。   The present invention relates to a method for evaluating a silicon single crystal wafer, and more particularly to a method for performing CV measurement of an n-type silicon single crystal wafer using a mercury electrode.

従来、シリコン単結晶ウェーハの抵抗率を測定する方法として、C−V(Capacitance−Voltage)特性を測定する方法が知られている。C−V特性を測定するには、試料となるシリコン単結晶ウェーハの表面にショットキー接合を形成し、逆バイアス電圧を連続的に変化させながら印加することによりシリコン単結晶ウェーハの内部に空乏層を拡げて容量を変化させる。シリコン単結晶ウェーハの表面にショットキー接合を形成するために、例えば水銀電極が用いられる。   Conventionally, as a method for measuring the resistivity of a silicon single crystal wafer, a method for measuring CV (Capacitance-Voltage) characteristics is known. In order to measure the CV characteristics, a depletion layer is formed inside the silicon single crystal wafer by forming a Schottky junction on the surface of the silicon single crystal wafer to be a sample and applying a reverse bias voltage continuously. To expand the capacity and change the capacity. For example, a mercury electrode is used to form a Schottky junction on the surface of the silicon single crystal wafer.

試料となるシリコン単結晶ウェーハがn型の場合、予めウェーハの表面を酸化して薄い酸化珪素膜を形成させ、この酸化珪素膜上に水銀電極を接合することにより、C−V特性を測定することができる。   When the sample silicon single crystal wafer is n-type, the surface of the wafer is oxidized in advance to form a thin silicon oxide film, and a mercury electrode is bonded onto the silicon oxide film to measure CV characteristics. be able to.

シリコン単結晶ウェーハ表面への薄い酸化珪素膜の形成は、過酸化水素などの酸化剤を含有する溶液にウェーハを数分間浸漬させた後に、リンスと乾燥を行う方法が知られている(非特許文献1)。しかし、この方法では酸化処理から乾燥までに約20分間かかるので、時間の短縮が必要である。   A thin silicon oxide film is formed on the surface of a silicon single crystal wafer by rinsing and drying after immersing the wafer in a solution containing an oxidizing agent such as hydrogen peroxide for several minutes (non-patented). Reference 1). However, in this method, since it takes about 20 minutes from the oxidation treatment to drying, it is necessary to shorten the time.

また、シリコン単結晶ウェーハ表面に5nm以上の比較的厚い酸化珪素膜を形成しても、C−V特性を測定することができる(特許文献1)。しかし、特許文献1記載の方法では、シリカガラスを酸化珪素に転化させるために1時間程度の熱処理を行う必要があり、作業効率が悪い。   Further, the CV characteristics can be measured even when a relatively thick silicon oxide film of 5 nm or more is formed on the surface of the silicon single crystal wafer (Patent Document 1). However, in the method described in Patent Document 1, it is necessary to perform heat treatment for about 1 hour in order to convert the silica glass into silicon oxide, and the working efficiency is poor.

そこで、n型シリコン単結晶ウェーハを酸素含有雰囲気中で紫外光に曝すことにより、ウェーハの表面をオゾンで酸化する方法が提案されている(特許文献2、3)。   Thus, a method has been proposed in which an n-type silicon single crystal wafer is exposed to ultraviolet light in an oxygen-containing atmosphere to oxidize the wafer surface with ozone (Patent Documents 2 and 3).

また、シリコン単結晶ウェーハがp型の場合、該ウェーハを濃HF溶液あるいは希HF溶液で処理し、脱イオン水で洗浄、窒素雰囲気中で遠心乾燥してウェーハの表面を調製することが特許文献2に記載されている。   When the silicon single crystal wafer is p-type, the wafer surface is prepared by treating the wafer with concentrated HF solution or diluted HF solution, washing with deionized water, and centrifugal drying in a nitrogen atmosphere. 2.

ASTM Standards F1392−02ASTM Standards F1392-02

特開2012−138463号公報JP 2012-138463 A 特表2002−516486号公報Special table 2002-516486 gazette 特開2013−46030号公報JP 2013-46030 A

しかし、低抵抗率のn型シリコン単結晶ウェーハのC−V特性を測定すると、その測定精度が悪くなる傾向がある。   However, when the CV characteristic of a low resistivity n-type silicon single crystal wafer is measured, the measurement accuracy tends to deteriorate.

本発明は、上記問題点に鑑みてなされたものであって、従来よりも改善されたC−V特性の測定精度を得ることのできるシリコン単結晶ウェーハの評価方法を提供することを目的とする。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for evaluating a silicon single crystal wafer that can obtain measurement accuracy of CV characteristics that is improved as compared with the prior art. .

上記目的を達成するために、本発明は、フッ酸でn型シリコン単結晶ウェーハを処理して、自然酸化膜を除去する自然酸化膜除去工程と、自然酸化膜を除去した前記n型シリコン単結晶ウェーハの表面に酸化膜を形成する酸化膜形成工程と、前記酸化膜を形成した前記n型シリコン単結晶ウェーハの表面に水銀電極を接合してC−V特性を測定するC−V特性測定工程とを有することを特徴とするシリコン単結晶ウェーハの評価方法を提供する。   In order to achieve the above object, the present invention provides a natural oxide film removing step of removing a natural oxide film by treating an n-type silicon single crystal wafer with hydrofluoric acid, and the n-type silicon single crystal from which the natural oxide film has been removed. An oxide film forming step for forming an oxide film on the surface of the crystal wafer, and a CV characteristic measurement for measuring a CV characteristic by bonding a mercury electrode to the surface of the n-type silicon single crystal wafer on which the oxide film is formed. And a method for evaluating a silicon single crystal wafer.

このように、n型シリコン単結晶ウェーハのC−V特性に影響を及ぼす自然酸化膜を予め除去するので、従来よりも真の値に近いC−V特性を得ることができ、また、日々徐々に厚くなる自然酸化膜の影響が無くなるので、抵抗率の日間変動を小さくすることができる。   In this way, since the natural oxide film that affects the CV characteristics of the n-type silicon single crystal wafer is removed in advance, it is possible to obtain CV characteristics that are closer to the true value than before, and gradually gradually from day to day. Therefore, the influence of the natural oxide film that becomes thicker is eliminated, so that the daily fluctuation of resistivity can be reduced.

ここで、前記n型シリコン単結晶ウェーハの抵抗率が0.04Ωcm以上、1Ωcm以下であることが望ましい。
自然酸化膜の影響は抵抗率が低くなるに従い大きくなるので、このように、n型シリコン単結晶ウェーハの抵抗率が0.04Ωcm以上、1Ωcm以下の場合に、効果的に抵抗率の測定精度を上げることができる。
Here, it is desirable that the resistivity of the n-type silicon single crystal wafer is 0.04 Ωcm or more and 1 Ωcm or less.
Since the influence of the natural oxide film increases as the resistivity decreases, the resistivity measurement accuracy is effectively improved when the resistivity of the n-type silicon single crystal wafer is 0.04 Ωcm or more and 1 Ωcm or less. Can be raised.

また、前記n型シリコン単結晶ウェーハの抵抗率が0.2Ωcm以下であることがより望ましい。
このように、n型シリコン単結晶ウェーハの抵抗率が0.2Ωcm以下の場合に、より効果的に抵抗率の測定精度を上げることができる。
The resistivity of the n-type silicon single crystal wafer is more preferably 0.2 Ωcm or less.
Thus, when the resistivity of the n-type silicon single crystal wafer is 0.2 Ωcm or less, the measurement accuracy of the resistivity can be increased more effectively.

さらに、前記酸化膜形成工程では、紫外線の光源とシリコン単結晶ウェーハの載置部との間に、オゾンガスを通過させるが、光を遮光する遮光板を配置し、紫外線を遮光しつつオゾンガスで前記n型シリコン単結晶ウェーハの表面に酸化珪素膜を形成し、前記C−V特性測定工程では、前記酸化珪素膜上に水銀電極を接合してC−V特性を測定することが望ましい。
このように、紫外線の光源とシリコン単結晶ウェーハの載置部との間に、オゾンガスを通過させるが、光を遮光する遮光板を配置し、紫外線を遮光しつつオゾンガスでn型シリコン単結晶ウェーハの表面に酸化珪素膜を形成することで、作業時間を短縮しつつ、安定してC−V特性を測定することができる。
Further, in the oxide film forming step, ozone gas is allowed to pass between the ultraviolet light source and the silicon single crystal wafer mounting portion. It is desirable to form a silicon oxide film on the surface of the n-type silicon single crystal wafer, and measure a CV characteristic by bonding a mercury electrode on the silicon oxide film in the CV characteristic measurement step.
In this way, an ozone gas is allowed to pass between the ultraviolet light source and the silicon single crystal wafer mounting portion, but a light-shielding plate that shields light is arranged, and the n-type silicon single crystal wafer is irradiated with ozone gas while shielding the ultraviolet light. By forming the silicon oxide film on the surface, the CV characteristics can be stably measured while shortening the working time.

以上のように、本発明によれば、n型シリコン単結晶ウェーハのC−V特性に影響を及ぼす自然酸化膜を予め除去するので、従来よりも真の値に近いC−V特性を得ることができ、また、日々徐々に厚くなる自然酸化膜の影響が無くなるので、抵抗率の日間変動を小さくすることができる。   As described above, according to the present invention, since the natural oxide film that affects the CV characteristics of the n-type silicon single crystal wafer is removed in advance, a CV characteristic closer to the true value than before can be obtained. In addition, since the influence of the natural oxide film that gradually increases day by day is eliminated, daily fluctuations in resistivity can be reduced.

本発明のシリコン単結晶ウェーハの評価方法の一例を示す概略工程図である。It is a schematic process drawing which shows an example of the evaluation method of the silicon single crystal wafer of this invention. 自然酸化膜除去工程の一例を示す概略図である。It is the schematic which shows an example of a natural oxide film removal process. オゾンガス発生装置の一例を示す概略図である。It is the schematic which shows an example of an ozone gas generator. n型シリコン単結晶ウェーハの主表面に帯電していた静電気が除去される様子を示す概念図である。It is a conceptual diagram which shows a mode that the static electricity electrically charged by the main surface of the n-type silicon single crystal wafer is removed. 静電気除去装置の一例を示す概略図である。It is the schematic which shows an example of an electrostatic removal apparatus. 逆バイアス電圧を印加する際に直列に形成される容量を示す概念図である。It is a conceptual diagram which shows the capacity | capacitance formed in series when a reverse bias voltage is applied. 逆バイアス電圧を印加する際に直列に形成される容量を示す概略説明図である。It is a schematic explanatory drawing which shows the capacity | capacitance formed in series when a reverse bias voltage is applied. 真の容量との差が抵抗率の小さいほど大きくなることを示すグラフである。It is a graph which shows that a difference with a true capacity | capacitance becomes large, so that resistivity is small. 実施例の抵抗率変化を示すグラフである。It is a graph which shows the resistivity change of an Example. 比較例の抵抗率変化を示すグラフである。It is a graph which shows the resistivity change of a comparative example.

以下、本発明について、実施態様の一例として、図を参照しながら詳細に説明するが、本発明はこれに限定されるものではない。
図1は、本発明のシリコン単結晶ウェーハの評価方法の一例を示す概略工程図である。
まず、n型シリコン単結晶ウェーハ、例えばn型シリコンエピタキシャルウェーハを準備する(図1(a))。
次に、n型シリコン単結晶ウェーハをフッ酸で処理し、該ウェーハの表面に形成されている自然酸化膜を除去する(図1(b)自然酸化膜除去工程)。
続いて、n型シリコン単結晶ウェーハの表面に薄い酸化珪素膜を形成する(図1(c)酸化珪素膜形成工程)。
最後に、n型シリコン単結晶ウェーハの所望位置のC−V特性を測定する(図1(d)C−V特性測定工程)。
Hereinafter, the present invention will be described in detail as an example of an embodiment with reference to the drawings, but the present invention is not limited thereto.
FIG. 1 is a schematic process diagram showing an example of a silicon single crystal wafer evaluation method of the present invention.
First, an n-type silicon single crystal wafer, for example, an n-type silicon epitaxial wafer is prepared (FIG. 1A).
Next, the n-type silicon single crystal wafer is treated with hydrofluoric acid to remove the natural oxide film formed on the surface of the wafer (FIG. 1 (b) natural oxide film removing step).
Subsequently, a thin silicon oxide film is formed on the surface of the n-type silicon single crystal wafer (FIG. 1 (c) silicon oxide film forming step).
Finally, the CV characteristic at the desired position of the n-type silicon single crystal wafer is measured (FIG. 1 (d) CV characteristic measurement step).

以下に、本発明のシリコン単結晶ウェーハの評価方法の各工程についてさらに詳しく説明する。
図2は、自然酸化膜除去工程の一例を示す概略図である。
まず、n型シリコン単結晶ウェーハ12をフッ酸41に浸漬し、表面に形成された自然酸化膜42をエッチング除去する(図2(a))。フッ酸41の濃度は例えば25〜50重量%である。
Below, it demonstrates in more detail about each process of the evaluation method of the silicon single crystal wafer of this invention.
FIG. 2 is a schematic view showing an example of the natural oxide film removing step.
First, the n-type silicon single crystal wafer 12 is immersed in hydrofluoric acid 41, and the natural oxide film 42 formed on the surface is removed by etching (FIG. 2A). The concentration of hydrofluoric acid 41 is, for example, 25 to 50% by weight.

次に、n型シリコン単結晶ウェーハ12を脱イオン水43でリンスし、フッ酸41を十分に除去する(図2(b))。脱イオン水43によるリンスは、2槽ないし3槽のリンス槽に分けて連続的に行うと効率的にフッ酸を除去できる。   Next, the n-type silicon single crystal wafer 12 is rinsed with deionized water 43 to sufficiently remove the hydrofluoric acid 41 (FIG. 2B). When rinsing with deionized water 43 is performed continuously in two or three rinsing tanks, hydrofluoric acid can be efficiently removed.

そして、脱イオン水43中から取り出したn型シリコン単結晶ウェーハ12を乾燥し、表面の水分を除去する(図2(c))。乾燥方法は、スピンドライ、圧縮空気または圧縮窒素の噴き付け等の方法がある。   Then, the n-type silicon single crystal wafer 12 taken out from the deionized water 43 is dried to remove moisture on the surface (FIG. 2 (c)). Examples of the drying method include spin drying, spraying compressed air or compressed nitrogen.

続いて、自然酸化膜を除去したn型シリコン単結晶ウェーハ12の主表面に、例えば図3のオゾンガス発生装置10を用いて薄い酸化珪素膜15を形成する。オゾンガス発生装置10は、紫外線の光源である水銀ランプ11と、シリコン単結晶ウェーハ12の載置部13とを有し、水銀ランプ11と載置部13との間に、遮光板14が配置されている。   Subsequently, a thin silicon oxide film 15 is formed on the main surface of the n-type silicon single crystal wafer 12 from which the natural oxide film has been removed using, for example, the ozone gas generator 10 shown in FIG. The ozone gas generator 10 includes a mercury lamp 11 that is an ultraviolet light source and a mounting portion 13 for a silicon single crystal wafer 12, and a light shielding plate 14 is disposed between the mercury lamp 11 and the mounting portion 13. ing.

水銀ランプ11から照射される紫外線には、184.95nmの波長が含まれる。空気中で紫外線を照射すると、酸素分子は184.95nmの波長の光により分解し、オゾンガスと原子状酸素を生じる。   The ultraviolet ray irradiated from the mercury lamp 11 includes a wavelength of 184.95 nm. When ultraviolet rays are irradiated in the air, oxygen molecules are decomposed by light having a wavelength of 184.95 nm to generate ozone gas and atomic oxygen.

遮光板14は複数枚のパンチングメタルを重ね合わせてなり、上下パンチングメタルの孔の位置がずらされている。オゾンガスと原子状酸素はパンチングメタル間の隙間と孔を通過してシリコン単結晶ウェーハ12まで到達するが、紫外線は殆ど遮光される。遮光率は95%以上、より望ましくは99%以上100%未満であることが望ましい。遮光率が95%以上であれば、C−V特性にノイズが発生することを抑制できる。また、遮光率が100%未満であれば、オゾンガスが通過できなくなり、シリコン単結晶ウェーハ12の主表面に酸化珪素膜が形成されないという現象を抑制できる。   The light shielding plate 14 is formed by overlapping a plurality of punching metals, and the positions of the holes of the upper and lower punching metals are shifted. Although ozone gas and atomic oxygen pass through the gaps and holes between the punching metals and reach the silicon single crystal wafer 12, the ultraviolet rays are almost shielded. The light shielding rate is 95% or more, more desirably 99% or more and less than 100%. If the light shielding rate is 95% or more, it is possible to suppress the occurrence of noise in the CV characteristics. Further, if the light shielding rate is less than 100%, ozone gas cannot pass through, and the phenomenon that the silicon oxide film is not formed on the main surface of the silicon single crystal wafer 12 can be suppressed.

空気中で水銀ランプ11から紫外線を所定時間照射すると、厚さ約0.3nmの酸化珪素膜15がn型シリコン単結晶ウェーハ12の主表面に形成される。   When ultraviolet rays are irradiated from the mercury lamp 11 for a predetermined time in the air, a silicon oxide film 15 having a thickness of about 0.3 nm is formed on the main surface of the n-type silicon single crystal wafer 12.

オゾンガス発生装置10を用いてシリコン単結晶ウェーハ12の主表面に酸化珪素膜15を形成すると、図4(a)に示すように、シリコン単結晶ウェーハ12の主表面にマイナスの静電気が帯電する。シリコン単結晶ウェーハ12がn型の場合、マイナスの静電気とn型キャリアが反発し合い、主表面近傍に空乏層32が形成される。空乏層32の幅は、静電気が時間の経過とともに放電され、だんだん狭くなる。   When the silicon oxide film 15 is formed on the main surface of the silicon single crystal wafer 12 using the ozone gas generator 10, negative static electricity is charged on the main surface of the silicon single crystal wafer 12 as shown in FIG. When silicon single crystal wafer 12 is n-type, negative static electricity and n-type carriers repel each other, and depletion layer 32 is formed near the main surface. The width of the depletion layer 32 becomes narrower as static electricity is discharged over time.

マイナスの静電気に起因する空乏層32が形成された状態でC−V特性を測定すると、静電気の放電とともに空乏層32の幅が狭くなるので、C−V特性を安定して測定することができない。   When the CV characteristic is measured in a state where the depletion layer 32 caused by negative static electricity is formed, the width of the depletion layer 32 becomes narrower along with the discharge of static electricity, so the CV characteristic cannot be measured stably. .

そこで、オゾンガス発生装置10を用いてn型シリコン単結晶ウェーハ12の主表面に酸化珪素膜15を形成した後に、除電を行う(図4(b))。すると、シリコン単結晶ウェーハ12の主表面に帯電していた静電気が除去されるので、空乏層32も同時に消滅し、静電気の放電に起因する抵抗率の経時的な低下が改善される。   Therefore, after the silicon oxide film 15 is formed on the main surface of the n-type silicon single crystal wafer 12 using the ozone gas generator 10, static elimination is performed (FIG. 4B). Then, since the static electricity charged on the main surface of the silicon single crystal wafer 12 is removed, the depletion layer 32 disappears at the same time, and the decrease in resistivity with time due to the discharge of static electricity is improved.

除電を行う静電気除去装置20は例えば図5に示すように、+イオンを発生させる電極針21と、−イオンを発生させる電極針22と、電極針21、22に直流電圧を印加する電源23、24と、接地電極25とを有し、電極針21と電極針22に高電圧を印加することでコロナ放電を発生させる。   For example, as shown in FIG. 5, the static eliminator 20 that performs static elimination includes an electrode needle 21 that generates + ions, an electrode needle 22 that generates − ions, a power source 23 that applies a DC voltage to the electrode needles 21 and 22, 24 and a ground electrode 25, and a corona discharge is generated by applying a high voltage to the electrode needle 21 and the electrode needle 22.

コロナ放電が発生すると、電極針21、22周辺に存在している空気が電気的に分解されてイオンが発生し、このイオンで反対極性の静電気を電気的に中和することでシリコン単結晶ウェーハ12の除電を行う。   When the corona discharge occurs, the air existing around the electrode needles 21 and 22 is electrically decomposed to generate ions, and the silicon single crystal wafer is electrically neutralized with the static electricity having the opposite polarity by the ions. 12 is removed.

除電を施したn型シリコン単結晶ウェーハ12の酸化珪素膜15上に水銀電極31を接合し、逆バイアス電圧を連続的に変化させながら印加すると、逆バイアス電圧に応じてn型シリコン単結晶ウェーハ12内に形成された空乏層33が拡がり、容量として計測される。この逆バイアス電圧と容量の関係をグラフにプロットすると、C−V特性を得ることができる。   When a mercury electrode 31 is bonded onto the silicon oxide film 15 of the n-type silicon single crystal wafer 12 subjected to static elimination and applied while changing the reverse bias voltage continuously, the n-type silicon single crystal wafer is applied according to the reverse bias voltage. The depletion layer 33 formed in 12 spreads and is measured as a capacitance. When the relationship between the reverse bias voltage and the capacitance is plotted on a graph, CV characteristics can be obtained.

このとき、図6(a)、図7(a)に示すように、自然酸化膜42を除去せずに該自然酸化膜42上に酸化珪素膜15を形成すると、逆バイアス電圧を印加する際に、酸化珪素膜15に起因する容量C15、自然酸化膜42に起因する容量C42、逆バイアス電圧に応じてn型シリコン単結晶ウェーハ12内に形成された空乏層33に起因する容量C33が直列に形成される。   At this time, as shown in FIGS. 6A and 7A, when the silicon oxide film 15 is formed on the natural oxide film 42 without removing the natural oxide film 42, a reverse bias voltage is applied. In addition, a capacitance C15 caused by the silicon oxide film 15, a capacitance C42 caused by the natural oxide film 42, and a capacitance C33 caused by the depletion layer 33 formed in the n-type silicon single crystal wafer 12 according to the reverse bias voltage are connected in series. Formed.

面積A、厚さdのコンデンサの容量Cは、(1)式で表される。

C=A*εSiO2/d ・・・(1)
ここで、εは真空誘電率8.85×10−12F/m、εSiO2は酸化珪素の比誘電率3.84である。面積Aは水銀電極31の面積であり、例えば2mmである。
The capacitance C of the capacitor having the area A and the thickness d is expressed by equation (1).

C = A * ε 0 * ε SiO 2 / d (1)
Here, ε 0 is a vacuum dielectric constant of 8.85 × 10 −12 F / m, and ε SiO 2 is a relative dielectric constant of silicon oxide of 3.84. The area A is the area of the mercury electrode 31 and is 2 mm 2 , for example.

オゾンガス発生装置10により形成される酸化珪素膜15の厚さdが例えば0.3nmの場合、その容量C15は、

C15=2*10−6*8.85×10−12*3.84/0.3*10−9
=227×10−9F ・・・(2)
である。
When the thickness d of the silicon oxide film 15 formed by the ozone gas generator 10 is, for example, 0.3 nm, the capacitance C15 is

C15 = 2 * 10 −6 * 8.85 × 10 −12 * 3.84 / 0.3 * 10 −9
= 227 × 10 −9 F (2)
It is.

また、一般的な自然酸化膜の厚さdは1nmであり、その容量C42は、

C42=2*10−6*8.85×10−12*3.84/1*10−9
=68×10−9F ・・・(3)
である。
Moreover, the thickness d of a general natural oxide film is 1 nm, and its capacity C42 is

C42 = 2 * 10 −6 * 8.85 × 10 −12 * 3.84 / 1 * 10 −9
= 68 × 10 −9 F (3)
It is.

n型シリコン単結晶ウェーハ12に逆バイアス電圧を印加したときに形成される容量C33は、例えば抵抗率が0.05Ωcmの場合、1.6×10−9Fである。 The capacitance C33 formed when a reverse bias voltage is applied to the n-type silicon single crystal wafer 12 is 1.6 × 10 −9 F when the resistivity is 0.05 Ωcm, for example.

容量C15、容量C42、容量C33は直列に形成されるので、全体の容量をCとすると、

1/C=1/C15+1/C42+1/C33
=1/227×10−9+1/68×10−9+1/1.6×10−9
=0.644×10 ・・・(4)
∴C =1.55×10−9
である。このとき、真の容量C33と測定される容量Cの差C33−Cは、

(C33−C)/C33×100=(1.6−1.55)/1.6×100
=3.1% ・・・(5)
である。
Since the capacitor C15, the capacitor C42, and the capacitor C33 are formed in series, if the entire capacity is C,

1 / C = 1 / C15 + 1 / C42 + 1 / C33
= 1/227 × 10 −9 + 1/68 × 10 −9 + 1 / 1.6 × 10 −9
= 0.644 × 10 9 (4)
∴C = 1.55 × 10 −9 F
It is. At this time, the difference C33-C between the true capacitance C33 and the measured capacitance C is:

(C33-C) / C33 × 100 = (1.6−1.55) /1.6×100
= 3.1% (5)
It is.

これに対し、図6(b)、7(b)に示すように、自然酸化膜42を例えばフッ酸で予めエッチング除去すると、容量C15と容量C33が直列に形成され、その全体の容量は、

1/C=1/C15+1/C33
=1/227×10−9+1/1.6×10−9
=0.629×10 ・・・(6)
∴C =1.59×10−9
である。このとき、真の容量C33と測定される容量Cの差C33−Cは、

(C33−C)/C33×100=(1.6−1.59)/1.6×100
=0.6% ・・・(7)
であり、自然酸化膜42を予め除去することにより、真の容量C33との差が大幅に低減できる。
On the other hand, as shown in FIGS. 6B and 7B, when the natural oxide film 42 is removed by etching with, for example, hydrofluoric acid in advance, a capacitor C15 and a capacitor C33 are formed in series, and the overall capacitance is

1 / C = 1 / C15 + 1 / C33
= 1/227 × 10 −9 + 1 / 1.6 × 10 −9
= 0.629 × 10 9 (6)
∴C = 1.59 × 10 −9 F
It is. At this time, the difference C33-C between the true capacitance C33 and the measured capacitance C is:

(C33-C) / C33 × 100 = (1.6−1.59) /1.6×100
= 0.6% (7)
Thus, by removing the natural oxide film 42 in advance, the difference from the true capacitance C33 can be greatly reduced.

同様にして、n型抵抗率0.04Ωcm以上37Ωcm以下の範囲について、真の容量C33と測定される容量Cの差C33−Cを求めると、図8に示すように、抵抗率が1Ωcm以下の領域で真の容量との差が顕著に大きくなることがわかる。したがって、C−V特性を測定するn型シリコン単結晶ウェーハ12の抵抗率が1Ωcm以下の場合、より望ましくは0.2Ωcm以下の場合、自然酸化膜42を予め除去した後に、酸化珪素膜15を形成することが望ましい。なお、抵抗率が0.04Ωcm未満になると、逆バイアス電圧を印加しても空乏層33が殆ど拡がらないため、安定したC−V特性を得ることが難しい。   Similarly, when the difference C33-C between the true capacitance C33 and the measured capacitance C is determined in the n-type resistivity range of 0.04 Ωcm to 37 Ωcm, the resistivity is 1 Ωcm or less as shown in FIG. It can be seen that the difference from the true capacity is remarkably increased in the region. Therefore, when the resistivity of the n-type silicon single crystal wafer 12 for measuring CV characteristics is 1 Ωcm or less, more desirably 0.2 Ωcm or less, the natural oxide film 42 is removed in advance, and then the silicon oxide film 15 is removed. It is desirable to form. When the resistivity is less than 0.04 Ωcm, it is difficult to obtain stable CV characteristics because the depletion layer 33 hardly expands even when a reverse bias voltage is applied.

自然酸化膜42を予め除去すると、真の容量C33と測定される容量Cの差C33−Cが大幅に小さくなるので、従来よりも真の値に近いC−V特性を得ることができる。
測定により得られた逆バイアス電圧値とキャパシタンス値を例えば(8)式と(9)式に代入すると、n型エピタキシャル層の深さWならびに、深さWにおけるドーパント濃度N(W)を算出することができるので、エピタキシャル層中の深さ方向におけるドーパント濃度のプロファイルを得ることができる。

W=AεSi/C ・・・(8)

N(W)=2/(qεSi)*{d(C−2)/dV}−1 ・・・(9)
ここで、Wはエピタキシャル層内の深さに相当する空乏層幅、Aは水銀電極の面積(水銀がエピタキシャル層の表面に接合するときの接触面積)、εSiはシリコンの誘電率、Cはキャパシンタンス容量、N(W)はエピタキシャル層内の深さWにおけるドーパント濃度、qは電子の電荷量、Vは印加電圧である。
When the natural oxide film 42 is removed in advance, the difference C33-C between the true capacitance C33 and the measured capacitance C is significantly reduced, so that a CV characteristic closer to the true value than before can be obtained.
When the reverse bias voltage value and the capacitance value obtained by the measurement are substituted into, for example, the expressions (8) and (9), the depth W of the n-type epitaxial layer and the dopant concentration N (W) at the depth W are calculated. Therefore, a dopant concentration profile in the depth direction in the epitaxial layer can be obtained.

W = Aε Si / C (8)

N (W) = 2 / ( qε Si A 2) * {d (C -2) / dV} -1 ··· (9)
Where W is the width of the depletion layer corresponding to the depth in the epitaxial layer, A is the area of the mercury electrode (contact area when mercury is bonded to the surface of the epitaxial layer), ε Si is the dielectric constant of silicon, and C is Capacitance capacitance, N (W) is a dopant concentration at a depth W in the epitaxial layer, q is an electron charge amount, and V is an applied voltage.

エピタキシャル層中の深さ方向におけるドーパント濃度のプロファイルの中で、測定深さを指定すると、その深さにおけるドーパント濃度を測定することができる。また、得られたドーパント濃度をASTM STANDARDS F723等の換算式により換算することにより、ドーパント濃度を抵抗率に換算することができる。   If the measurement depth is specified in the profile of the dopant concentration in the depth direction in the epitaxial layer, the dopant concentration at that depth can be measured. Further, the dopant concentration can be converted into resistivity by converting the obtained dopant concentration by a conversion formula such as ASTM STANDARDDS F723.

このようにして得られるドーパント濃度もしくは抵抗率を、n型シリコン単結晶ウェーハ12の同一箇所で日々測定すると、徐々に厚くなる自然酸化膜の影響が無くなるので、抵抗率の日間変動が小さくなる。   When the dopant concentration or resistivity obtained in this way is measured every day at the same location on the n-type silicon single crystal wafer 12, the influence of the gradually increasing natural oxide film is eliminated, so that the daily fluctuation of the resistivity is reduced.

以下、実施例及び比較例を示して本発明をより具体的に説明するが、本発明はこれらに限定されるものではない。   EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.

(実施例)
抵抗率0.17Ω・cmのn型シリコンエピタキシャル層を有するシリコンエピタキシャルウェーハ12を準備し、25重量%のフッ酸で処理し、自然酸化膜をエッチング除去した。脱イオン水で十分にリンスし、乾燥させた後に、遮光板14を用いたオゾンガス発生装置10でシリコンエピタキシャルウェーハ12の主表面に厚さ約0.3nmの酸化珪素膜15を形成した。
(Example)
A silicon epitaxial wafer 12 having an n-type silicon epitaxial layer having a resistivity of 0.17 Ω · cm was prepared, treated with 25 wt% hydrofluoric acid, and the natural oxide film was removed by etching. After sufficiently rinsing with deionized water and drying, a silicon oxide film 15 having a thickness of about 0.3 nm was formed on the main surface of the silicon epitaxial wafer 12 by the ozone gas generator 10 using the light shielding plate 14.

続いて、静電気除去装置20でシリコンエピタキシャルウェーハ12の主表面に帯電している静電気を除去した後に、水銀電極を接合してシリコンエピタキシャルウェーハ12の中心部のC−V特性を測定し、抵抗率に換算する。この手順で測定を7日間行い、その結果を図9に示した。初日から最終日までの間、抵抗率は安定しており、その間に上昇した抵抗率は1.8%であった。   Subsequently, after the static electricity charged on the main surface of the silicon epitaxial wafer 12 is removed by the static eliminator 20, the mercury electrode is joined and the CV characteristic at the center of the silicon epitaxial wafer 12 is measured to determine the resistivity. Convert to. Measurement was carried out for 7 days by this procedure, and the results are shown in FIG. The resistivity was stable from the first day to the last day, and the resistivity increased during that period was 1.8%.

(比較例)
抵抗率0.17Ω・cmのn型シリコンエピタキシャル層を有するシリコンエピタキシャルウェーハ12を準備し、自然酸化膜をエッチング除去せずに、遮光板14を用いたオゾンガス発生装置10でシリコンエピタキシャルウェーハ12の主表面に厚さ約0.3nmの酸化珪素膜15を形成した。
(Comparative example)
A silicon epitaxial wafer 12 having an n-type silicon epitaxial layer having a resistivity of 0.17 Ω · cm is prepared, and the main surface of the silicon epitaxial wafer 12 is obtained by the ozone gas generator 10 using the light shielding plate 14 without removing the natural oxide film by etching. A silicon oxide film 15 having a thickness of about 0.3 nm was formed on the surface.

続いて、静電気除去装置20でシリコンエピタキシャルウェーハ12の主表面に帯電している静電気を除去した後に、水銀電極を接合してシリコンエピタキシャルウェーハ12の中心部のC−V特性を測定し、抵抗率に換算した。2日目以降は、自然酸化膜除去、酸化珪素膜15の追加形成を行わないで静電気除去した後にC−V特性の測定を行った。その結果、図10に示すように、初日から最終日までの間に抵抗率はしだいに上昇し、期間内に9.4%上昇した。   Subsequently, after the static electricity charged on the main surface of the silicon epitaxial wafer 12 is removed by the static eliminator 20, the mercury electrode is joined and the CV characteristic at the center of the silicon epitaxial wafer 12 is measured to determine the resistivity. Converted into On and after the second day, the CV characteristics were measured after removing static electricity without removing the natural oxide film and additionally forming the silicon oxide film 15. As a result, as shown in FIG. 10, the resistivity gradually increased from the first day to the last day, and increased by 9.4% within the period.

本発明のシリコン単結晶ウェーハの評価方法によると、n型シリコン単結晶ウェーハのC−V特性に影響を及ぼす自然酸化膜を予め除去するので、従来よりも真の値に近いC−V特性を得ることができる。また、日々徐々に厚くなる自然酸化膜の影響が無くなるので、抵抗率の日間変動が小さくなる。   According to the silicon single crystal wafer evaluation method of the present invention, the natural oxide film that affects the CV characteristics of the n-type silicon single crystal wafer is removed in advance, so that the CV characteristics closer to the true value than before are obtained. Can be obtained. Further, since the influence of the natural oxide film that gradually increases day by day is eliminated, the daily fluctuation of resistivity is reduced.

なお、本発明は、上記実施形態に限定されるものではない。上記実施形態は、例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。   The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

10…オゾンガス発生装置、 11…水銀ランプ、
12…n型シリコン単結晶ウェーハ、 13…載置部、 14…遮光板、
15…酸化珪素膜、 20…静電気除去装置、 21、22…電極針、
23、24…電源、 25…接地電極、 31…水銀電極、
32…空乏層(静電気により形成される空乏層)、
33…空乏層(逆バイアスにより形成される空乏層)、 41…フッ酸、
42…自然酸化膜、 43…脱イオン水。


10 ... ozone gas generator, 11 ... mercury lamp,
12 ... n-type silicon single crystal wafer, 13 ... mounting part, 14 ... light shielding plate,
15 ... Silicon oxide film, 20 ... Static eliminator, 21, 22 ... Electrode needle,
23, 24 ... power source, 25 ... ground electrode, 31 ... mercury electrode,
32 ... depletion layer (depletion layer formed by static electricity),
33 ... depletion layer (depletion layer formed by reverse bias), 41 ... hydrofluoric acid,
42 ... Natural oxide film, 43 ... Deionized water.


Claims (4)

フッ酸でn型シリコン単結晶ウェーハを処理して、自然酸化膜を除去する自然酸化膜除去工程と、
自然酸化膜を除去した前記n型シリコン単結晶ウェーハの表面に酸化膜を形成する酸化膜形成工程と、
前記酸化膜を形成した前記n型シリコン単結晶ウェーハに除電を施して、前記n型シリコン単結晶ウェーハの主表面に帯電していた静電気を除去する工程と、
前記酸化膜を形成し、除電を施した前記n型シリコン単結晶ウェーハの表面に水銀電極を接合してC−V特性を測定するC−V特性測定工程と
を有することを特徴とするシリコン単結晶ウェーハの評価方法。
A natural oxide film removing step of treating the n-type silicon single crystal wafer with hydrofluoric acid to remove the natural oxide film;
An oxide film forming step of forming an oxide film on the surface of the n-type silicon single crystal wafer from which the natural oxide film has been removed;
Removing the static electricity charged on the main surface of the n-type silicon single crystal wafer by neutralizing the n-type silicon single crystal wafer on which the oxide film is formed;
And a CV characteristic measuring step of measuring a CV characteristic by bonding a mercury electrode to the surface of the n-type silicon single crystal wafer on which the oxide film has been formed and subjected to static elimination. Crystal wafer evaluation method.
前記n型シリコン単結晶ウェーハの抵抗率が0.04Ωcm以上、1Ωcm以下であることを特徴とする請求項1に記載のシリコン単結晶ウェーハの評価方法。   2. The method for evaluating a silicon single crystal wafer according to claim 1, wherein the resistivity of the n-type silicon single crystal wafer is 0.04 Ωcm or more and 1 Ωcm or less. 前記n型シリコン単結晶ウェーハの抵抗率が0.2Ωcm以下であることを特徴とする請求項2に記載のシリコン単結晶ウェーハの評価方法。   The method for evaluating a silicon single crystal wafer according to claim 2, wherein the resistivity of the n-type silicon single crystal wafer is 0.2 Ωcm or less. 前記酸化膜形成工程では、紫外線の光源とシリコン単結晶ウェーハの載置部との間に、オゾンガスを通過させるが、光を遮光する遮光板を配置し、紫外線を遮光しつつオゾンガスで前記n型シリコン単結晶ウェーハの表面に酸化珪素膜を形成し、
前記C−V特性測定工程では、前記酸化珪素膜上に水銀電極を接合してC−V特性を測定することを特徴とする請求項1ないし請求項3のいずれか1項に記載のシリコン単結晶ウェーハの評価方法。


In the oxide film forming step, ozone gas is allowed to pass between the ultraviolet light source and the silicon single crystal wafer mounting portion, but a light-shielding plate that shields light is disposed, and the n-type is formed using ozone gas while shielding ultraviolet light. A silicon oxide film is formed on the surface of a silicon single crystal wafer,
4. The silicon single unit according to claim 1, wherein in the CV characteristic measurement step, a CV characteristic is measured by bonding a mercury electrode on the silicon oxide film. 5. Crystal wafer evaluation method.


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