JP6024897B2 - Low voltage cache memory - Google Patents

Description

  The present invention relates to a technique relating to a low voltage operation cache memory.

SRAM (Static Random) in recent years
In semiconductor memories such as Access Memory), CMOS process technology mounted on SoC advances, processing dimensions (scaling size) of integrated circuits are reduced, higher chip density and lower chip cost are realized, and memory capacity is increased. doing.
Such reduction of the scaling size increases the variation in threshold voltage of the transistors constituting the memory cell such as SRAM, reduces the noise margin for reading and writing in the memory cell, destabilizes the memory cell operation, and causes bit errors. The rate is increasing.

  Such an increase in process variation greatly affects the reliability of the microprocessor, making it difficult to achieve low voltage operation. Device mismatching between transistors in the SRAM due to process variations decreases the operation margin of the memory cell, and as a result, causes cell failure (read failure, write failure, access time violation). Further, as the miniaturization progresses, the minimum operating voltage tends to increase, and the operating margin of the memory cell is reduced. Since the SRAM occupies most of the number of transistors in the processor, it can be said that the operating voltage of the entire processor is determined by a cache memory including a large SRAM block. Therefore, in order to increase the operating margin of the memory cell and reduce the operating voltage of the processor, it is essential to reduce the voltage of the cache memory.

Many studies on low-voltage operation cache memories have been introduced so far (see, for example, Non-Patent Documents 1 and 2). However, in the low-voltage operation cache memory proposed in Non-Patent Document 1, an on-chip is used to specify the location of the failed cache line.
Since the fuse is used, there is a problem that the cost is increased.
In addition, the low-voltage operation cache memory proposed in Non-Patent Document 2 has a problem that the area overhead is large because an additional bit and an additional circuit are required.

On the other hand, DVS (Dynamic
There is a technique to reduce the operating voltage and power consumption, such as Voltage Scaling), but in the recent fine process due to the influence of the increasing process variation, SRAM ensures a sufficient operating margin in the low voltage region It is difficult to do. In particular, since the cache memory includes an enormous number of SRAM cells, the large-capacity cache memory in the processor is easily affected by manufacturing variations, and it is difficult to maintain operation reliability in a low voltage region. Thus, the cache memory is a factor that hinders the reduction of the minimum operating voltage of the entire processor.
In particular, RDF (Random
Random variations such as “Dopant Fluctuation” greatly affect the reliability of SRAM cells. As a result, the failure cells generated in the manufacturing process are randomly distributed in the cache memory. By removing the faulty cells scattered in the cache memory, it is possible to effectively reduce the minimum operating voltage of the entire cache memory.
However, since the failure cells are randomly distributed, fine-grain control that performs some control by specifying the location of the failure cell requires an additional cycle and a complicated peripheral circuit, resulting in an increase in cost.

  Normally, the cache memory is configured using a SRAM having a smaller capacity and a higher speed than a lower-level storage device. The cache memory has a structure that stores a part of the data body and a set of attribute information such as data storage addresses and flags in a fixed-capacity memory. Exists. Previously, it was connected to the outside of the chip of the processor, but in recent years, it is taken into the processor chip as the LSI integration degree increases and the required speed increases. The cache memory stores and manages data in a certain unit (for example, 32 bytes) called data as a cache line.

  When there is a data access request to the cache memory, it is necessary to instantly search (for example, one cycle) whether or not the data exists in the cache and in which line it exists. For this purpose, the search speed is increased by limiting the storage position to some extent by a part of the data storage address (the lower few bits of the cache line unit address: index). Each cache line stores the upper bit (frame address) of the cache line unit address, and corresponds to the frame address part of the search address and the cache line of the search index position stored in the cache when searching the cache memory A hit in the cache is detected by comparing the frame address. This frame address storage buffer is a tag. By providing a plurality of sets of tags, a plurality of data can be stored even with the same index. The number of tag sets (the number of ways) is called the association degree.

  A cache memory having a data storage structure composed of a plurality of tags (association degree 2 or more) is referred to as a set associative cache memory. In the case of a set associative cache memory, a plurality of pieces of data with different frame addresses can be stored in the same index. The cache hit rate increases as the association degree increases. In particular, when it is configured by the number of sets of n tags (the number of ways), it is called an n-way set associative cache memory.

  In general, a large memory structure such as a cache memory is composed of several sub-blocks. For example, in the case of the 4-way set associative cache memory shown in FIG. 1, all the cache ways each include four SRAM blocks and peripheral circuits. In the case of such a cache memory, it is possible to perform control at the SRAM block level, remove defects of the SRAM cell generated in the manufacturing process, and effectively reduce the minimum operating voltage of the entire cache memory.

Here, the association degree of the cache memory of the 4-way set associative method will be described with reference to FIG. As shown in the figure, assuming that some SRAM cells have failed, in order to remove defects of the failed SRAM cells, control is performed at the SRAM block level, and the SRAM block including the failed SRAM cells is invalidated. Assume that.
Since the cache line of the invalidated SRAM block cannot be used, the association degree, which is the number of cache lines, that is, the number of tag sets (the number of ways) is reduced in the index including the cache line. Even if the degree of association decreases, there is no problem if there are other cache lines allocated. For example, in indexes 0 and 1 in FIG. 2, there are no cache lines in way 0 and way 1, but in ways 2 and 3, this cache memory has an association level of 2 in indexes 0 and 1. It is possible to operate.

Thus, even if the SRAM block including the failed SRAM cell is invalidated, normal operation as a cache memory is possible as long as another cache line exists at the same index. As described above, since the failed SRAM cells are randomly distributed in the cache memory, the number of invalidated SRAM blocks differs for each index. Accordingly, the association degree in each index of the cache memory takes various values.
In the case of FIG. 2, the cache memory operates at an association degree of 2 at indexes 0 and 1, an association degree of 4 at indexes 2 and 3, and an association degree of 3 at indexes 4-7.

However, as shown in FIG. 3, if all SRAM blocks of a particular index contain a failed SRAM cell, there will be no cache line to allocate data at that index. In such a situation, an appropriate operation as a cache memory cannot be performed. Therefore, there is a problem that the cache operation may not be performed simply by invalidating the block including the failed SRAM cell and simply excluding it from the cache operation.
Therefore, it is not preferable to simply invalidate and exclude the SRAM block including the failed SRAM cell (failed SRAM block) from the operation, and there is no cache line to allocate data at a specific index using the failed SRAM block as much as possible. I need to solve the problem.

On the other hand, the present inventors can dynamically change the bit reliability of the memory cell according to the application and the memory situation, and ensure the stability of the operation to reduce the power consumption and the high reliability. We are proposing a memory that can be realized.
The proposed memory has a mode in which 1 bit is composed of one memory cell (1 bit / 1 cell mode, hereinafter referred to as “normal mode”) and n memory cells in which 1 bit is n (n is 2 or more). Mode (1 bit / n cell mode, hereinafter referred to as “high reliability mode”) can be dynamically switched, and by switching from the normal mode to the high reliability mode, a 1-bit operation can be performed. This memory increases the stability and increases the cell current of the read operation (speeds up the read operation) and can self-repair bit errors (see Patent Documents 1 to 3).

  One embodiment of such a proposed semiconductor memory is cross-coupled as shown in FIG. 4 in which each output is connected to a path leading to each of a pair of bit lines arranged corresponding to a column of memory cells. In a memory cell comprising a pair of inverters, a pair of switch portions provided between the bit line and the output of the inverter, and one word line whose conduction can be controlled, two adjacent A pair of P-type MOS transistors and one mode control line capable of controlling the P-type MOS transistors to be conductive are added between data holding nodes of two memory cells.

Here, the circuit operation of the memory cell of FIG. 4 will be briefly described.
4 includes a P-type MOS transistor (M00) and an N-type MOS transistor (M02) connected in series between power supply potential VVDDA and ground potential VGNDA, power supply potential VVDDA and ground potential VGNDA. A latch circuit composed of a P-type MOS transistor (M01) and an N-type MOS transistor (M03) connected in series is formed. The memory cell (MC01) itself is a general 6-transistor memory cell.
Similarly, in memory cell (MC10), P-type MOS transistor (M10) and N-type MOS transistor (M12) connected in series between power supply potential VVDDB and ground potential VGNDB, and between power supply potential VVDDB and ground potential VGNDB. A latch circuit including a P-type MOS transistor (M11) and an N-type MOS transistor (M13) connected in series to each other is formed. The memory cell (MC10) itself is a memory cell having a general 6-transistor configuration.

  In the memory cell (MC01), the gate terminals of the P-type MOS transistor (M00) and the N-type MOS transistor (M02) are both connected to the node (N01) of the P-type MOS transistor (M01) and the N-type MOS transistor (M03). Has been. The gate terminals of the P-type MOS transistor (M01) and the N-type MOS transistor (M03) are both connected to the node (N00) of the P-type MOS transistor (M00) and the N-type MOS transistor (M02). Since the transistors M00 to M03 are thus cross-coupled, the P-type MOS transistors (M00, M01) operate as load transistors, and the N-type MOS transistors (M02, M03) operate as drive transistors. The same applies to the memory cell (MC10).

The memory cell (MC01) includes a switch portion of N-type MOS transistors (M04, M05) connected between the complementary bit lines (BL, / BL) and the nodes (N00, N01). The gate terminals of the N-type MOS transistors (M04, M05) are both connected to a common word line (WLA), and the gate potential of the N-type MOS transistors (M04, M05) is controlled by the word line (WLA). . That is, in the memory cell (MC01), the P-type MOS transistors (M00, M01) are used as load transistors, the N-type MOS transistors (M02, M03) are driven transistors, and the N-type MOS transistors (M04, M05) are used. It operates as a switch unit.
The memory cell (MC10) also includes a switch unit of N-type MOS transistors (M14, M15) connected between the complementary bit lines (BL, / BL) and the nodes (N10, N11). The gate terminals of the N-type MOS transistors (M14, M15) are both connected to a common word line (WLA), and the gate potential of the N-type MOS transistors (M14, M15) is controlled by the word line (WLA). .

  A pair of P-type MOS transistors (M20, M21) serving as a mode control switch unit are provided between the data holding nodes (between N00 and N10, between N01 and N11) of the memory cells (MC01, MC10). One mode control line (/ CTRL) for controlling the conduction of the P-type MOS transistors (M20, M21) is provided.

  In the memory cell having the circuit configuration as described above, 1-bit data is stored in the memory cell (MC01) and 1-bit data is stored in the two memory cells, the memory cell (MC01) and the memory cell (MC10). The mode control line (/ CTRL) can be used properly. The memory cell having the above circuit configuration has two modes: a mode in which 1 bit is constituted by one memory cell (normal mode) and a mode in which 1 bit is constituted by connecting two memory cells (high reliability mode). Therefore, the bit reliability of the memory cell can be dynamically changed according to the application and the memory condition, and the operation stability is ensured to realize low power consumption and high reliability.

International publication pamphlet WO2009 / 088020 International Publication Pamphlet WO2012 / 021277 JP 2011-040010 A

C. Wilkerson, H. Gao, AR Alameldeen, Z. Chishti, M. Khellah, and S. -L. Lu, “Trading Off Cache Capacity for Reliability to Enable Low Voltage Operation,” IEEE International Symposium Computer Architecture, pp 203-214, 2008 J. Kim, N. Hardavellas, K. Mai, B. Falasafi, and J. C. Hoe, “Multi-Bit Error Tolerant Caches Using Two-Dimensional Error Coding,” ACM / IEEE International Symposium MicroArchitecture, pp. 197-209, 2007

As described above, the set associative cache memory cannot operate properly by simply invalidating the SRAM block including the failed SRAM cell.
In view of the above situation, the present invention solves the problem that there is no cache line for allocating data at a specific index, and provides a low-voltage operation cache memory that can effectively reduce the operation voltage of the entire cache memory. For the purpose.

In order to achieve the above object, a low voltage operation cache memory of the present invention includes a data storage structure configured by tags, and a set associative cache memory including a plurality of cache ways including a plurality of memory cell blocks. The configuration is as follows.
First, a memory cell block includes a pair of cross-coupled inverters, each output being connected to a path leading to each of a pair of bit lines arranged corresponding to a column of memory cells, and a bit line and an inverter. A mode control switch unit between a memory cell composed of a pair of switch units provided between the output and one word line for controlling conduction of the switch unit, and between data holding nodes of adjacent memory cells And one mode control line for controlling the conduction of the mode control switch section.

  Then, for each memory cell block, from the normal mode in which one bit is composed of one memory cell, a high reliability mode in which two adjacent memory cells are connected and one bit is composed of two memory cells. When a memory cell block is detected to be faulty offline or online, the faulty memory cell block is switched to the high-reliability mode and one of two adjacent cache lines is used. A memory cell block is formed. As a result, the operation margin of the failed memory cell block is expanded and the minimum operation voltage of the entire cache memory is reduced.

  The memory cell block of the low-voltage operation cache memory according to the present invention has the above-described configuration. When the mode control switch between the data holding nodes of two adjacent memory cells is turned on (high reliability mode), 1 Bit data can be shared by two memory cells, thereby realizing high reliability. That is, at the time of writing, two word lines are simultaneously activated and simultaneously written into two memory cells. Thereby, the deterioration of the write margin in the upper and lower memory cells of the pair structure is alleviated. At the time of reading, only one word line is raised and data is read through the bit line. At the time of reading, a memory cell having a small read operation margin SNM (Static noise margin) is reinforced by the other memory cell. Further, since the effect of increasing the capacitance of the internal node can be obtained, the soft error resistance can also be improved.

When a memory cell block is detected offline or online, the memory cell block in which the failure is detected is switched to the high-reliability mode without specifying which memory cell has failed. A memory cell block that uses one of the lines. As described above, in the high reliability mode, the operation margin of the memory cell is increased, so that the operation margin of the memory cell block can be expanded.
Further, by switching to the high reliability mode for each memory cell block, the area overhead of peripheral circuits (XY decoder circuit, sense amplifier circuit, etc.) is reduced.

  Here, in the memory cell block in which the low-voltage operation cache memory of the present invention has failed, when switching to the high-reliability mode and using one of the two adjacent cache lines, all the cache indexes of the cache memory are It is preferable to allocate a cache line so that a cache operation can be performed with an association degree equal to or more than half the number of cache ways.

For all cache indexes in the cache memory, cache operation with more than half of the number of cache ways is possible, minimizing variation in association between cache indexes and increasing the cache hit rate Can be maintained.
For example, in the case of a 4-way set associative cache memory, a cache line is allocated so as to enable a cache operation with an association degree of 2 or higher. In the case of an 8-way set associative cache memory, a cache line is allocated so as to enable a cache operation with an association degree of 4 or higher.

  In a four-way set associative cache memory, if all four SRAM blocks of a specific index include a failed SRAM cell, as shown in FIG. 3 above, all four SRAM blocks are reliable. In order to switch to the mode and enable a cache operation with an association degree of 2 or more, each SRAM block is assigned to use one of two adjacent cache lines. As shown in FIG. 5, for example, when way 0 and way 2 are assigned to the upper cache line and way 1 and way 3 are assigned to the lower cache line, the association degree can be maintained at 2.

Specifically, the cache operation can be performed with an association degree equal to or more than half the number of cache ways by assigning the cache line as follows.
First, in the memory cell block in which the low-voltage operation cache memory of the present invention has failed, when switching to the high-reliability mode and using one of the two adjacent cache lines, the memory cell block of the even-numbered cache way In this case, even-numbered cache lines are assigned, and in the case of odd-numbered cache way memory cell blocks, odd-numbered cache lines are assigned.

  Further, in the memory cell block in which the low-voltage operation cache memory of the present invention has failed, when switching to the high reliability mode and using one of the two adjacent cache lines, the memory cell block of the even-numbered cache way In this case, odd-numbered cache lines are assigned, and in the case of odd-numbered cache way memory cell blocks, even-numbered cache lines are assigned.

  In the memory cell block in which the low-voltage operation cache memory according to the present invention is faulty, when switching to the high reliability mode and using one of the two adjacent cache lines, the number of cache ways is N (number is 0). , 1,..., N−1), and even if the cache cell is a memory cell block with a number less than N / 2, an even-numbered cache line is assigned and the cache with a number greater than or equal to N / 2. In the case of a way memory cell block, an odd index cache line is allocated.

  In the memory cell block in which the low-voltage operation cache memory according to the present invention is faulty, when switching to the high reliability mode and using one of the two adjacent cache lines, the number of cache ways is N (number is 0). , 1,..., N−1), and in the case of a memory cell block of a cache way with a number less than N / 2, an odd index cache line is assigned and a cache with a number greater than or equal to N / 2. In the case of a way memory cell block, an even index cache line is allocated.

In addition, in the memory cell block in which the low-voltage operation cache memory of the present invention has failed, the cache line status bit of the invalid cache line that is not used is used as identification information in which one of two adjacent cache lines is used in the high reliability mode. Is preferably set to {Valid bit, Dirty bit} = {0, 1}.
In a general write-back cache memory, the state of {Valid bit, Dirty bit} = {0, 1} cannot be taken. Therefore, as described above, the invalid cache line can be used to determine the invalid cache line by setting the valid bit and dirty bit of the invalid cache line to 0 and 1, respectively.

Next, an LRU (Least Recently Used) replacement algorithm for the low voltage operation cache memory of the present invention will be described.
In the LRU replacement algorithm of the low voltage operation cache memory according to the present invention, when the failed memory cell block is in the high reliability mode, the LRU tree bits of the invalid cache line not used are fixed to the MRU (Most Recently Used) state.
In the LRU replacement algorithm, the LRU cache line becomes a replacement target. However, by always fixing the invalid cache line to the MRU state, it is possible to prevent the invalid cache line from becoming the replacement target cache line.

Further, the LRU (Least) of the low voltage operation cache memory of the present invention is used.
Recently Used) In the replacement algorithm, when there are M invalid cache lines that are not used when the failed memory cell block is in the high-reliability mode, the LRU tree bits of the invalid cache lines that are not used are set to 0 (MRU) in the order of the cache way number. 1, ..., M-1.
With the above configuration, when the processor switches from the low voltage mode to the high voltage mode in the DVS control, it is necessary to switch the SRAM block that has failed in the low voltage region and operated in the high reliability mode to the normal mode. In this case, it is not necessary to reset the LRU tree bit, and it is only necessary to turn off the mode control switch provided between the data holding nodes of adjacent memory cells.

  Further, in the LRU replacement algorithm of the low voltage operation cache memory of the present invention, when there are M invalid cache lines that are not used, the LRU tree bit of the cache line of new data assigned when a cache miss occurs is set to M, The LRU tree bits of other cache lines to be used are incremented by 1 in order from M + 1 according to the order before the cache miss occurred.

  For example, in a 4-way set associative cache memory, if there is one invalid cache line at a certain index, the LRU status bit of the invalid cache line is fixed to the MRU status (for example, 0) as described above, and a cache miss The LRU tree bit of the cache line of the new data allocated when the error occurs is set to 1, and the LRU tree bits of the other cache lines to be used are set to 2 and 3, respectively, according to the order before the cache miss occurs.

  For example, in a 4-way set associative cache memory, if there are two invalid cache lines in an index, the LRU tree bit of the invalid cache line is fixed to 0 (MRU) as described above, or invalid. The LRU tree bits of the cache line are fixed to 0 (MRU) and 1 in the order of the cache way numbers. The LRU tree bit of the cache line of new data allocated when a cache miss occurs is set to 2, and the LRU tree bit of the other cache line to be used is set to 3.

  Further, in the LRU replacement algorithm of the low voltage operation cache memory of the present invention, when there are M invalid cache lines that are not used, the LRU tree bit of the cache line in which the cache hit has occurred is set to M, and other cache lines to be used The LRU tree bits are incremented by 1 sequentially from M + 1 according to the order before the cache miss occurred.

  For example, in a 4-way set associative cache memory, if there is one invalid cache line in a certain index, the LRU tree bit of the invalid cache line is fixed to 0 (MRU) as described above, or the invalid cache line The LRU tree bits are fixed to 0 (MRU) and 1 in the order of the cache way number, the LRU tree bit of the cache line in which the cache hit occurs is set to 1, and the LRU tree bit of the other cache line to be used is set to the cache miss. According to the order before waking up, make it a few respectively.

  Also, for example, in a 4-way set associative cache memory, when there are two invalid cache lines in a certain index, the LRU tree bit of the invalid cache line is fixed to the MRU state (for example, 0) as described above. The LRU tree bit of the cache line in which the cache hit has occurred is set to 2, and the LRU tree bit of the other cache line to be used is set to 3.

According to the low voltage operation cache memory of the present invention, instead of simply invalidating the SRAM block including the failed SRAM cell (failed SRAM block), the failed SRAM block is switched to the high-reliability mode, and the failed SRAM block has an operation margin. It can be reconfigured into an SRAM block with the original half cache line expanded.
Further, according to the low voltage operation cache memory of the present invention, even when there is a failure SRAM block, the association degree is 2 or more, and an appropriate cache operation can be performed.
That is, according to the low voltage operation cache memory of the present invention, it is possible to solve the problem that there is no cache line for allocating data at a specific index, and to effectively reduce the operation voltage of the entire cache memory.

4-way set associative cache memory circuit diagram Data structure diagram of 4-way set associative cache memory Illustration of conventional problems Circuit configuration diagram of memory cell pair to improve bit reliability of memory cell Explanatory diagram of using memory cell pairs for conventional problems Data structure diagram of cache memory of set associative method of embodiment 1 Example of selection pattern of cache line of set associative cache memory of embodiment 1 A circuit diagram showing that even-numbered cache way memory cell blocks are assigned even-numbered cache lines and odd-numbered cache way memory cell blocks are assigned odd-indexed cache lines. Data structure diagram of 8-way set associative cache memory Explanation of cache line status bits Cache memory block diagram Explanatory drawing of the LRU replacement algorithm of the set associative cache memory of Embodiment 1 (case where a cache miss occurs) Explanatory drawing of the LRU replacement algorithm of the set associative cache memory of the first embodiment (case where a cache hit occurs) Minimum operating voltage measurement result graph in SRAM block Explanatory diagram of LRU replacement algorithm (switching from normal mode to high reliability mode) for 8-way set associative cache memory (1) Explanatory diagram of LRU replacement algorithm (switching from normal mode to high reliability mode) for 8-way set associative cache memory (2) Explanatory diagram of LRU replacement algorithm (switch from high reliability mode to normal mode) for 8-way set associative cache memory (1) Explanatory diagram of LRU replacement algorithm (switch from high reliability mode to normal mode) for 8-way set associative cache memory (2) Explanatory diagram of LRU replacement algorithm (cache miss) for 8-way set associative cache memory (1) Explanatory diagram of LRU replacement algorithm (cache miss) for 8-way set associative cache memory (2) Explanatory diagram of LRU replacement algorithm (cache hit) for 8-way set associative cache memory (1) Explanatory diagram of LRU replacement algorithm (cache hit) for 8-way set associative cache memory (2) Explanatory diagram of LRU replacement algorithm (cache miss when there are multiple invalid cache lines) for 8-way set associative cache memory (1) Explanatory drawing of the LRU replacement algorithm (cache miss when there are multiple invalid cache lines) for the 8-way set associative cache memory (2) Explanatory diagram of LRU replacement algorithm (cache hit when there are multiple invalid cache lines) for 8-way set associative cache memory (1) Explanatory diagram of LRU replacement algorithm (cache hit when there are multiple invalid cache lines) for the 8-way set associative cache memory (2) Explanatory diagram of LRU replacement algorithm (cache miss when there are multiple invalid cache lines) for 8-way set associative cache memory (3) Explanatory drawing of LRU replacement algorithm (cache miss when there are multiple invalid cache lines) for cache memory of 8-way set associative method (4) Explanatory diagram of LRU replacement algorithm (cache hit when there are multiple invalid cache lines) for 8-way set associative cache memory (3) Explanatory diagram of LRU replacement algorithm (cache hit when there are multiple invalid cache lines) for 8-way set associative cache memory (4)

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The scope of the present invention is not limited to the following examples and illustrated examples, and many changes and modifications can be made.

FIG. 6 illustrates a data structure diagram of the cache memory of the 4-way set associative method according to the first embodiment.
Each way is composed of four SRAM blocks. In addition, each memory cell of each SRAM block is a memory cell pair adjacent to each other in the vertical direction. As shown in FIG. 4, data of a 1-bit memory cell pair (MC01, MC10) composed of 6 transistors is used. A pair of P-type MOS transistors (M20, M21) and a mode control line (/ CTRL) for controlling conduction of the P-type MOS transistor are provided between the holding nodes as a mode control switch unit. . The memory cell pair adjacent to the upper and lower sides realizes two modes, a normal mode and a high reliability mode in which an operation margin is expanded.
In the normal mode, one bit is composed of one memory cell (MC01 or MC10). On the other hand, the high-reliability mode is composed of a pair of memory cells (MC01, MC10) in which one bit is two. Switching between the two operation modes is performed by one mode control line (/ CTRL) for controlling the conduction of the P-type MOS transistor between the pair of memory cells (MC01, MC10).
A way is constituted by SRAM blocks in which such memory cell pairs are arranged in a matrix, and has a data structure of a cache memory as shown in FIG.

  In the data structure diagram shown in FIG. 6, in the data structure of FIG. 2, each SRAM block in the first stage of way 0, the first stage of way 1, the third stage, and the fourth stage of way 3 is defective. When this occurs, the failed SRAM blocks in the first stage of way 0, the first stage of way 1, the third stage, and the fourth stage of way 3 are switched to the high reliability mode in which the operation margin is expanded. At that time, it is not searched for which memory cell has failed, and the entire failed SRAM block is in the high reliability mode. In a failed SRAM block that has entered the high-reliability mode, it is possible to generate a half cache line with an expanded operation margin. Therefore, it is possible to continue using the failed SRAM block instead of simply excluding the failed SRAM block from the cache operation.

  Therefore, the average association degree is improved as compared with the case where the failed SRAM block is simply excluded from the operation. This will be described in detail. In the case of the data structure shown in FIG. 2, the number of SRAM blocks that have not failed for indexes 0 to 7 is 3, 3, 4, 4, 3, 4, 3, and 4, respectively. Here, if the failed SRAM block is simply excluded from the cache operation, the number of non-failed SRAM blocks for indexes 0 to 7 is 2, 2, 4, 4, 3, 3, 3, 3. Therefore, the average association degree of the entire cache memory is (2 + 2 + 4 + 4 + 3 + 3 + 3 + 3) ÷ 8 = 3.

  On the other hand, in the case of the data structure diagram of FIG. 6, the number of SRAM blocks that have not failed for indexes 0 to 7 are 3, 3, 4, 4, 3, 4, 3, and 4, respectively. In the case of FIG. 6, since the failed SRAM block is switched to the high reliability mode and the operation margin is expanded and the cache operation is continued as it is, the number of non-failed SRAM blocks for indexes 0 to 7 is 3, 3, 4 , 4, 3, 4, 3 and 4. Therefore, the average association degree of the entire cache memory is improved to (3 + 3 + 4 + 4 + 3 + 4 + 3 + 4) ÷ 8 = 3.5.

FIG. 7 illustrates an example of a cache line selection pattern of the set associative cache memory according to the first embodiment. FIG. 7A shows an index in the case of memory cell blocks of even-numbered cache ways (way 0, 2,..., 6) when the indexes of two adjacent cache lines are N and N + 1. Number N cache line is allocated (ENABLE
CACHE LINE is assigned), and in the case of an odd-numbered cache way (way 1, 3,..., 7) memory cell block, a selection pattern in which an index cache line with index number N + 1 is assigned is shown. For example, if N is an even number, an even-numbered cache way memory cell block is assigned an even-numbered cache line, and an odd-numbered cache way memory cell block is assigned an odd-indexed cache line. It is done. When N is an odd number, an odd-numbered cache way memory cell block is assigned an odd-numbered cache line, and an odd-numbered cache way memory cell block is assigned an even-numbered cache line. It is done.

FIG. 7B shows an index number N in the case of the memory cell block of the cache way (way 0, 1, 6, 7) when the indexes of two adjacent cache lines are N and N + 1. A cache line is assigned (ENABLE
In the case of memory cell blocks of other cache ways (way 2, 3, 4, 5), a selection pattern in which an index cache line of index number N + 1 is assigned is shown.

In FIG. 7C, when the indexes of two adjacent cache lines are N and N + 1, the memory cell block of the cache way (way 0, 1, 6, 7) has the index number N + 1. A cache line is assigned (ENABLE
In the case of memory cell blocks of other cache ways (way 2, 3, 4, 5), a selection pattern in which an index cache line of index number N is assigned is shown.

  As described above, in the failed SRAM block, when switching to the high reliability mode and using one of the two adjacent cache lines, all cache indexes of the cache memory have an association degree equal to or more than half the number of cache ways. The cache line is allocated so that the cache operation can be performed.

  FIG. 8 is a circuit diagram of the selection pattern of FIG. 7A. In the case of even-numbered cache way memory cell blocks, cache lines with index numbers N, N + 2,. In the case of the memory cell block of the numbered cache way, a circuit diagram showing how cache lines with index numbers N + 1, N + 3,..., N + 63 are allocated is shown. FIG. 8A shows the memory cell circuit structure of the memory cell block of the even-numbered cache way, in which the lower memory cells in the upper and lower adjacent memory cell pairs are invalidated (DISABLE), and the index numbers N, N + 2 ,..., N + 62 cache lines are allocated. FIG. 8 (2) shows a memory cell circuit structure of a memory cell block of an odd-numbered cache way, in which the upper memory cell of the upper and lower adjacent memory cell pairs is invalidated (DISABLE), and index numbers N + 1, N + 3, ..., N + 63 cache lines are allocated.

FIG. 9 is a data structure diagram of an 8-way set associative cache memory. Each way is a 512 Kbit 8-way set associative cache memory having four 16 Kbit SRAM blocks and 32 SRAM blocks as a whole.
In the case of an odd-numbered cache way memory cell block, an odd index cache line is assigned (an even index cache line is invalid).
As shown in FIG. 9, if the SRAM block at the second stage of way 1 is a failure block, the cache line of the even index becomes invalid when switching to the high reliability mode, and the odd index (index 65, 67,. .., 125, 127) are only allocated. As a result, the association degrees of the index numbers 64 to 127 are 7, 8, 7, 8,.

FIG. 10 is an explanatory diagram of the status bits of the cache line. In the failed SRAM block, in the high-reliability mode, {Valid bit, Dirty bit} indicates the cache line state bits of the invalid state (INVALID) cache line that is not used as identification information for using which of the two adjacent cache lines is used. = Set to {0,1}.
As described above, the invalid cache line can be easily determined by using the property of the state bit of the cache.
In a general write-back cache memory, the state of {Valid bit, Dirty bit} = {0, 1} cannot be taken. Therefore, as described above, the valid bit and dirty bit of the invalid cache line are set to 0 and 1, respectively, and used to determine the invalid cache line. Other cache line states (EMPTY, CLEAN, DIRTY) are used in advance and are not particularly changed in the present invention.

  FIG. 11 is a block diagram of the cache memory. The cache memory shown in FIG. 11 is a 64 KB 8-way set associative cache memory (32-byte cache line), and a data array is composed of four SRAM banks. As shown in the figure, the tag array is composed of four SRAM blocks in accordance with the data array. As a data array and tag array SRAM cell, as shown in FIG. 4, a pair of P-type as a mode control switch unit is provided between data holding nodes of a 1-bit memory cell pair (MC01, MC10) composed of 6 transistors. A cell provided with MOS transistors (M20, M21) and one mode control line (/ CTRL) for controlling the conduction of the P-type MOS transistor is used. The memory cell pair adjacent to the upper and lower sides realizes two modes, a normal mode and a high reliability mode in which an operation margin is expanded. Switching control between the normal mode and the high-reliability mode can be performed in units of SRAM blocks. The cache status RAM is composed of 1-bit memory cells composed of 6 transistors in one block. The cache status RAM stores VALID, DIRTY, cache block replacement algorithm information (such as LRU), and the like, as in a general cache.

Next, an LRU (Least Recently Used) replacement algorithm for the cache memory of the present invention will be described.
FIG. 12 is an explanatory diagram of a 4-way set associative cache memory LRU replacement algorithm according to the first embodiment (a case where a cache miss occurs). FIG. 12 (1) shows an example of the cache operation by the conventional LRU replacement algorithm, and FIG. 12 (2) shows an example of the cache operation by the LRU replacement algorithm improved so as to be applied to the cache memory of the present invention. ing. In order to simplify the description, a state in which any SRAM block constituting the way is switched to the high reliability mode is illustrated as if the way has been switched to the high reliability mode as shown in FIG.

First, the cache operation according to the conventional LRU replacement algorithm of FIG. The high-reliability mode is applied to the cache way 2 (WAY 2) on the assumption that the LRU tree bits of the four cache ways (WAY 0 to 3) are in a certain order. In order to remove the invalid cache line from the cache operation, in the SRAM block operating in the high reliability mode, the LRU state of the logically invalid index is set to MRU (Most
Recently Used), that is, fix the LRU tree bit to 0. This avoids data being assigned to invalid cache lines.
In the conventional LRU replacement algorithm, when a cache miss occurs while the cache way 2 is logically invalidated, the cache line (cache way 0) of the LRU (LRU tree bit is 3) on the LRU tree is generated. New data is allocated, and the cache line is set to MRU (LRU tree bit is 0). The LRU tree bits of the other cache lines are each incremented by 1 (WAY1: 2-> 3, WAY2: 0-> 1, WAY3: 1-> 2).

Next, the cache operation according to the improved LRU replacement algorithm of FIG. In the improved LRU replacement algorithm, when a cache miss occurs, when assigning new data to a cache line in the LRU state, if there are N invalid cache lines to which the high reliability mode is applied, the new data is transferred. The LRU tree bit of the allocated cache line is MRU + N, that is, if there is one invalid cache line to which the high-reliability mode is applied as shown in FIG. 12, the LRU of the cache line (cache way 0) to which new data is allocated The tree bit is set to 0 + 1 = 1. The LRU tree bits of other valid cache lines that are not invalid are each incremented by 1 (WAY 1: 2-> 3, WAY 3: 1-> 2).
If there is no invalid cache line, the same operation as the conventional LRU replacement algorithm is performed.

  FIG. 13 is an explanatory diagram of an LRU replacement algorithm for a 4-way set associative cache memory according to the first embodiment (a case where a cache hit occurs). FIG. 13A shows an example of the cache operation by the conventional LRU replacement algorithm, and FIG. 13B shows an example of the cache operation by the LRU replacement algorithm improved to be applied to the cache memory of the present invention. ing. In FIG. 13, as in FIG. 12, in order to simplify the description, a state in which any SRAM block constituting the way is switched to the high reliability mode is illustrated as if the way has been switched to the high reliability mode.

  First, the cache operation according to the conventional LRU replacement algorithm of FIG. The high-reliability mode is applied to the cache way 2 (WAY 2) on the assumption that the LRU tree bits of the four cache ways (WAY 0 to 3) are in a certain order. In order to remove the invalid cache line from the cache operation, in the SRAM block operating in the high-reliability mode, the LRU state of the logically invalid index is fixed to MRU (Most Recently Used), that is, the LRU tree bit is set to 0. This avoids data being assigned to invalid cache lines.

  In the conventional LRU replacement algorithm, when a cache hit occurs in the cache way 1 in a state where the cache way 2 is logically invalidated, the cache line of the cache way 1 in which the cache hit occurs is transferred to the MRU (LRU tree bit). Is 0). Among the other cache lines, the LRU tree bit of the cache line whose state of the LRU tree bit is smaller than the cache line hit by the cache hit is incremented by one. In the example shown in FIG. 13, the LRU tree of the cache way 2 (LRU tree bit is 0) and the cache way 3 (LRU tree bit is 1) whose LRU tree bit value is smaller than the cache way 1 (LRU tree bit is 2). Increment the bit by one.

Next, the cache operation according to the improved LRU replacement algorithm of FIG. In the improved LRU replacement algorithm, if there are N invalid cache lines to which the high-reliability mode is applied, if a cache hit occurs in the cache way 1, the LRU tree bit of the cache way 1 in which the cache hit occurs is set to MRU + N That is, if there is one invalid cache line to which the high-reliability mode is applied as shown in FIG. 13, the LRU tree bit of the cache way 1 in which the cache hit occurs is set to 0 + 1 = 1. In addition to other valid cache lines that are not invalid, the LRU tree bits whose LRU tree bit state is smaller than the LRU tree bit state (state 2 in FIG. 13) of the cache line 1 that has a cache hit are incremented by one. In the example of FIG. 13, the cache way 3 has an LRU tree bit that is smaller than the state of the LRU tree bit of the cache line 1, and increments the LRU tree bit of the cache way 3 by 1 (WAY 3: 1-> 2).
If there is no invalid cache line, the same operation as the conventional LRU replacement algorithm is performed.

FIG. 14 is a graph of the minimum operating voltage measurement result in the SRAM block. The cache memory to be measured is a 512 Kbit 8-way set associative cache memory that was prototyped in a 65 nm CMOS process. It consists of 32 16Kbit SRAM blocks, and each way consists of 4 SRAM blocks.
It has been found that this cache memory can operate at 0.57 (V) in the high reliability mode. Therefore, the entire operating voltage can be reduced by applying the high reliability mode only to the SRAM block that cannot operate at 0.57 (V) in the normal mode.
In the graph of FIG. 14, the left side shows a normal mode and the right side shows a high reliability mode, and the operating voltages of 32 SRAM blocks (0 to 31) are measured. In the normal mode, 0.65 (V) to 0.57 (V) is obtained by applying the high reliability mode to the five SRAM blocks (6, 8, 16, 25, 28) marked with a circle in the figure. The effect of reducing the operating voltage of 80 (mV) can be obtained. In this case, since the memory capacity of each of the 5 blocks of 16 Kbits is halved, the total memory capacity is reduced by 16 × 5 × 0.5 = 40 Kbits to 512-40 = 472 Kbits. Therefore, the capacity overhead of the cache memory is 40 ÷ 512 × 100 = 7.81 (%).

Next, the area overhead of the cache memory will be described. For the assessment of area overhead, CACTI (for details, see N. Muralimanohar, R. Balasubramonian,
and NP Jouppi, “CACTI
6.0, ”Technical Report HPL-2009-85, Hewlett Packard Labs, 2009).
The area of the SRAM cell (Proposed) using the memory cell pair (configured with 14 transistors) used in the cache memory of the present invention is equal to the SRAM cell pair (6T
11% larger than the area of SRAM) (For details, see H. Fujiwara, S. Okumura, Y. Iguchi, H.
Noguchi, H. Kawaguchi and M. Yoshimoto, “A
7T / 14T Dependable SRAM and Its Array Structure to Avoid Half Selection, ”IEEE
See International Conference on VLSI Design, pp. 295-300, 2009. ).
In the case of the 512 Kbit (64 KB) 8-way set associative method with a 32-byte cache line, which is the object of evaluation, the capacity of the tag array is as small as 4.75 KB, and the influence of variations is considered to be relatively small. STATUS in the assessment of area overhead
Like the RAM, it is composed of a 6-transistor SRAM. The tag array is assumed to use a 6-transistor SRAM that can operate at 0.5 (V) and is 1.3 times larger than the minimum area.

  Table 1 below shows the results of estimating the area overhead of a 512 Kbit (64 KB) 8-way set associative cache memory. In the 65 nm process, the cache memory of the present invention had an area overhead of 5.22%.

Referring to FIGS. 15 to 30, an example is given of an 8-way set associative cache memory in which there are a plurality (M) of failed SRAM blocks and a plurality (M) of invalid cache lines. explain.
Here, MRU is 0 and LRU is 7. Further, as in the first embodiment, for simplicity of explanation, a state in which any SRAM block constituting the way is switched to the high reliability mode is illustrated as if the way has been switched to the high reliability mode.
FIG. 15 shows a state in which the LRU state of M invalid cache lines is set to MRU (= 0) when switching to the high-reliability mode online and there are M invalid cache lines (M = 3). Yes. Further, other non-invalid cache lines are changed from M (= 3) to N-1 (= 7) according to the order of the LRU tree bits. Here, N is the number of ways.
In FIG. 15, cache ways 2, 4, and 6 are SRAM blocks that operate in the high-reliability mode, and are index cache lines that are logically invalidated (M = 3). The LRU states of the cache ways 2, 4 and 6 are all fixed at MRU (= 0), and the LRU states of the other cache lines are 3 to 7 in the order of the LRU tree bits.

Also, FIG. 16 shows that when switching to the high-reliability mode online and there are M invalid cache lines (M = 3), the MRU invalid cache line LRU states are changed from MRU (= 0) to M in order of way number. Set to -1 (= 2). Further, other non-invalid cache lines are changed from M (= 3) to N-1 (= 7) according to the order of the LRU tree bits. Here, N is the number of ways.
In FIG. 16, cache ways 2, 4, and 6 are SRAM blocks that operate in the high reliability mode, and are cache lines of indexes that are logically invalidated (M = 3). The LRU states of the cache ways 2, 4 and 6 are fixed to MRU (= 0), 1 and 2 in order, and the LRU states of the other cache lines are 3 to 7 in the order of the LRU tree bits.

For example, when the processor is in DVS control, Low
When switching from the voltage mode to the high voltage mode, it is necessary to switch the SRAM block that has failed in the low voltage region and operated in the high reliability mode to the normal mode. At that time, as shown in FIG. 16, if the LRU states of the cache ways 2, 4 and 6 operating in the high-reliability mode are fixed to MRU (= 0), 1 and 2 in order, the LRU tree bit (See FIG. 17), it is only necessary to turn off the mode control switch (PMOS switch) of the memory cell pair in the data array and the tag array.

  On the other hand, as shown in FIG. 15, when all the LRU states of the cache ways 2, 4 and 6 operating in the high reliability mode are fixed to MRU (= 0), all the LRU tree bits of the invalid cache line are all Since it is MRU (= 0), when the SRAM block is switched to the normal mode, it is necessary to reset the LRU tree bits so that the LRU states of the cache ways 2, 4, 6 are 0, 1, 2, etc. (See FIG. 18).

Next, an LRU replacement algorithm for an 8-way set associative cache memory when one invalid cache line is not used will be described with reference to FIGS. 19 and 20 are explanatory diagrams of cache misses, and FIGS. 21 and 22 are explanatory diagrams of cache hits.
19 to 22 show a case where only the cache way 2 (WAY 2) is in the high-reliability mode and the number of invalid cache lines not used is one.
FIG. 19 shows a case where the conventional LRU replacement algorithm is applied. When a cache miss occurs, the cache way 1 of LRU (= 7) is updated with LRU tree bits to become MRU (= 0). This shows a state where the state of the LRU tree bit of the cache way is incremented by one.

  On the other hand, FIG. 20 shows a case where the improved LRU replacement algorithm is applied. When a cache miss occurs, the LRU (= 7) cache way 1 is updated with LRU tree bits and MRU + 1 = 1. The state of the LRU tree bit state of another valid cache way is incremented by one. The state of the LRU tree bit of the cache way 2 (WAY 2) is fixed to MRU (= 0).

  FIG. 21 shows a case where a conventional LRU replacement algorithm is applied. A cache hit occurs in the cache way 3, the state of the LRU tree bit becomes MRU (= 0), and the cache way in which the cache hit occurs The state of the LRU tree bits of the other cache ways (0 to 5) smaller than the state of 3 LRU tree bits is incremented by one.

  On the other hand, FIG. 22 shows a case where an improved LRU replacement algorithm is applied. A cache hit occurs in the cache way 3, the state of the LRU tree bit becomes MRU + 1 = 1, and the cache way 3 in which the cache hit occurs The state of the LRU tree bits of other valid cache ways that are smaller than the state of the LRU tree bits and the state of the LRU tree bits is not the invalid cache line of the MRU (= 0) is incremented by one. Yes.

Next, an LRU replacement algorithm for an 8-way set associative cache memory when there are three invalid cache lines not used will be described with reference to FIGS. 23 and 24 are explanatory diagrams of cache misses, and FIGS. 25 and 26 are explanatory diagrams of cache hits.
23 to 26 show a case where the three cache ways 2, 4, 6 (WAY 2, WAY 4, WAY 6) are in the high-reliability mode and the number of unused invalid cache lines is three.
FIG. 23 shows a case where the conventional LRU replacement algorithm is applied. When a cache miss occurs, the cache way 1 of LRU (= 7) is updated with LRU tree bits to become MRU (= 0). This shows a state where the state of the LRU tree bit of the cache way is incremented by one. Here, the LRU tree bit states of the three cache ways 2, 4, 6 (WAY2, WAY4, WAY6) are all set to MRU (= 0) when the high-reliability mode is switched. When this occurs, it is incremented by 1 and all become 1.

  On the other hand, FIG. 24 shows a case where the improved LRU replacement algorithm is applied. When a cache miss occurs, the LRU (= 7) cache way 1 is updated with LRU tree bits and MRU + 3 (invalid not used) (Number of cache lines) = 3, and the state of the LRU tree bit of another valid cache way is incremented by one. The state of the LRU tree bits of the three cache ways 2, 4, 6 (WAY2, WAY4, WAY6) is fixed to MRU (= 0).

  FIG. 25 shows a case where the conventional LRU replacement algorithm is applied. A cache hit occurs in the cache way 3, the state of the LRU tree bit becomes MRU (= 0), and the cache way in which the cache hit occurs. The state of the LRU tree bits of the other cache ways (0 to 5) smaller than the state of 3 LRU tree bits is incremented by one. The states of the LRU tree bits of the three cache ways 2, 4, 6 (WAY2, WAY4, WAY6) are also incremented by 1 and all become 1.

  On the other hand, FIG. 26 shows a case where the improved LRU replacement algorithm is applied. A cache hit occurs in the cache way 3, the state of the LRU tree bit becomes MRU + 3 = 3, and the cache way 3 in which the cache hit occurs The state of the LRU tree bits of other valid cache ways that are smaller than the state of the LRU tree bits and the state of the LRU tree bits is not the invalid cache line of the MRU (= 0) is incremented by one. Yes. The state of the LRU tree bits of the three cache ways 2, 4, 6 (WAY2, WAY4, WAY6) is fixed to MRU (= 0).

Next, another LRU replacement algorithm for an 8-way set associative cache memory when there are three invalid cache lines not used will be described with reference to FIGS. 27 and 28 are explanatory diagrams of cache misses, and FIGS. 29 and 30 are explanatory diagrams of cache hits.
27 to 30 show a case where the three cache ways 2, 4, 6 (WAY 2, WAY 4, WAY 6) are in the high-reliability mode and the number of unused invalid cache lines is three.
FIG. 27 shows a case where a conventional LRU replacement algorithm is applied. When a cache miss occurs, the cache way 1 of LRU (= 7) is updated with LRU tree bits to become MRU (= 0). This shows a state where the state of the LRU tree bit of the cache way is incremented by one. Here, the states of the LRU tree bits of the three cache ways 2, 4, 6 (WAY2, WAY4, WAY6) are set to 0, 1, 2 in order of increasing way number when the high-reliability mode is switched. When a cache miss occurs, it is incremented by 1 to 1, 2, and 3, respectively.

On the other hand, FIG. 28 shows a case where the improved LRU replacement algorithm is applied. When a cache miss occurs, the cache way 1 of LRU (= 7) is updated with LRU tree bits and MRU + 3 (invalid not used) (Number of cache lines) = 3, and the state of the LRU tree bit of another valid cache way is incremented by one. Here, the states of the LRU tree bits of the three cache ways 2, 4, 6 (WAY2, WAY4, WAY6) are set to 0, 1, 2 in order of increasing way number when the high-reliability mode is switched. It is fixed as it is.
That is, when there are M invalid cache lines that are not used, the LRU states of the M invalid cache lines are set from MRU (= 0) to M-1 in order of way number, and assigned when a cache miss occurs. M is the LRU tree bit of the new data cache line,
The LRU tree bits of the other cache lines to be used are incremented by 1 in order from M + 1 according to the order before the cache miss occurred.

  FIG. 29 shows a case where the conventional LRU replacement algorithm is applied. A cache hit occurs in cache way 3, the state of the LRU tree bit becomes MRU (= 0), and the cache way in which the cache hit occurs The state of the LRU tree bits of the other cache ways (0 to 5) smaller than the state of 3 LRU tree bits is incremented by one. The state of the LRU tree bits of the three cache ways 2, 4, 6 (WAY2, WAY4, WAY6) is also incremented by 1 from 0, 1, 2 to 1, 2, 3.

On the other hand, FIG. 30 shows a case where an improved LRU replacement algorithm is applied. A cache hit occurs in the cache way 3, and the state of the LRU tree bit is MRU + 3 (the number of invalid cache lines not used) = 3. The state of the LRU tree bit of another valid cache way that is smaller than the state of the LRU tree bit of the cache way 3 where the cache hit has occurred and the state of the LRU tree bit is not the invalid cache line of MRU (= 0) It shows a state where it is incremented by one. The state of the LRU tree bits of the three cache ways 2, 4, 6 (WAY2, WAY4, WAY6) is fixed with 0, 1, 2 set in ascending order of the way number when the high-reliability mode is switched. Has been.
That is, when there are M invalid cache lines that are not used, the LRU states of the M invalid cache lines are set from MRU (= 0) to M-1 in order of way number, and the cache line where the cache hit has occurred is set. Let the LRU tree bit be M,
The LRU tree bits of the other cache lines to be used are incremented by 1 sequentially from M + 1 according to the order before the cache hit occurs.

  The present invention is useful for a cache memory of a computer.

MC, MC01, MC10 Memory cell

Claims (11)

In a set associative cache memory having a data storage structure constituted by tags and having a plurality of cache ways constituted by a plurality of memory cell blocks,
The memory cell block includes:
Provided between a pair of cross-coupled inverters, each output connected to a path leading to each of a pair of bit lines arranged corresponding to a column of memory cells, and the output of the bit line and the inverter A memory cell including a pair of switch units and a word line for controlling conduction of the switch unit, a mode control switch unit between data holding nodes of adjacent memory cells, and the mode control switch unit A mode control line for controlling the conduction of
For each memory cell block,
It is a circuit configuration that can switch from a normal mode in which one bit is composed of one memory cell to a high-reliability mode in which two adjacent memory cells are connected and one bit is composed of two memory cells. ,
When a failure is detected in the memory cell block offline or online, the memory cell block in which the failure is detected is switched to the high-reliability mode, and two adjacent cache lines are used without using information on which memory cell has failed. low voltage operation cache memory, characterized in that the memory cell blocks either always use the.
In the failed memory cell block, when switching to the high reliability mode and using one of the two adjacent cache lines,
2. The low voltage operation according to claim 1, wherein a cache line is allocated to all cache indexes of the cache memory so that a cache operation with an association degree equal to or more than half the number of cache ways is possible. Cache memory.   When switching to the high-reliability mode and using one of the two adjacent cache lines in the failed memory cell block, even-numbered cache way memory cell blocks are assigned even-numbered cache lines. 3. The low voltage operation cache memory according to claim 2, wherein an odd index cache line is assigned in the case of an odd numbered cache way memory cell block.   When switching to the high-reliability mode and using one of two adjacent cache lines in a failed memory cell block, an odd-numbered cache way memory cell block is assigned an odd index cache line. 3. The low-voltage operation cache memory according to claim 2, wherein even-numbered cache lines are assigned to odd-numbered cache way memory cell blocks.   In a failed memory cell block, when switching to the high reliability mode and using one of the two adjacent cache lines, the number of cache ways is N (numbers are 0, 1,..., N−1). In the case of a cache way memory cell block with a number less than N / 2, an even index cache line is assigned, and in the case of a cache way memory cell block with a number greater than or equal to N / 2, an odd index is assigned. 3. The low voltage operation cache memory according to claim 2, wherein the cache line is assigned.   In a failed memory cell block, when switching to the high reliability mode and using one of the two adjacent cache lines, the number of cache ways is N (numbers are 0, 1,..., N−1). In the case of a cache way memory cell block having a number less than N / 2, an odd index cache line is allocated, and in the case of a cache way memory cell block having a number of N / 2 or more, an even index is assigned. 3. The low voltage operation cache memory according to claim 2, wherein the cache line is assigned. In a failed memory cell block,
In high reliability mode,
As identification information of which of the two adjacent cache lines is used,
7. The low-voltage operation cache memory according to claim 1, wherein a cache line state bit of an invalid cache line that is not used is set to {Valid bit, Dirty bit} = {0, 1}. In cache memory LRU (Least Recently Used) replacement algorithm,
When the failed memory cell block is in high reliability mode,
8. The low-voltage operation cache memory according to claim 1, wherein an LRU tree bit of an invalid cache line that is not used is fixed to an MRU (Most Recently Used) state. In cache memory LRU (Least Recently Used) replacement algorithm,
When the failed memory cell block is in high reliability mode,
If there are M invalid cache lines that are not used,
8. The low voltage operation according to claim 1, wherein LRU tree bits of invalid cache lines not used are set to 0 (MRU), 1,..., M-1 in the order of cache way numbers. Cache memory. If there are M invalid cache lines that are not used,
Let M be the LRU tree bit of the cache line of the new data allocated when a cache miss occurs,
10. The low-voltage operation cache memory according to claim 8, wherein the LRU tree bits of other cache lines to be used are incremented by 1 in order from M + 1 according to the order before a cache miss occurs. If there are M invalid cache lines that are not used,
The LRU tree bit of the cache line where the cache hit occurred is M,
10. The low-voltage operation cache memory according to claim 8, wherein the LRU tree bits of other cache lines to be used are incremented by 1 in order from M + 1 according to the order before a cache miss occurs.