JP6032908B2 - Power supply device and image forming apparatus having power supply device - Google Patents

Description

  The present invention relates to a current resonance type switching power supply device.

  FIG. 7A shows a circuit configuration diagram of a conventional current resonance type switching power supply device. In FIG. 7A, the full wave rectification circuit 2 outputs a voltage obtained by full wave rectification of the AC voltage input from the commercial AC power supply 1 to the smoothing capacitor 3. The smoothing capacitor 3 obtains a DC voltage Vdc by smoothing the voltage that has been full-wave rectified by the full-wave rectifier circuit 2.

  At both ends of the smoothing capacitor 3, for example, switching elements 8 and 9 (hereinafter referred to as a high-side FET 8 and a switching element 9 as a low-side FET 9) such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) are used. A series circuit is connected. A transformer 11 is connected in parallel to the low-side FET 9. A winding on the primary side of the transformer 11 (also referred to as a primary winding) is equivalently represented by an excitation inductance 12 and a leakage inductance 13, and the leakage inductance 13 and the current resonance capacitor 14 constitute a series resonance circuit. In addition, as the leakage inductance 13, there is a configuration in which an inductance is provided separately from the transformer 11. A voltage resonant capacitor 10 is connected in parallel to the low-side FET 9.

  The secondary winding (also referred to as secondary winding) of the transformer 11 is wound in two phases, one is wound so that a voltage in phase with the primary winding is generated, and the other is the primary winding. It is wound so as to generate a reverse-phase voltage. The secondary winding of the transformer 11 is connected to a rectifying / smoothing circuit including a diode 15 </ b> A, a diode 15 </ b> B, and a smoothing capacitor 16. Note that the load resistor 17 connected to the smoothing rectifier circuit represents a load. The rectifying / smoothing circuit connected to the secondary winding loads the DC output voltage Vout by full-wave rectifying and smoothing the voltage induced in the secondary winding of the transformer 11 (pulse voltage controlled on / off). Output to the resistor 17.

  The DC output voltage Vout branches and is also input to the error amplifier in the shunt regulator 19. The error amplifier compares the value of the DC output voltage Vout with the reference voltage value and supplies an error signal corresponding to the error to the photocoupler. The photocoupler 21 feeds back an error signal from the secondary side to the primary side while maintaining insulation between the primary side and the secondary side. In addition, the resistor 20 is provided to limit the current that flows to the photodiode that is the light emitting element of the photocoupler 21.

  The oscillation frequency of an oscillator (not shown) built in the control circuit 7 changes depending on the magnitude of the current that flows to the phototransistor that is a light receiving element of the photocoupler 21 and is input to the control circuit 7. As the oscillation frequency changes, the switching frequency of the high-side FET 8 and the low-side FET 9 changes, and the amount of energy transmitted from the primary side to the secondary side also changes. As a result, the value of the secondary side DC output voltage Vout is variably controlled. Further, the control circuit 7 applies a voltage to each gate terminal of the high-side FET 8 and the low-side FET 9 so that the FETs are not turned on at the same time (also referred to as dead time), and the high-side FET 8 and the low-side FET 9 Are alternately turned on / off.

  In such a switching power supply device, when the value of the DC output voltage Vout on the secondary side is lowered, the switching frequency is controlled to be lowered. This increases the amount of energy transmitted to the secondary side. Conversely, when the value of the DC output voltage Vout on the secondary side increases, the switching frequency is controlled to be increased so that the amount of energy transmission to the secondary side is reduced.

  FIG. 7B shows details of a portion constituting the primary side resonance circuit of the switching power supply in FIG. In FIG. 7B, D1 is a body diode of the high-side FET 8, and D2 is a body diode of the low-side FET 9. FIG. 8 shows an operation waveform of the resonance circuit of FIG. 7B, where VQ1gs is a gate signal for driving the high-side FET 8, VQ2gs is a gate signal for driving the low-side FET 9, and IQ1 is The current flowing through the high-side FET 8, IQ 2 is the current flowing through the low-side FET 9, Ires is the current flowing through the resonance circuit, and Vcr is the voltage across the resonance capacitor 14.

  The steady operation (operation in a stable state) of the resonance circuit will be described with reference to FIG. First, in the period A (the high-side FET 8 is on and the low-side FET 9 is off), a current flows through the path of the high-side FET 8 → the leakage inductance 13 → the current resonance capacitor 14. Energy is stored in the current resonance capacitor 14 via the excitation inductance 12 and the leakage inductance 13 of the primary winding of the transformer 11, and the voltage of the current resonance capacitor 14 rises.

  Next, in the dead time period B (when both the high-side FET 8 and the low-side FET 9 are off), the current flows through the path of the body diode D2 → the leakage inductance 13 → the current resonance capacitor 14 of the low-side FET 9. Zero-volt switching (also referred to as ZVS: Zero Voltage Switching) is realized by turning on the low-side FET 9 while a current is flowing through the diode D2.

  Next, during the period C (the high-side FET 8 is off and the low-side FET 9 is on), the charging of the current resonance capacitor 14 continues, and when the energy stored in the leakage inductance 13 is released, the direction of the resonance current Changes, and a current flows through the path of the current resonance capacitor 14 → the leakage inductance 13 → the low-side FET 9. At this time, the voltage of the current resonance capacitor 14 decreases.

  Next, in the dead time period D (FETs 8 and 9 are both off), the current flows through the path of the current resonance capacitor 14 → leakage inductance 13 → D 1. ZVS is realized by turning on the high-side FET 8 in a state where a current flows through D1. As described above, in a steady state, the switching frequency of the high-side FET 8 and the low-side FET 9 is variably controlled while performing the resonance operation of the leakage inductance 13 and the current resonance capacitor 14, thereby being applied to the primary winding of the transformer 11. The amount of energy (electric power) transmitted to the secondary side is controlled by changing the voltage.

  Next, the control of the dead time period B and the period D will be described. Conventionally, the dead time is fixedly set, and as described above, in order to realize ZVS, it is necessary to allow a current to flow through the body diode of the FET during the dead time period. Conventionally, the dead time is set to be sufficiently long in consideration of variations in circuit elements and an output range.

  However, if the dead time period is long, the FET cannot be turned on during that period, so there is a possibility that the time for supplying energy to the resonance circuit is not sufficient. As a result, there is a concern that the efficiency of the resonant circuit is reduced. Further, when a transformer or a capacitor is miniaturized as such a switching power supply, a method of increasing the switching frequency can be considered. When attempting to increase the frequency of a current resonance type switching power supply, if the length of the dead time is long, there is a limit to the increase in frequency depending on that.

  Patent Document 1 has been proposed as a method for solving such a problem. In the switching power supply device of Patent Document 1, after the control circuit 7 detects that a current flows through the body diode of the FET that is a switching element, the FET that is different from the FET in which the current flows through the body diode is turned on. To control. As a method for detecting that a current has passed through the body diode, a method for measuring the potential difference between the drain and source of the FET is employed. Thus, the dead time period is shortened and ZVS is realized.

JP 2005-198457 A

  However, the switching power supply device of Patent Document 1 is configured to end the dead time period after the current flows through the body diode. Further, if the transformer or the capacitor is further downsized to increase the switching frequency, the dead time is reduced. There is a limit to further shortening the period.

On the other hand, in order to supply power to the resonance circuit, the high side FET needs to be turned on. However, when the frequency is increased with the dead time period kept constant, the ratio of the time for turning on the high side FET is Decrease.
Therefore, there is a problem that sufficient output cannot be obtained with higher frequency.

A power supply apparatus for solving the above-described problems includes a transformer, a first switching element and a second switching element connected in series, and a driving means connected in parallel to a primary side of the transformer, and the driving means Rectifying and smoothing means for rectifying and smoothing the voltage output from the secondary side of the transformer by driving, and according to the output from the rectifying and smoothing means, the first switching element and the second switching element are A dead time is set so that both the first switching element and the second switching element are turned off before the second switching element is turned on after the first switching element is turned on. In addition, after the second switching element is turned on, the dead time is provided until the first switching element is turned on. A control means for outputting a signal for driving the urchin said driving means, said control means, the displacement of the voltage at the midpoint of said first switching element and the second switching element is connected The detected displacement amount is compared with a threshold value, and the dead time is set based on the comparison result .

The image forming apparatus of the present invention is an image forming apparatus that forms an image on a recording material, and includes a controller that controls an image forming operation and a power source that supplies power to the controller. When, having a first switching element and a second switching element connected in series, and a drive means connected in parallel to the primary side of the transformer, the secondary side of the transformer by the driving means is driven Rectifying / smoothing means for rectifying and smoothing the voltage output from the first switching element and the second switching element are alternately turned on in accordance with the output from the rectifying / smoothing means , and the first After the switching element is turned on, both the first switching element and the second switching element are turned off before the second switching element is turned on. To provide a Dotaimu, and, after the second switching element is turned on, and a control means for outputting a signal for driving the driving means so as to provide the dead time until the first switching element is turned on The control means detects a displacement amount of a voltage at a middle point where the first switching element and the second switching element are connected, compares the detected displacement amount with a threshold value, and compares the result. The dead time is set based on the above .

  As described above, according to the present invention, in the current resonance type switching power supply device, the switching frequency can be further increased by using a small transformer or capacitor, and the switching power supply device can be further downsized. Can do.

Power supply circuit of embodiment 1 Characteristics of operation waveform and dead time period of power supply circuit of embodiment 1 Power supply circuit of embodiment 2 Characteristics of Operation Waveform and Threshold of Power Supply Circuit of Embodiment 2 Control circuit of embodiment 3 Characteristics of Operation Waveform and Threshold Value of Power Supply Circuit of Embodiment 3 Conventional power circuit Waveform of conventional power circuit The figure which shows the example of application of the power supply of this invention

  Hereinafter, specific configurations of the present invention for solving the above-described problems will be described based on the following examples. In addition, the Example shown below is an example, Comprising: It is not the meaning which limits the technical scope of this invention only to them.

Example 1
The configuration and operation of the first embodiment will be described below with reference to FIG. FIG. 1A shows a half-bridge current resonance type switching power supply device. In FIG. 1A, the AC voltage input from commercial AC power supply 1 to full-wave rectified by full-wave rectifier circuit 2 is output to smoothing capacitor 3. The smoothing capacitor 3 smoothes the full-wave rectified voltage to obtain a DC voltage Vdc.

  A control circuit 7 controls the switching frequency, and controls the frequency for driving the first switching element 8 and the second switching 9 according to the signal input from the photocoupler 21. The switching elements 8 and 9 are connected in series to perform switching operations alternately, are connected to the primary side of the insulating transformer 11, and drive the primary side. In this embodiment, a MOSFET is employed. Hereinafter, the MOSFET 8 is referred to as a high side FET 8 and the MOSFET 9 is referred to as a low side FET 9. A capacitor 10 is connected to the drain terminal and the source terminal of the low-side FET 9 and is a voltage resonance capacitor.

  Reference numeral 11 denotes an insulating transformer, which is represented by an equivalent circuit of an excitation inductance 12 and a leakage inductance 13. The current resonance capacitor 14 and the leakage inductance 13 constitute a series resonance circuit. 15A and 15B are diodes for rectifying the voltage generated in the secondary winding (secondary winding) of the transformer, and 16 is a capacitor for smoothing the voltage rectified by the diodes 15A and 15B. The diodes 15A and 15B and the capacitor 16 constitute a rectifying / smoothing circuit. Reference numeral 17 denotes a load resistance.

  Reference numeral 19 denotes a shunt regulator that internally compares the reference voltage with the output voltage from the secondary side and outputs a current corresponding to the error in the comparison result. Reference numeral 21 denotes a photocoupler which transmits an error signal output from the shunt regulator 19 to the primary side control circuit 7 as feedback information.

  FIG. 1B shows a block diagram of the control circuit 7. The gate driver 31 drives the gates of the high-side FET 8 and the low-side FET 9 by the output unit 37 based on the output of the oscillator 32. The output unit 37 turns on, for example, the gate of the high-side FET 8 while the output of the oscillator 32 is at a high level. The oscillator 32 changes the oscillation frequency based on feedback information from the photocoupler 21. The determination unit 33 detects the frequency of the oscillator 32 and sets a dead time period corresponding to the detected frequency by the dead time setting unit 34.

  When the output from the oscillator 32 becomes low level, the determination unit 33 calculates the oscillation frequency from the time when the immediately preceding oscillator 32 is at high level. The dead time setting unit 34 sets the dead time period in the timer 35 according to the oscillation frequency calculated by the determination unit 33. When the set time elapses, the timer 35 switches the output of the output unit 37 from the high side to the low side by the switching unit 36 and restarts the oscillator. When a high level is output from the oscillator 32, the gate of the low-side FET 9 is turned on. The gate of the low-side FET 9 is turned off when the output of the oscillator 32 becomes low level.

  By repeating the above operation, the dead time period corresponding to the oscillation frequency can be set flexibly.

  Next, the operation of the circuit shown in FIG. 1 will be described with reference to the timing chart shown in FIG. The timing chart in FIG. 2A shows waveforms in a steady state (stable operation state), and describes two cases with different driving frequencies.

  VQ1gs and VQ2gs represent gate drive voltages of the high-side FET 8 and the low-side FET 9, respectively. IQ1 and IQ2 represent drain currents of the high-side FET and the low-side FET, respectively. Ires indicates a resonance current flowing in the resonance circuit. Hereinafter, the operation will be described in time series.

  First, at time E, the control circuit 7 turns on the high-side FET 8 and turns off the low-side FET 9. The control circuit 7 maintains this switch state during the period from time E to time F by the oscillator 32 according to the feedback information of the photocoupler 21.

  When the output of the oscillator 32 becomes low level at time F, the determination unit 33 calculates the time until the output of the oscillator becomes low level, that is, the time from time E to time F. The determination unit 33 outputs the calculated value to the dead time setting unit 34. The dead time setting unit 34 sets a dead time period in the timer 35 according to the time from time E to time F. The timer 35 maintains the switch state until the set dead time elapses.

  At time G, the dead time period set in the timer 35 elapses, and the timer 35 switches the output of the output unit 37 from the high side to the low side by the switching unit 36. The switching unit 36 outputs an oscillation start signal to the oscillator 32. Accordingly, the output of the oscillator 32 becomes high level, and the gate of the low-side FET 9 is turned on via the output unit 37.

  The determination unit 33 maintains the switch state for a period from time G to time H until the output of the oscillator 32 becomes low level. When the output of the oscillator 32 becomes low level at time H, the determination unit 33 calculates the time from time G to time H. The determination unit 33 outputs the calculated value to the dead time setting unit 34. The dead time setting unit 34 sets a dead time period in the timer 35 according to the time from time G to time H. The timer 35 maintains the switch state until the set dead time elapses.

  At time I, the dead time period set in the timer 35 elapses, and the timer 35 switches the output of the output unit 37 from the low side to the high side by the switching unit 36. The switching unit 36 outputs an oscillation start signal to the oscillator 32. Along with this, the output of the oscillator 32 becomes high level, and the gate of the high side FET 8 is turned on via the output unit 37.

  Here, assuming that the dead time period when the switching frequency is low is TL and the dead time period when the switching frequency is high is TH, the dead time period becomes shorter as the frequency becomes higher, and the switching frequency f and The dead time periods TL and TH have characteristics as shown in FIG. In the characteristic A in FIG. 2, a fixed dead time period is set up to a predetermined frequency fa, and when the frequency exceeds the predetermined frequency fa, it is linearly shortened. Moreover, it is good also as a linear structure in the whole frequency range like the characteristic B. That is, as the drive frequency increases so as to satisfy TL> TH, the dead time period is set to be shorter so that driving at a higher switching frequency is possible.

  As described above, according to this embodiment, the current resonance type switching power supply can be driven at a high frequency. Therefore, the switching power supply device can be reduced in size.

(Example 2)
This embodiment is partially different in circuit configuration from the first embodiment. In addition, since it is the same operation | movement about the structure which overlaps with Example 1, description is abbreviate | omitted about the overlapping structure.

  FIG. 3A shows a circuit configuration of this embodiment, and shows a circuit of a half-bridge current resonance type switching power supply. The difference from the first embodiment is the configuration in which the middle point of the high-side FET 8 and the low-side FET 9 and the control circuit 41 are connected.

  FIG. 3B shows the internal configuration of the control circuit. In FIG. 3B, the timer 42 determines the ON time of the FET according to the feedback signal FB, and outputs a high level when the FET is on and a low level when the FET is off to the output unit 47. The timer 42 starts counting by a signal from the switching unit 46 and outputs a high level, and outputs a low level when the time set in the timer 42 has elapsed.

  When the output from the timer 42 becomes low level, the determination unit 43 sets the threshold value Vth according to the value set in the timer 42. The comparison unit 45 compares the threshold values Vth and Vn. The output from the comparison unit 45 is switched according to the comparison result. The switching unit 46 receives the comparison result of the comparison unit 45, restarts the timer 42, and switches the output from the output unit 47.

  Next, the operation of the circuit configured in FIG. 3 will be described with reference to a timing chart shown in FIG. The timing chart of FIG. 4A shows each waveform in a steady state (a state where the operation is stable), and describes two waveforms having different driving frequencies.

  VQ1gs and VQ2gs represent gate drive voltages of the high-side FET 8 and the low-side FET 9, respectively. IQ1 and IQ2 represent drain currents of the high-side FET 8 and the low-side FET 9, respectively. Ires indicates a resonance current flowing in the resonance circuit. Vn represents a voltage at a midpoint that is a contact point between the high-side FET and the low-side FET. Hereinafter, the operation will be described in time series.

  First, at time J, the control circuit 41 turns on the high-side FET 8 and turns off the low-side FET 9. The control circuit 41 maintains this switch state for a period from time J to time K by the timer 42 according to the feedback information of the photocoupler 21.

  When the output of the timer 42 becomes low level at time K, the output unit 47 sets the gate of the high side FET 8 to low level and turns off the high side FET 8. The determination unit 43 sets the threshold value VthL of the threshold setting unit 44 according to the time set in the timer 42. The comparison unit 45 compares the threshold value VthL set by the threshold value setting unit 44 with the midpoint voltage Vn. Thereafter, the switch state of the high-side FET 8 and the low-side FET 9 is maintained until the threshold VthL and the midpoint voltage Vn match.

  At time L, the comparison unit 45 outputs a low level to the switching unit 46 at the timing when the threshold value VthL and the midpoint voltage Vn match. The switching unit 46 switches the output destination of the output unit 47 to the gate of the low-side FET by switching the signal level. Then, the timer 42 is restarted.

  The timer 42 sets the time corresponding to the feedback signal FB at that time in the timer 42. The timer 42 starts counting and outputs a high level signal to the output unit 47 at the same time. In response to the high level signal, the output unit 47 outputs a high level to the gate of the low-side FET 9. The gate state of the low-side FET 9 is maintained until time M when the time set in the timer 42 elapses.

  When the output of the timer 42 becomes low level at time M, the determination unit 43 sets the threshold value VthH of the threshold setting unit 44 according to the time set in the timer 42. The comparison unit 45 compares the threshold VthH set by the threshold setting unit 44 with the midpoint voltage Vn. Thereafter, the switch state is maintained until VthH and Vn match.

  At time N, a high level is output from the comparison unit 45 to the switching unit 46 at the timing when the threshold value VthL and the midpoint voltage Vn match. The switching unit 46 switches the output destination of the output unit 47 to the gate of the high-side FET 8 by switching the level of the signal from the comparison unit 45. Also, the timer 42 is restarted.

  The timer 42 sets a time corresponding to the feedback signal FB at that time in the timer 42 and starts counting and simultaneously outputs a high level signal to the output unit 47. In response to the high level signal, the output signal of the output unit 47 outputs a high level to the gate of the high side FET 9.

  The threshold voltages VthH and VthL have frequency characteristics as shown in FIG. The threshold voltage VthH has a characteristic that the value decreases as the switching frequency increases. For example, the threshold voltage VthH is constant up to a predetermined frequency fa as in the characteristic C, or linearly decreases from fa, or the frequency as in the characteristic D. The characteristic can be changed linearly over the entire area.

  The threshold voltage VthL is a characteristic that increases as the switching frequency increases. For example, a characteristic that is constant up to a predetermined frequency fb like the characteristic E and linearly increases from fb, or a characteristic that changes linearly over the entire frequency like the characteristic F can be used.

  FIG. 4C shows a chart when the switching frequency is set higher than that in FIG. In FIG. 4C, since VthH2 is lower than VthH1, the dead time period is shortened. Similarly, since VthL2 is higher than VthL1, the dead time period is shortened.

  As described above, according to the present embodiment, the current resonance type switching power supply can be driven at a high frequency. Therefore, the switching power supply device can be reduced in size.

Example 3
Since the present embodiment has a different configuration from the first and second embodiments, and the same configuration and operation as those of the first embodiment are the same as those in the first embodiment, the description thereof will be omitted.

  FIG. 5 shows an internal configuration of the control circuit 50 according to the third embodiment. In FIG. 5, the buffer 51 captures and holds (stores) the midpoint voltage Vn of the high-side FET 8 and the low-side FET 9 according to the output of the timer 52. The value set in the timer 52 is set to a value sufficiently shorter than the resonance period calculated from the resonance capacitor 14 and the leakage inductance 13 of the transformer.

  The storage unit 53 stores the value of the buffer 51 of 51, and stores the midpoint voltage Vn captured once. The difference calculator 54 obtains the difference between the values of the buffer 51 and the storage unit 53. The comparator 56 compares the output value ΔVn of the difference calculator 54 with the value set in the threshold setting unit 55. The value set in the threshold setting unit 55 is determined by the value set in the timer 42.

  The timer 42 determines the FET on time based on the FB signal of the photocoupler 21 and outputs a high level signal when the FET is turned on and a low level signal when the FET is turned off to the output unit 47. The gate driver 31 drives the gates of the high-side FET 8 and the low-side FET 9 by the output unit 47 based on the output of the timer 42. The timer 42 starts counting in response to a signal from the switching unit 46, outputs a high level, and outputs a low level signal when the time set in the timer 42 has elapsed.

  When the output from the timer 42 becomes low level, the determination unit 43 sets the threshold values VthRH and VthRL in the threshold setting unit 55 according to the value set in the timer 42.

  Next, the operation of the circuit of FIG. 5 will be described with reference to the timing chart shown in FIG. The timing chart of FIG. 6 shows each waveform in a steady state (a state in which stable operation is performed), and describes two different driving frequencies.

  VQ1gs and VQ2gs represent gate drive voltages of the high-side FET and the low-side FET, respectively. IQ1 and IQ2 represent drain currents of the high-side FET and the low-side FET. Ires indicates a resonance current flowing in the resonance circuit. Vn represents a midpoint voltage that is a contact point between the high-side FET and the low-side FET. ΔVn represents the amount of voltage displacement per time. Hereinafter, the operation will be described in time series.

  First, at time O, the control circuit 50 turns on the high-side FET 8 and turns off the low-side FET 9. The control circuit 50 maintains this switch state for a period from time O to time P by the timer 42 according to the feedback information of the photocoupler 21.

  When the output of the timer 42 becomes low level at time P, the determination unit 43 sets the threshold value VthRL of the threshold setting unit 55 according to the time set in the timer 42. The comparison unit 45 compares the threshold value VthRL set by the threshold value setting unit 55 with the calculation result ΔVn by the difference calculator. Thereafter, this switch state is maintained until the threshold value VthRL and ΔVn match.

  At time Q, the comparator 56 outputs a low-level signal to the switching unit 46 at the timing when the threshold value VthRL and ΔVn match. The switching unit 46 switches the output destination of the output unit 47 to the gate of the low-side FET 9 when the signal level is switched. Also, the timer 42 is restarted.

  The timer 42 sets a time corresponding to the feedback signal at that time in the timer 42 and starts counting and simultaneously outputs a high level signal to the output unit 47. In response to the high level signal, the output unit 47 outputs a high level signal to the gate of the low-side FET 9. Until the time set in the timer 42 elapses, the output state to the gate of the low-side FET is maintained.

  When the output of the timer 42 becomes low level at time R, the determination unit 43 sets the threshold value VthRH of the threshold setting unit 55 according to the time set in the timer 42. The comparison unit 56 compares the threshold value VthRH set by the threshold value setting unit 55 with the midpoint voltage displacement amount ΔVn. Thereafter, this switch state is maintained until the threshold voltage, VthRH, and ΔVn match.

  At time S, the comparator 56 outputs a high-level signal to the switching unit 46 at the timing when the threshold value VthRL and ΔVn match. The switching unit 46 switches the output destination of the output unit 47 to the gate of the high-side FET 8 when the signal level is switched. Also, the timer 42 is restarted.

  The timer 42 sets a time corresponding to the feedback signal at that time in the timer 42 and starts counting, and at the same time outputs a high level signal to the output unit 47. In response to the high level signal, the output unit 47 outputs a high level signal to the gate of the high side FET 8.

  The threshold values VthRH and VthRL have frequency characteristics as shown in FIG. 6C when one period is from the period O to S. The threshold VthRH is a characteristic that increases as the switching frequency increases. For example, the characteristic V is constant up to the frequency fc as in the characteristic G, and linearly increases from the frequency fc, or changes linearly over the entire frequency as in the characteristic H. It may be the characteristic to be.

  The threshold value VthRL is a characteristic that decreases as the switching frequency increases. For example, a characteristic that is constant up to the frequency fc as in the characteristic I and linearly decreases from fc, or a characteristic that changes linearly in the entire frequency as in the characteristic J may be used.

  FIG. 6C shows a chart when the switching frequency is made higher than that in FIG. In FIG. 6, since the threshold value VthRH2 is higher than the threshold value VthRH1, the dead time period is shortened. Similarly, since the threshold value VthRL1 is lower than the threshold value VthL2, the dead time period is shortened.

  As described above, according to the present embodiment, the current resonance type switching power supply can be driven at a high frequency. Therefore, the switching power supply device can be reduced in size.

(Application example of power supply)
The power supply apparatus described in the above embodiment can be applied as a low-voltage power supply in an image forming apparatus such as a laser beam printer, a copying machine, or a facsimile. The application example will be described below. The power source of the present invention is applied as a power source for power supply to a controller as a control unit in the image forming apparatus and power supply to a motor as a drive unit of a conveyance roller that conveys a sheet as a recording material. .

  FIG. 9A shows a schematic configuration of a laser beam printer which is an example of an image forming apparatus. The laser beam printer 2000 includes a photosensitive drum 2110 as an image carrier on which a latent image is formed as an image forming unit 2100, and a developing unit 2120 that develops the latent image formed on the photosensitive drum with toner. Then, the toner image developed on the photosensitive drum 2110 is transferred to a sheet (not shown) as a recording medium supplied from the cassette 2160, and the toner image transferred to the sheet is fixed and discharged to the tray 2150.

  FIG. 9B shows a power supply line from a power source to a controller as a control unit and a motor as a drive unit of the image forming apparatus. The power source of the present invention can be applied as a power source for supplying power to the controller having the CPU 3100 for controlling such an image forming operation, and a power source for supplying power to the motor 3120 and the motor 3130 as drive units for image formation. As described in the above embodiments, since the power supply device provided in the image forming apparatus can be reduced in size, the image forming apparatus main body can be reduced in size.

DESCRIPTION OF SYMBOLS 1 Commercial power supply 2 Rectifier circuit 3 Smoothing capacitor 6 Comparator 7 Control circuit 8 Switching element (high side FET)
9 Switching element (low-side FET)
DESCRIPTION OF SYMBOLS 10 Capacitor 11 Transformer 12 Excitation inductance 13 Leakage inductance 14 Current resonance capacitor 15 Diode 16 Smoothing capacitor 17 Load resistance 19 Shunt regulator 20 Resistance 21 Photocoupler

Claims (4)

With a transformer,
Drive means having a first switching element and a second switching element connected in series, connected in parallel to the primary side of the transformer;
Rectifying and smoothing means for rectifying and smoothing the voltage output from the secondary side of the transformer by driving the driving means;
According to the output from the rectifying and smoothing means, the first switching element and the second switching element are alternately turned on, and after the first switching element is turned on, the second switching element is turned on. Until the first switching element is turned on after the second switching element is turned on so as to provide a dead time in which both the first switching element and the second switching element are turned off. the and a control means for outputting a signal for driving the driving means so as to provide,
The control means detects a displacement amount of a voltage at a middle point where the first switching element and the second switching element are connected, compares the detected displacement amount with a threshold value, and determines the dead time based on a comparison result. A power supply device characterized by setting. The power supply apparatus according to claim 1 , wherein the control unit switches the threshold value to a larger value as the frequency for driving the driving unit is higher . An image forming apparatus for forming an image on a recording material,
A controller for controlling an image forming operation; and a power source for supplying power to the controller.
The power supply is
A transformer having a first switching element and a second switching element connected in series, connected in parallel to a primary side of the transformer; and the secondary of the transformer by driving the driving means Rectifying and smoothing means for rectifying and smoothing the voltage output from the side;
According to the output from the rectifying and smoothing means, the first switching element and the second switching element are alternately turned on, and after the first switching element is turned on, the second switching element is turned on. Until the first switching element is turned on after the second switching element is turned on so as to provide a dead time in which both the first switching element and the second switching element are turned off. And a control means for outputting a signal for driving the driving means so as to provide a voltage at a middle point where the first switching element and the second switching element are connected. a displacement amount detecting said detected relative displacement amount and the threshold value, and sets the dead time based on the comparison result Image forming apparatus. The image forming apparatus according to claim 3 , wherein the control unit switches the threshold value to a larger value as the frequency for driving the driving unit is higher .

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