JP6041787B2 - Image processing apparatus, image forming apparatus, and drive pulse generation method - Google Patents

Description

  The present invention relates to an image processing apparatus, an image forming apparatus, and a driving pulse generation method for generating a driving pulse for driving an exposure scanning apparatus by sequentially delaying input pixel data.

  An electrophotographic image forming apparatus includes an exposure scanning device that exposes a photosensitive member by irradiating the photosensitive member with a laser beam. The exposure scanning device exposes the photosensitive member by scanning a laser beam corresponding to the image signal in the axial direction of the photosensitive member. Such scanning is also called main scanning, and the scanning amount in one main scanning is called a scanning line.

  The laser beam scanned by the exposure scanning device is generated based on a drive pulse output from a PWM circuit included in the image forming apparatus. Specifically, a drive pulse having a pulse width corresponding to the density of each pixel included in the input image data is generated by a PWM circuit, and a pulse signal obtained by repeatedly turning these drive pulses on and off is exposed. A laser beam corresponding to the pulse signal is generated by being output to the scanning device. Therefore, the laser beam includes information on the density of each pixel in the scanning line. The pulse width (or duty ratio) of the drive pulse per pixel is the beam lighting time per pixel, and this pulse width is the density information per pixel.

  The PWM circuit is provided with a plurality of stages of delay circuits composed of a plurality of delay elements. This PWM circuit detects the number of delay stages per clock in the delay circuit that determines the beam lighting time per pixel, and converts pixel data into the pulse width in accordance with the number of delay stages. On the other hand, it is known that the delay amount (delay capability for each delay element) in the delay element varies depending on the operating environment. Therefore, conventionally, a calibration signal is input to the delay circuit at a timing when image processing is not performed, such as between print jobs, and the delay amount per clock of the delay circuit in the operating environment before main scanning is detected. Thus, the number of delay stages is corrected (Patent Document 1).

JP 2005-153366 A JP 2002-94371 A

  However, the clock signal used in the PWM circuit is affected by jitter and the frequency of the clock signal varies. There is a problem that when the cycle for each clock varies due to the variation in frequency, the number of delay stages per clock also varies. A technique for suppressing the influence of jitter in a clock signal (Patent Document 2) has been proposed in the past, but the problem that the amount of delay varies for each detection due to the influence of jitter cannot be solved.

  An object of the present invention is to provide an image processing apparatus, an image forming apparatus, and a drive pulse generation method capable of reducing the variation in the detected delay amount by suppressing the influence of jitter of the clock signal.

An image processing apparatus according to one aspect of the present invention includes a delay circuit, an input unit, a detection unit, and an adjustment unit. The delay circuit includes a plurality of delay elements that sequentially delay input pixel data and convert the pixel data into drive pulses for driving the exposure scanning apparatus. The input unit inputs the pixel data to one of the delay elements of the delay circuit based on a reference delay stage number determined in accordance with pixel density information included in the pixel data. The detection unit inputs a predetermined calibration signal to the delay circuit a plurality of times during non-image processing , and calculates the delay amount per cycle of the operation clock for each number of times while the calibration signal is delayed and output. To detect. The adjustment unit adjusts the reference delay stage number using an average value of a plurality of delay amounts detected by the detection unit.

  An image forming apparatus according to another aspect of the present invention includes the image processing apparatus.

A drive pulse generation method according to another aspect of the present invention inputs the pixel data to any one of a plurality of delay elements included in a delay circuit based on a reference delay stage number corresponding to the density information of the pixels included in the pixel data. This is a method for generating a drive pulse for driving the exposure scanning apparatus. This drive pulse generation method includes a first step and a second step. In the first step, a predetermined calibration signal is input to the delay circuit a plurality of times during non-image processing , and the delay amount per cycle of the operation clock is output for each number of times while the calibration signal is delayed and output. To detect. In the second step, an average value of a plurality of delay amounts detected in the first step is calculated, and the reference delay stage number is adjusted using the average value.

  According to the present invention, it is possible to reduce the variation in the detected delay amount by suppressing the influence of the jitter of the clock signal.

1 is a diagram illustrating a configuration of an image forming apparatus according to an embodiment of the present invention. FIG. 2 is a top perspective view of a laser exposure apparatus provided in the image forming apparatus shown in FIG. 1. FIG. 2 is a block diagram illustrating a configuration of a control unit included in the image forming apparatus illustrated in FIG. 1. It is a logic circuit diagram which shows the delay chain circuit of the control part shown in FIG. It is a block diagram which shows the delay stage number adjustment part of the control part shown in FIG. It is a graph which shows the experimental measurement value of the dispersion | variation in the correction value in the delay chain circuit of embodiment of this invention, and a detection frequency.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings for understanding of the present invention. The following embodiments are examples embodying the present invention, and do not limit the technical scope of the present invention.

  First, the configuration of an image forming apparatus 10 according to an embodiment of the present invention will be described with reference to FIG.

[Image forming apparatus 10]
FIG. 1 is a schematic diagram showing a configuration of an image forming apparatus 10 (an example of the image forming apparatus of the present invention) according to an embodiment of the present invention. As shown in FIG. 1, the image forming apparatus 10 forms an image on a print sheet based on read image data of a document or image data input from the outside. The image forming apparatus 10 includes a scanner 12 at the top and an electrophotographic image forming unit 14 at the bottom. The specific example of the image forming apparatus 10 according to the embodiment of the present invention has a function of performing image processing on input image data. For example, a printer, a copier, a facsimile, or each of these functions is provided. It is a multifunction machine equipped.

  The image forming unit 14 forms an image on a print sheet based on image data read by the scanner 12 or print data (print job) input from the outside. The image forming unit 14 mainly includes an operation display unit 17, a paper feed tray 16, a transport roller 19, a laser exposure device 11 (an example of an exposure scanning device of the present invention), a transfer device 15, and a fixing device 18. And a control unit 5 for controlling these operations. These components are arranged inside a casing 20 that constitutes a housing of the image forming unit 14. A plurality of printing sheets are held in the sheet feeding tray 16. The laser exposure device 11 exposes the photosensitive member 13 included in the transfer device 15 by irradiating a laser beam. The transfer device 15 transfers the toner image onto the printing paper fed from the paper feed tray 16. The fixing device 18 fixes the toner image transferred to the printing paper on the printing paper. Between the upper part of the casing 20 and the scanner 12, a paper discharge space 21 that is open at the front is formed. A paper discharge tray 23 is provided on the lower surface of the paper discharge space 21. The printing paper fed from the paper feed tray 16 is conveyed by the conveyance roller 19 along the conveyance path 20A provided in the casing 20, and the toner image is transferred to the printing paper by the transfer device 15 in the conveyance process. The The toner image transferred to the printing paper is fixed to the printing paper by being heated and melted when passing through the fixing device 18. The printing paper that has passed through the fixing device 18 is discharged to the paper discharge space 21 and held on the paper discharge tray 23.

As shown in FIG. 2, the laser exposure apparatus 11 includes a housing 25, a semiconductor laser light source 26, a polygon mirror 27, an fθ lens 28, a beam detector 29, a condenser lens 30, and a total reflection mirror 31. And a slit (injection port) 32. The semiconductor laser light source 26 emits a laser beam. The polygon mirror 27 rotates at high speed, reflects the laser beam, and scans in the main scanning direction. The beam detector 29 detects the presence or absence of a laser beam. The condenser lens 30 converts the laser beam into parallel light together with the fθ lens 15. The total reflection mirror 31 changes the optical path of the laser beam that has passed through the condenser lens 17 to a right angle. The slit 32 is formed in the housing 12 and is an exit port that guides the optical path of the laser beam from the total reflection mirror 19 to the irradiation surface of the scanned medium such as the photosensitive member 13.

  In the laser exposure apparatus 11, the polygon mirror 27 rotates at high speed clockwise (in the direction of the arrow in FIG. 2) when viewed from above. Therefore, the laser beam emitted from the semiconductor laser light source 26 is reflected in the direction of the fθ lens 28 by the rotating polygon mirror 27. The laser beam that has passed through the fθ lens 28 then performs main scanning for each line while moving from the right end to the left end of the total reflection mirror 31 in the drawing. As a result, the laser beam reflected by the total reflection mirror 31 is scanned in the same direction as the axial direction of the photosensitive member 13 to expose the photosensitive member 13.

  Further, the side surface of the polygon mirror 27 is constituted by a reflecting surface that forms a polygon (in FIG. 2, a hexagon as an example). Therefore, as the polygon mirror 27 rotates in the clockwise direction, the laser beam is irradiated not only in the scanning area irradiated on the total reflection mirror 31 but also outside the scanning area not irradiated on the total reflection mirror 31. At this time, if the beam detector 29 provided outside the scanning region is irradiated with the laser beam before the main scanning of the photosensitive member 13 is performed, the laser beam is detected by the beam detector 29. The beam detector 29 generates a beam detector signal (hereinafter, referred to as a BD signal or a main scanning synchronization signal) for taking a scanning start timing for each line when the laser beam is irradiated. This BD signal is used to determine the scanning start timing at which the laser exposure device 11 actually starts scanning the photosensitive member 13 with a laser beam. The BD signal is sent to the control unit 5.

  An image forming apparatus 10 shown in FIG. 1 is connected to an information processing apparatus (not shown), and print data (print job) including image data is transmitted from the information processing apparatus. In this case, the control unit 5 performs a process of expanding the image data into a plurality of pixel data for each pixel in the image processing unit 52 described later. Such pixel data is input from the image processing unit 52 to a density adjusting unit 53 described later.

  The control unit 5 is a computer having control devices such as a CPU, a ROM, a RAM, and an EEPROM. The CPU is a processor that executes various arithmetic processes. The ROM is a non-volatile storage unit in which information such as a control program for causing the CPU to execute various processes is stored in advance. The RAM is volatile storage means, and the EEPROM is nonvolatile storage means. The RAM and the EEPROM are used as a temporary storage memory (working area) for various processes executed by the CPU.

  The control unit 5 controls the image forming apparatus 10 in an integrated manner by causing the CPU to execute various control programs stored in advance in the ROM. The control unit 5 may be configured by an electronic circuit such as an integrated circuit (ASIC, DSP). In addition to the control unit 5, an engine control unit for controlling the image forming unit 14 and the like may be provided separately.

  In the present embodiment, the control unit 5 generates, for each pixel data, a driving pulse having a width corresponding to the gradation (density information) for each pixel included in each pixel data constituting the input image data. . Then, the control unit 5 sequentially sends the generated drive pulses to the laser exposure apparatus 11 as an image signal (drive pulse) for driving the semiconductor laser light source 26 shown in FIG. Upon receiving the drive pulse, the laser exposure device 11 modulates (turns on) the semiconductor laser light source 26 for a time corresponding to the pulse width of the drive pulse, thereby exposing the electrostatic latent image of one pixel (dot). An image is formed on the photoreceptor 13. Note that the image signal actually sent to the laser exposure apparatus 11 is a pulse wave signal in which a plurality of the driving pulses corresponding to each pixel are continuous.

  In order to generate the drive pulse, the control unit 5, as shown in FIG. 3, the image processing unit 52, the density adjustment unit 53 (an example of the adjustment unit of the present invention), the edge conversion unit 54, and the pulse generation unit 56. The correction value detection unit 57 (an example of the detection unit of the present invention) is provided. In the present embodiment, these are described as being configured by an electronic circuit such as an integrated circuit (ASIC, DSP). However, the processing of each unit may be executed by the CPU based on a control program. . Hereinafter, each part with which the control part 5 is provided is explained in full detail.

  The image processing unit 52 performs a process of expanding the input image data into a plurality of pixel data for each pixel. The developed pixel data is input to the next density adjustment unit 53.

  Here, in the present embodiment, it is assumed that the maximum exposure time of one pixel on one scanning line corresponds to one period of a so-called dot clock. The basic clock for controlling each unit from the density adjustment unit 53 to the correction value detection unit 57 is 250 MHz. The dot clock uses 50 MHz obtained by dividing the basic clock. That is, the maximum exposure time for one pixel is 20 ns for calculation. The basic clock 250 MHz is input as an operation clock to a later-described delay chain circuit 59 (see FIG. 4) via the PLL circuit 60. At this time, since the operation clock input to the delay chain circuit 59 is affected by jitter of the PLL circuit 60, the frequency and period of the operation clock are not stable. That is, an operation clock whose frequency is varied within a predetermined width is input to the delay chain circuit 59.

  Each pixel data output from the image processing unit 52 is supplied to the density adjustment unit 53. The density adjustment unit 53 adjusts the density of each pixel data to a density according to the characteristics of the image forming apparatus 10, particularly the development characteristics during image formation. The density adjusting unit 53 holds a look-up table that indicates the correspondence relationship regarding the density before and after the adjustment, and adjusts the density based on the look-up table. Further, the density adjusting unit 53 determines the rising edge and falling edge position (pulse width or duty ratio) of the drive pulse based on the number of delay stages in the delay chain circuit 59 described later according to the adjusted density. Convert to the unit of the number of delay stages per dot clock.

  As shown in FIG. 5, in the present embodiment, the density adjustment unit 53 includes a delay stage number calculation unit 53A. The delay stage number calculation unit 53A calculates the delay stage number corresponding to the adjusted density so that the pulse width or duty ratio of the drive pulse corresponds to the adjusted density. In other words, the delay stage number calculation unit 53A delays the pixel data in the delay chain circuit 59 so that a drive pulse having a pulse width indicating the density is generated by the delay chain circuit 59 based on the density of the pixel data. The number of delay stages to be propagated (position where pixel data is input) is calculated. As a calculation method, the delay stage number calculation unit 53A has a lookup table in which the number of delay stages corresponding to each density is determined, and extracts the delay stage number corresponding to the density of the adjusted pixel data from the lookup table. The method to do is adopted. The number of delay stages calculated in this way is the number of pixel data that passes through the delay elements, and corresponds to the reference delay stage number of the present invention. The number of delay stages is an element that determines which delay element is used to input pixel data. Therefore, the density adjustment unit 53 performs a process of determining the input position of pixel data in a delay chain circuit 59 described later. It can be said that it is a part to do.

  The density adjusting unit 53 is an example of the adjusting unit of the present invention, and adjusts the delay stage number calculated by the delay stage number calculating unit 53A. In the present embodiment, as shown in FIG. 5, the density adjustment unit 53 includes an averaging unit 53B and a correction unit 53C.

  The averaging unit 53B calculates an average value of a plurality of correction values (corresponding to the correction amount of the present invention) detected by a correction value detection unit 57 described later. For example, the averaging unit 53B receives the correction value fed back from the correction value detection unit 57, and calculates the average value of all received correction values on the condition that the number of times of reception has reached a predetermined number of times. calculate. Thereafter, the averaged correction value is output to the correction unit 53C.

  When the correction unit 53C receives the average correction value input from the averaging unit 53B, the correction unit 53C corrects the delay stage number calculated by the delay stage number calculation unit 53A based on the average correction value. That is, the input position of pixel data (the input position in the delay chain circuit 59) specified by the number of delay stages is corrected. For example, the correction unit 53C stores the average correction value when the previous correction is performed, and the average correction value input from the averaging unit 53B is larger than the previous average correction value (the delay amount is large). In addition, correction is performed to shift the input position in a direction to increase the number of delay delay stages. On the other hand, when the average correction value input from the averaging unit 53B is smaller than the previous average correction value (the delay amount is small), the correction unit 53C sets the input position in a direction to decrease the number of delay delay stages. Perform shift correction.

  As described above, the density adjustment unit 53 adjusts (corrects) the number of delay stages using the average correction value that is the average value of the plurality of correction values detected by the correction value detection unit 57. Then, the pixel data together with the adjusted number of delay stages is output to the pulse generator 56 via the edge converter 54. By adjusting the number of delay stages, even if the delay speed of the delay chain circuit 59, that is, the number of delay stages per operation clock fluctuates due to the influence of jitter of the operation clock, feedback is performed as described above. The number of delay stages is adjusted (corrected) by an average correction value obtained from a plurality of correction values. Therefore, it is possible to obtain the number of delay stages that is hardly affected by the jitter of the operation clock. As a result, it is possible to generate a drive pulse that matches the image data. Further, by adjusting (correcting) the number of delay stages by this method, even when the number of delay stages varies due to changes in the operating environment (such as ambient temperature and humidity), the influence of the change in the operating environment is also affected. It is possible to obtain the number of delay stages that hardly receives. Note that the above-described adjustment does not necessarily have to be performed by the density adjustment unit 53, and is a stage before being input to the delay chain circuit 59 of the pulse generation unit 56, for example, an edge conversion unit 54 or a pulse generation unit described later. 56 may be performed.

  The edge conversion unit 54 compares adjacent pixels on one scanning line based on a plurality of input pixel data, and when originally continuous pixels have the same falling and rising edge positions, For example, a process of continuously connecting the pixels is performed.

  The pulse generator 56 includes a delay chain circuit 59 (an example of the delay circuit of the present invention) shown in FIG. The delay chain circuit 59 includes a plurality of delay elements that sequentially delay input pixel data and convert the pixel data into the drive pulses that drive the laser exposure apparatus 11. Each delay element is a delay circuit arranged in order from the most downstream most downstream delay element (delay element 200_0 in FIG. 4) to the most upstream most delay element (delay element 200_127 in FIG. 4). The delay chain circuit 59 will be described later.

  The pulse generation unit 56 is an example of the input unit of the present invention, and the pixel is based on the number of delay stages (the number of delay stages input from the density adjustment unit 53) according to the density of the pixels included in the pixel data. Data is input to any delay element 200 — n (n = 0 to 127) included in the delay chain circuit 59.

  The delay chain circuit 59 outputs a drive pulse (image signal) having a pulse width corresponding to the density of the pixel data to the laser drive voltage generator 11A based on the input. The precursor driving pulse is converted into a pulse having voltage capability and current capability for causing the semiconductor laser light source 26 to emit light by the laser driving voltage generation unit 11A, and is supplied to the laser exposure apparatus 11 (see FIGS. 1 and 2). Corresponding exposure is performed. Note that the laser drive voltage generation unit 11A and the laser exposure apparatus 11 are not included in the control unit 5, and are illustrated by broken lines in FIG. Of course, the controller 5 may include the laser drive voltage generator 11A.

  The correction value detection unit 57 detects a correction value for correcting the delay step number calculated by the delay step number calculation unit 53A of the density adjustment unit 53. Specifically, when a calibration signal is input to the input buffer 202 of the delay chain circuit 59 a plurality of times in response to a command from the CPU of the control unit 5, the calibration signal is delayed and propagated through the delay chain circuit 59 and output. In the meantime, the number of delay stages per cycle of the operation clock is detected as the correction value every number of times (the number of calibration signal inputs). That is, the correction value is represented by the number of delay elements (the number of delay stages) that the calibration signal has passed from when the calibration signal is input to the delay chain circuit 59 until one cycle of the operation clock elapses.

  Detection of a plurality of correction values in the correction value detection unit 57 is performed by continuously inputting the calibration signal a plurality of times during non-image processing where image processing is not performed. Here, the number of times the calibration signal is input may be two or more. The non-image processing time is a timing when the delay chain circuit 59 is not used for generating the drive pulse. Specifically, for example, when the image forming apparatus 10 is in a standby state, or when the image processing is not performed, such as a processing interval between processing of print data and processing of the next print data. Further, the image processing operation is interrupted when a predetermined condition is satisfied, for example, a predetermined number of images have been formed or a predetermined time has elapsed, and the calibration signal is input to the pulse generator 56. It may be.

  In this embodiment, every time the calibration signal is input to the input buffer 202 during non-image processing, the density adjustment unit 53 detects a correction value for adjusting (correcting) the number of delay stages. The correction value detection unit 57 detects the number of delay elements (the number of delay stages) when the calibration signal is output between the input of the calibration signal and the lapse of the operation clock as a correction value. The correction value is fed back to the density adjustment unit 53 each time it is detected, and the number of delay stages per operation clock calculated by the delay stage number calculation unit 53A before main scanning by the laser exposure apparatus 11 is started. Is corrected by an average correction value which is an average value of a plurality of correction values.

  In the present embodiment, as described above, the density adjustment unit 53 feeds back a plurality of the correction values to the density adjustment unit 53. However, since the density adjustment unit 53 processes the dot clock unit, Processing to replace the number of delay stages of the calibration signal with the number of delay stages per dot clock is performed. For example, in this embodiment, as shown in FIG. 4, the total number of delay stages of the delay chain circuit 59 is 128, and the delay time when no jitter occurs in the operation clock is, for example, 0.1 ns per stage. I am using something. Therefore, the number of delay stages per operation clock generated at 250 MHz is 40. As described above, since the frequency of the dot clock is 50 MHz, the number of delay stages per dot clock is 200. Since the maximum density is obtained when fully exposed during one dot clock, the maximum density is 200 in terms of the number of delay stages. Further, the minimum density is 0 when replaced with the delay stage number unit.

  Next, the delay chain circuit 59 will be described with reference to FIG. FIG. 4 is a logic circuit diagram of the delay chain circuit 59. In the upper part of FIG. 4, 128 D-type flip-flops (hereinafter referred to as flip-flops) 100_0 to 100_127 are connected as illustrated. Let a specific flip-flop be 100_n. Pixel data and an operation clock are input to the flip-flops 100_0 to 100_127 from terminals illustrated in the drawing. The operation clock is a clock signal obtained by inputting a basic clock (250 MHz) generated by an oscillation circuit (clock generation circuit) using a crystal resonator to the PLL circuit 60, and is input to the flip-flop 100_n. Therefore, the frequency of the operation clock varies under the influence of the jitter of the PLL circuit 60, and the clock cycle varies. Further, when a signal is input to a clear terminal (not shown), the flip-flops 100_0 to 100_127 are cleared. The flip lip 100_127 side is referred to as upstream, and the flip lip 100_0 side is referred to as downstream.

  In the middle stage of FIG. 4, 128 EX-NOR circuits 200_0 to 200_127 are connected as shown. A specific EX-NOR circuit is set to 200_n. Each EX-NOR circuit is an example of the delay element of the present invention. The EX-NOR circuit 200_n has one input terminal connected to the output terminal of the flip-flop 100_n, and the other input terminal connected to the upstream (right adjacent to FIG. 4) output terminal of the EX-NOR circuit 200_n + 1. Has been. The EX-NOR circuit 200_127 side is referred to as upstream, and the EX-NOR circuit 200_0 side is referred to as downstream.

  In the lower part of FIG. 4, 128 D-type flip-flops (hereinafter referred to as flip-flops) 300_0 to 300_127 are connected as illustrated. A specific flip-flop is assumed to be 300_n. Data and the operation clock are input to the flip-flops 300_0 to 300_127 from terminals shown in the drawing, respectively. Further, when a signal is input to a clear terminal (not shown), the flip-flops 300_0 to 300_127 are cleared. The flip lip 300_127 side is referred to as upstream, and the flip lip 300_0 side is referred to as downstream.

  An input buffer 202 is provided on the upstream side of the EX-NOR circuit, and an output terminal thereof is connected to the other input terminal of the EX-NOR circuit 200_127. The calibration signal is input to the input buffer 202. An output buffer 201 is provided on the downstream side of the EX-NOR circuit, and its input terminal is connected to the output terminal of the EX-NOR circuit 200_0. Further, from the output terminal of the output buffer 201, when scanning is performed based on pixel data, a driving pulse (image signal) for causing the semiconductor laser light source 26 to emit light is output to the laser driving voltage generator 11A. Is done.

  The 128 flip-flops 100_0 to 100_127 receive the pixel data from the pulse generation unit 56, pass the pixel data to the EX-NOR circuits 200_0 to 200_127, generate a predetermined delay, and output the drive pulse from the output buffer 201. . The 128 flip-flops 300_0 to 300_127 read and output a state in which the calibration signal input to the input buffer 202 is delayed and propagated through the EX-NOR circuits 200_0 to 200_127 from upstream to downstream. The output result is supplied to a density adjusting unit 53 described later and used for correcting (changing) the number of delay stages.

  In the image forming apparatus 10 described above, the control unit 5 determines an input position (a delay element for inputting pixel data) for inputting pixel data by the following method (driving pulse generation method). That is, the control unit 5 first inputs the calibration signal to the input buffer 202 of the delay chain circuit 59 a plurality of times during non-image processing, and outputs the operation clock while the calibration signal is delayed and output. The correction value per one cycle is detected by the correction value detector 57 for each number of inputs (first step). Then, an average value of the plurality of detected correction values is calculated, and the average correction value is used to adjust (correct) the delay stage number calculated by the delay stage number calculation unit 53A in the correction unit 53C (second). Step).

  As described above, in the image forming apparatus 10 of the present embodiment, a plurality of correction values detected by the correction value detection unit 57 are fed back to the density adjustment unit 53, and the density adjustment unit 53 feeds back the plurality of feedback values. The delay stage number calculated by the delay stage number calculation unit 53A is corrected by an average correction value that is an average value of the correction values. As a result, even if the operation clock is affected by the jitter of the PLL circuit 60, the difference from the correction value when there is no influence of the jitter is reduced, thereby reducing variations in the detected correction value. Can do. Thereby, the influence of the jitter of the PLL circuit 60 is suppressed, and the density adjusting unit 53 can correct the number of delay stages and shift the input position of the pixel data to the input position indicated by the corrected number of delay stages. As a result, a stable drive pulse can be generated and output to the laser drive voltage generator 11A, and a stable high-quality image can be formed.

  In the above-described embodiment, the example in which all of the plurality of correction values detected by the correction value detection unit 57 are averaged by the averaging unit 53B of the density adjustment unit 53 has been described, but the present invention is not limited to this. . For example, in the delay chain circuit 59 in the above-described embodiment, as shown in FIG. 6, the operation clock affected by the jitter of the PLL circuit 60 with respect to the basic clock having a frequency of 250 MHz and a period of 4.0 nS. It has been experimentally obtained that the period of fluctuates within a range of 3.5 nS to 4.5 nS, and a correction value (= delay stage number 40 stages) corresponding to 4.0 nS which is the center period of the range. There is an experimental result in which the detection frequency is the highest and the detection frequency of the correction value decreases as it deviates from the center period (away from the horizontal axis). Here, the vertical axis in FIG. 6 indicates the detection frequency of the correction value, and the horizontal axis indicates the frequency and period of the operation clock and the correction value at the time of the operation clock. In this case, the density adjustment unit 53 corrects more than a predetermined upper limit reference value [40 + α] level (corresponding to the upper limit reference value of the present invention) among the plurality of correction values detected by the correction value detection unit 57. The average correction value is obtained by excluding the value and the correction value of a predetermined lower limit reference value [40-α] or less, and the number of delay stages is adjusted (corrected) using the average correction value. Also good. Thereby, the variation in the number of delay stages after adjustment can be further reduced. The upper limit reference value [40 + α] and the lower limit reference value [40−α] are appropriately determined depending on the characteristics of the delay chain circuit 59 and the like.

  In the above-described embodiment, the image forming apparatus 10 including the control unit 5 is illustrated as the image forming apparatus of the present invention, but the present invention is not limited to this. For example, the present invention can be understood as an image processing apparatus that includes the control unit 5 and performs image processing on input image data.

  The present invention can also be understood as a drive pulse generation method applied to the image forming apparatus or the image processing apparatus. That is, according to the present invention, the beam exposure apparatus 11 is driven by inputting the pixel data to one of a plurality of delay elements provided in the delay chain circuit 59 based on the number of delay stages according to the density information of the pixels included in the pixel data. A drive pulse generation method for generating a drive pulse to be generated, which can be regarded as a drive pulse generation method including the first step and the second step.

DESCRIPTION OF SYMBOLS 10: Image forming apparatus 5: Control part 11: Laser exposure apparatus 29: Beam detector 52: Image processing part 53: Delay stage number adjustment part 53A: Delay stage number calculation part 53B: Average part 53C: Correction part 54: Edge conversion part 56 : Pulse generator 57: Correction value detector 59: Delay chain circuit 60: PLL circuit

Claims (4)

A delay circuit composed of a plurality of delay elements that sequentially convert the input pixel data into drive pulses for driving the exposure scanning apparatus, and a reference delay stage number determined according to the density information of the pixels included in the pixel data An input unit for inputting the pixel data to any one of the delay elements based on the delay circuit,
A detection unit that inputs a predetermined calibration signal into the delay circuit a plurality of times during non-image processing , and detects the delay amount per cycle of the operation clock for each number of times while the calibration signal is delayed and output; ,
An adjustment unit that adjusts the reference delay stage number using an average value of a plurality of delay amounts detected by the detection unit.   The adjustment unit obtains an average value except for a delay amount equal to or higher than a predetermined upper limit reference value and a delay amount equal to or lower than a predetermined lower limit reference value among the plurality of delay amounts detected by the detection unit, The image processing apparatus according to claim 1, wherein the reference delay stage number is adjusted using the average value.   An image forming apparatus comprising the image processing apparatus according to claim 1. A driving pulse for generating a driving pulse for driving the exposure scanning apparatus by inputting the pixel data to any one of a plurality of delay elements provided in the delay circuit based on a reference delay stage number corresponding to the density information of the pixel included in the pixel data. A generation method,
A first step of inputting a predetermined calibration signal to the delay circuit a plurality of times during non-image processing , and detecting a delay amount per cycle of the operation clock for each number of times while the calibration signal is delayed and propagated When,
A drive pulse generation method comprising: a second step of calculating an average value of a plurality of delay amounts detected in the first step and adjusting the reference delay stage number using the average value.

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