JP6043118B2 - Semiconductor device manufacturing method and semiconductor wafer - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to performing alignment using alignment marks provided at predetermined positions on a semiconductor wafer.

  In a semiconductor device, a circuit pattern is formed by repeating exposure and etching and overlapping a plurality of layers. For this reason, it is necessary to superimpose each layer accurately, and a pattern called an alignment mark is formed on a semiconductor wafer and used for alignment (alignment) of each layer.

  The alignment mark may be used for the purpose of inspecting desired superposition and etching accuracy. Alignment accuracy is extremely important in order to maintain the quality and reliability of semiconductor devices and promote miniaturization.

  As described in Patent Documents 1 and 2, as an alignment mark, a plurality of patterns made of semiconductor or metal are arranged in parallel so as to have a certain space, and are configured by repeating the pattern and the space. May be used.

  When the alignment mark is formed large, it becomes easy to read with an alignment apparatus attached to an exposure apparatus or the like, but the area for creating a circuit pattern is reduced.

  Therefore, Patent Document 1 describes an alignment method that enables alignment processing even when the dimension of the alignment mark is reduced. Specifically, as sparse alignment, the magnification of the objective lens is lowered and the scrub line (dicing line) is detected to align the wafer, and then the magnification of the objective lens is raised to detect the alignment mark in the scribe line. The original alignment is performed.

Japanese Patent Laid-Open No. 3-228308 (published on October 9, 1991) JP 2000-306822 A (published on November 2, 2000)

  In recent years, the miniaturization of wiring has progressed more and more, and there is an increasing need to make a large amount of individual semiconductor chips such as LEDs (Light Emitting Diodes) with one semiconductor wafer, and the dicing lines between the semiconductor chips are also narrowed. It has become to. Therefore, even in the method of providing an alignment mark on a dicing line as described above, there is a problem that it is difficult to read the alignment mark with an alignment apparatus.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device and a semiconductor device manufacturing method capable of performing alignment with high precision even in a miniaturized semiconductor device. There is.

  In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes an alignment step of performing alignment using alignment marks provided at predetermined positions of a semiconductor wafer. Is provided with a linear portion in which a plurality of patterns having elongated portions are arranged in a direction perpendicular to the longitudinal direction of the elongated portions. It is characterized by a wider interval.

  As a result of experiments, it has been found that the alignment mark having the above configuration can provide sufficient contrast even in a semiconductor device that has been miniaturized. Therefore, the alignment can be performed with high accuracy by using the alignment mark having the above configuration.

  Examples of the shape of the alignment mark include a line shape, a cross shape, an L shape, and a T shape.

  In the method for manufacturing a semiconductor device according to the present invention, the pattern includes a wide portion wider than the elongated portion at one or both ends of the elongated portion, and the width of the wide portion is adjacent to the adjacent pattern. It is preferable that the interval between the wide portions is wider than that. In this case, even if static electricity is generated in the pattern in a dicing process or the like, there is a high possibility that the static electricity is discharged not to the semiconductor chip but to the wide portion of the adjacent pattern. Therefore, damage to the semiconductor chip due to the discharge can be prevented.

  In the method for manufacturing a semiconductor device according to the present invention, the alignment mark may be provided in the vicinity of a dicing line in the semiconductor wafer. In this case, it is not necessary to secure a new area for providing the alignment mark.

  In the method for manufacturing a semiconductor device according to the present invention, the interval between the elongated portions is preferably 1.5 to 2 times the width of the elongated portion.

  Note that the semiconductor device manufactured by the above method can achieve the same effects as described above.

  As described above, in the method of manufacturing a semiconductor device according to the present invention, the alignment mark for alignment is a linear part in which a plurality of patterns each having an elongated part are arranged in a direction perpendicular to the longitudinal direction of the elongated part. With respect to the adjacent patterns, since the gap between the elongated portions is wider than the width of the elongated portions, sufficient contrast can be obtained even in a semiconductor device that has been miniaturized. By using the alignment mark having the above configuration, there is an effect that the alignment can be performed with high accuracy.

It is a top view which shows the outline | summary of the semiconductor wafer which concerns on one Embodiment of this invention. It is a top view which shows the Example of the pattern of the linear alignment mark provided in a semiconductor wafer, and a comparative example. It is sectional drawing which shows the Example of the pattern of the said linear alignment mark. It is a figure which shows the result of having measured the contrast of the pattern of the said linear alignment mark in a tabular form. It is a top view which shows the pattern of the linear alignment mark which concerns on another embodiment of this invention. It is a top view which shows the outline | summary of the semiconductor wafer which concerns on another embodiment of this invention. It is sectional drawing which shows the Example of the pattern of the linear alignment mark which concerns on other embodiment of this invention.

[Embodiment 1]
Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

  FIG. 1 is a plan view showing an outline of a semiconductor wafer according to the present embodiment. As shown in the figure, a semiconductor wafer 1 is provided with a plurality of semiconductor chip portions 2 arranged vertically and horizontally. The semiconductor chip portion 2 is divided from the semiconductor wafer 1 by dicing to become a semiconductor chip (semiconductor device) such as an LED.

  Further, the semiconductor wafer 1 is provided with a linear alignment mark 3 for alignment. The linear alignment mark 3 is desirably arranged in a dicing line indicating a dicing location.

  FIG. 2A is a plan view showing an example of a linear alignment mark pattern according to the present embodiment, and FIGS. 2B and 2C are plan views showing comparative examples of the linear alignment mark pattern. FIG. As shown in the drawing, the linear alignment marks of the present embodiment and the comparative example have a configuration in which a plurality of patterns, which are a plurality of elongated portions made of semiconductor or metal, are arranged in a direction perpendicular to the longitudinal direction of the elongated portions. .

  In the pattern 30 of the linear alignment mark 3 of this embodiment shown in FIG. 2A, the width (pattern width) Wp, which is the length in the short direction, is larger than the interval (space width) Ws between adjacent patterns 30. Is also narrow, that is, Wp <Ws. On the other hand, the pattern 101 of the linear alignment mark 100 of the comparative example shown in FIG. 2B has a width Wp equal to the interval Ws, that is, Wp = Ws. On the other hand, the pattern 111 of the linear alignment mark 110 of the comparative example shown in FIG. 2C has a width Wp wider than the interval Ws, that is, Wp> Ws.

  FIG. 3 shows a cross-sectional view of the linear alignment mark 3 of this embodiment shown in FIG. As shown in FIG. 3, the alignment mark 3 has a structure in which a gate insulating film 41 and a gate electrode layer 42 are stacked on a semiconductor silicon substrate 40 that is the semiconductor wafer 1. The linear alignment marks 100 and 110 of the comparative example shown in FIGS. 2B and 2C have the same structure.

[Example 1]
For each of the patterns 30, 101, and 111 in the three types of linear alignment marks 3, 100, and 110 shown in FIGS. Was measured with an alignment measuring device.

  The length of each linear alignment mark was 1 mm, and the length L in the longitudinal direction of each pattern was 48 μm. In addition, the thickness of the gate electrode layer 42 of each linear alignment mark was set to 3000 mm (angstrom). In addition, model number KLA-5300 manufactured by KLA Tencor was used as an alignment measurement apparatus.

  FIG. 4 is a diagram showing measurement results in a table format. In the determination results shown in FIG. 6, the case where the contrast is 800 or more is indicated by ◯, the contrast less than 800 or 500 or more is indicated by Δ, and the contrast less than 500 is indicated by ×. In the above alignment measuring apparatus, it has been empirically found that the alignment accuracy is 100% when the contrast is 800 or more.

  As shown in FIG. 4, when the space width Ws is wider than the pattern width Wp (FIGS. 2A and No. 1 and 2 in FIG. 4), the contrast is 800 or more, and alignment by the alignment apparatus is practical. It was possible in time. Therefore, the alignment defect rate was 0%.

  On the other hand, when the space width Ws and the pattern width Wp are equal (No. 3 and 4 in FIG. 2B and FIG. 4), the contrast is 500 or more and less than 800, and the alignment may be possible. The alignment may not be possible, and the alignment defect rate is about 50%.

  On the other hand, when the space width Ws is narrower than the pattern width Wp (FIG. 2 (c) and No. 5 and 6 in FIG. 4), the contrast is less than 500, and the alignment is often impossible. The defective rate was about 70%. When the pattern width Wp was 23 μm or more, the sensitivity deteriorated and the pattern could not be identified.

  Further, referring to FIG. 4, even if the patterns have different pitches (the sum of the space width Ws and the pattern width Wp), the same determination result is obtained as long as the patterns have the same magnitude relationship between the space width Ws and the pattern width Wp. (No. 1 ・ 2: Judgment result ○, No. 3 ・ 4: Judgment result Δ, and No. 5 ・ 6: Judgment result ×) in FIG. 4, that is, the pitch depends on the judgment result. I understand that I don't. In addition, in FIG. 1-3, it can be understood that a good determination result (◯) can be obtained if the space width Ws is at least 1.5 to 2 times the pattern width Wp.

  Examples of the pattern material include polysilicon, metal, and the like, and these materials have different light reflectivities. However, if the space width Ws is wider than the pattern width Wp, a contrast of 800 or more can be secured regardless of which of the above materials is used, and the alignment defect rate can be reduced.

  Intuitively, when the pattern width Wp is wider than the space width Ws, the alignment measuring device can easily detect the alignment mark 3 and a good result can be obtained. However, according to FIG. 4, good results could be obtained when the space width Ws was wider than the pattern width Wp.

  The reason is that the reflected light of the pattern 30 part and the reflected light of the exposed part of the semiconductor wafer that does not have the pattern interfere with each other so that high contrast is obtained and the alignment mark 3 is easy to see. Is expected.

  Therefore, in the linear alignment mark 3 composed of a plurality of patterns 30 and intervals, by making the space width Ws wider than the pattern width Wp, sufficient contrast can be obtained, and alignment defects can be reduced. There is an effect.

  As described above, in the semiconductor device of the present embodiment, alignment can be easily performed, and the maintenance and super miniaturization of the quality and reliability of the semiconductor device can be promoted.

[Embodiment 2]
Another embodiment of the present invention will be described with reference to FIG. In the present embodiment, the structure of the end portion of the pattern 30 is different from the pattern 30 shown in FIG. Note that the terms defined in the above embodiment are used according to the definition in this embodiment unless otherwise specified, and the description thereof is omitted.

  FIG. 5 is a plan view showing an example of a pattern of linear alignment marks according to the present embodiment. As illustrated, in this embodiment, a wide portion 31 wider than the pattern 30 is provided at the end of the pattern 30. As shown in the figure, in the wide portion 31, as in the pattern 30, the interval between adjacent wide portions 31 is wider than the width of the wide portion 31.

  By the way, in the linear alignment mark 3 as shown in FIG. 2A, when the width of the pattern 30 is narrow, if static electricity is generated in the pattern 30 in a dicing process or the like, the pattern of the semiconductor chip portion 2 starts from the end of the pattern 30. There is a risk of electrical discharge. On the other hand, in the present embodiment, as shown in FIG. 5, since the wide portion 31 is provided at the end of the pattern 30, the semiconductor chip portion 2 can be protected from electrostatic discharge generated at the alignment mark 3. it can.

  In addition, the provision of the wide portion 31 can enhance the adhesion in the adhesion between the pattern 30 having a narrow width and the base, and can prevent the pattern from peeling off. Furthermore, the effect of improving the diffuse reflectance of light on the alignment mark is also achieved.

  The wide portion 31 may be provided when the width Wp of the pattern 30 is particularly about 3 μm or less. For example, when the width Wp of the pattern 30 is 3 μm, the width of the wide portion 31 may be 5 μm.

  In addition, the width of the wide part 31 may be the same or wider than the interval between the adjacent wide parts 31. Even in this case, if the distance between the patterns 30 is wider than the width of the pattern 30, a good contrast can be secured between the patterns 30 and the patterns 30, and alignment can be easily performed.

[Embodiment 3]
Still another embodiment of the present invention will be described with reference to FIG. In this embodiment, an example of an alignment mark having a shape different from that of the above embodiment will be described. Note that the terms defined in the above embodiment are used according to the definitions in this embodiment unless otherwise specified, and the description thereof is omitted.

  FIG. 6A is a plan view showing an outline of the semiconductor wafer according to the present embodiment. As shown in the figure, the semiconductor wafer 1 is provided with a cross-shaped mark 4, an L-shaped mark 5, and a T-shaped mark 6 as alignment marks.

  FIG. 6B is an enlarged view of the L-shaped mark 5. As shown in the figure, the alignment mark according to the present embodiment includes a plurality of groups in which a plurality of patterns 30 which are a plurality of elongated portions made of semiconductor or metal are arranged in a direction perpendicular to the longitudinal direction of the elongated portions. The arrangement is arranged. Also in this embodiment, the same effect as the first embodiment can be obtained.

  As an example of this embodiment, the dimension of the cross mark 4 is about 68 μm × 68 μm, the dimension of the L-shaped mark 5 is about 39 μm × 39 μm, and the dimension of the T-shaped mark 6 is , Approximately 39 μm × 68 μm. Further, as shown in the drawing, the intersection A in the alignment mark may have a configuration in which the pattern 30 is not provided, or may have a configuration in which various patterns 30 are provided. In any configuration, it is considered that the influence on the alignment defect rate is small.

As described above, various changes can be made to the alignment mark.
[Embodiment 4]
Another embodiment of the present invention will be described with reference to FIG. In the present embodiment, the alignment mark structure is different from that shown in FIG. Note that the terms defined in the above embodiment are used according to the definition in this embodiment unless otherwise specified, and the description thereof is omitted.

  FIG. 7 shows a cross-sectional view of the linear alignment mark of the present embodiment. As shown in FIG. 7, the pattern 30 a of the alignment mark 3 a has a structure in which a gate insulating film 41, a gate electrode layer 42, and a coating resist layer 43 are stacked on a semiconductor silicon substrate 40 that is the semiconductor wafer 1. Yes. The thickness of the gate electrode layer 42 of each linear alignment mark was 3000 mm, and the thickness of the coating resist layer 43 was 5000 mm. Also in this embodiment, the same effect as the first embodiment can be obtained.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  For example, in the above embodiment, the alignment mark is provided in the dicing line. However, the present invention is not limited to this, and for example, the alignment mark may be provided so as to protrude from the dicing line.

  As described above, according to the present invention, in an alignment mark composed of a plurality of patterns, a sufficient contrast can be obtained from the alignment mark by making the interval between adjacent patterns wider than the width of the pattern. Since it can be performed well, it can be applied to the manufacture of any semiconductor device that has been miniaturized.

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Semiconductor chip part (semiconductor device)
3 Alignment mark 30 patterns (elongated part)
31 Wide part 4 Cross-shaped mark 5 L-shaped mark 6 T-shaped mark Wp Pattern width (width of elongated part)
Ws Space width (interval between narrow parts)

Claims (5)

A method for manufacturing a semiconductor device, comprising:
Using an alignment mark provided at a predetermined position of the semiconductor wafer, including an alignment step of performing alignment,
The alignment mark includes a linear portion in which a plurality of patterns having elongated portions are arranged in a direction perpendicular to the longitudinal direction of the elongated portions,
For adjacent the pattern, the greater than the width of the elongated portion, towards the spacing of the elongate portion to each other is widely,
The pattern includes a wide portion wider than the elongated portion at one or both ends of the elongated portion,
A method for manufacturing a semiconductor device, characterized in that, in the adjacent patterns, the interval between the wide portions is wider than the width of the wide portions . 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the alignment mark is provided in the vicinity of a dicing line in the semiconductor wafer. 3. The method of manufacturing a semiconductor device according to claim 1, wherein an interval between the elongated portions is 1.5 to 2 times a width of the elongated portions. The alignment marks may be linear, cross-shaped, the method of manufacturing a semiconductor device according to any one of L-shaped, and from the claims 1, wherein the T-shaped is at least one to three.   A semiconductor wafer having an alignment mark at a predetermined position,
  The alignment mark includes a linear portion in which a plurality of patterns having elongated portions are arranged in a direction perpendicular to the longitudinal direction of the elongated portions,
  For the adjacent patterns, the interval between the elongated portions is wider than the width of the elongated portions,
  The pattern includes a wide portion wider than the elongated portion at one or both ends of the elongated portion,
  A semiconductor wafer characterized in that, in the adjacent patterns, the interval between the wide portions is wider than the width of the wide portions.

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