JP6049564B2 - Data trace circuit, integrated circuit, and data trace method - Google Patents

Description

  The present invention relates to a technique for collecting (tracing) data flowing through an integrated circuit, for example.

Program behavior is analyzed to improve computer performance.
As a method for analyzing the behavior of a program, a method of probing a bus and recording an address or the like on a storage medium was disclosed in the 1970s (for example, Patent Document 1).
Recently, a commercially available logic analyzer probe uses data to record data (also referred to as a trace) in a memory and analyzes the recorded data using a general computer. By this method, the behavior of the program can be analyzed without using a dedicated device.

In addition, there is a method using a function called a performance counter (for example, Patent Document 2 and Non-Patent Document 1).
In this method, events such as a cache miss occurring in a computer are counted without directly monitoring a signal generated in the computer, and a bottleneck in the operation of the computer is investigated based on the number of counts.

On the other hand, as a result of the dramatic increase in circuit integration due to advances in semiconductors, the SoC has a CPU (Central Processing Unit), a cache memory, a memory controller, a RAM (Random Access Memory), an input / output device, a bus, etc. mounted on a single chip. (System on a Chip) has been developed.
However, since an event that affects the performance of the entire system, such as an operation related to a cache miss or an access to a memory or an input / output device, occurs inside the SoC, a bus or LSI pin (LSI: Large Scale) that is externally output from the SoC. It is very difficult to know these events by connecting to Integration.

  Similar problems have arisen not only in terms of performance but also in terms of program debugging, and the following methods have been proposed to solve or alleviate the problems.

  (1) A debugging method using JTAG (Joint Test Action Group) is common. JTAG is a function for reading the contents of the CPU or memory with the program stopped. However, this method has a problem that the operation cannot be continued in many embedded devices that require real-time operation.

(2) There is a method of outputting important internal signals from an LSI using high-speed signals (for example, Patent Document 3). However, in this method, if the condition of (frequency × number of pins) <(average signal change frequency × number of bits) is not satisfied, information is lost if information is not compressed even if information is buffered. Or there is a problem that only information about a sample can be obtained.
(3) As a technique for solving this problem, there is a memory inside the LSI, information on the event that has occurred is once written in the memory, and the information that has been written in the memory is taken over time later by JTAG or Ethernet (registered trademark) There is a method of reading using a technique such as the above. When this method is used, in order to reduce the chip area of the memory, the address space of the SRAM (Static Random Access Memory) built in the LSI is divided, and the event is recorded using DMA (Direct Memory Access). Information is written into the divided SRAM (for example, Patent Document 4).

As a result of the improved processing capability of high-performance and high-performance embedded devices, the method (2) (pin output method) cannot cope with an increase in frequency band for obtaining event information. In the method (3) (SRAM method), since the storage capacity is small, the event information cannot be stored.
Therefore, in order to use the method (2) for performance analysis, a RAM having a storage capacity of several hundred kilobytes to several tens of megabytes is required. In consideration of chip cost and performance, it is necessary to store event information in a DRAM (Dynamic RAM) provided outside the chip.

As a method for acquiring event information, a method of monitoring an internal bus of an integrated circuit in order to reduce an acquisition circuit is common.
Specifically, the command signal and the valid signal transmitted via the internal bus are monitored (for example, Patent Document 5). The valid signal is a signal indicating that the command signal is valid.
Although the purpose is different, a method of monitoring the bus and recording fault information in a memory has been used for a long time (for example, Patent Document 6).

On the other hand, those in the form of a point-to-point connection that directly connects a signal transmission source and a signal reception source in an integrated circuit have come into circulation. By this point-to-point connection, the transmission source and the reception source are directly connected by the interconnect method without going through the internal bus. In the previous form, there was one bus sender at a time, but in this form there may be a plurality of bus senders simultaneously.
In addition, since a transmission path (also referred to as a channel) for transmitting a write command signal and a transmission path for transmitting a read command signal are provided separately, the read command signal and the write can be written even if there is one transmission source. The command signal may be generated at the same time.

Some interconnect methods autonomously arbitrate between the valid state of the transmission source and the valid state of the reception source. In other words, the transmission source makes the valid signal (VALID) indicating that the command signal is effective, and the reception source makes the effective signal (READY) indicating that the command signal can be taken in significant. Then, it is considered that the transmission of the command signal is established when both the effective signal of the transmission source and the effective signal of the reception source become significant. This mechanism is called a shake hand.
There is AXI (Advanced Extensible Interface) of ARM Co., Ltd. as a specification of the shake hand (see Non-Patent Document 2). Although not described therein, in order to perform arbitration when a plurality of transmission sources attempt to transmit command signals to the same reception source at the same time, the following functions can be realized. The function is to select a combination of a transmission source and a reception source by a switch circuit so that transmission of command signals is not established simultaneously by a plurality of combinations.

The integrated circuit having such an interconnect form has the following problems.
The first problem is that the same number of signal lines as the number of transmission sources are required, the number of signals increases, and the chip area increases.
The second problem is that a trace buffer must be provided with a structure capable of simultaneously recording information of a plurality of transactions (for example, command signals). Like AXI, if a handshake occurs at the same time for both the channel for the read command signal and the channel for the write command signal, multiple transactions occur at the same time, so the circuit for collecting traces becomes large-scale And complicate.
The third problem is that the original transfer performance of the interconnect method cannot be obtained if simultaneous occurrence of shake hands is suppressed or reduced. Although a method of suppressing or reducing the simultaneous occurrence of shake hands only at the time of acquiring the trace is conceivable, the performance of the operation to be measured is not correctly reflected in the trace result, and it is necessary to correct the performance value obtained from the trace result. In addition, if the mode is switched from the normal mode to the suppression mode that suppresses the simultaneous occurrence of shake hands during the transmission of the command signal, the continuity of the operation of the interconnect method is not guaranteed.

US Pat. No. 3,588,837 US Pat. No. 5,557,548 JP 2001-109643 A JP 2006-318172 A JP 2001-134465 A JP-A-5-94384

“MPC750 RISC Microprocessor User's Manual”, Motorola, 1997, p. 11-1 to 11-12 "AMBA (R) AXI protocol", ARM

  An object of the present invention is, for example, to be able to simultaneously store one or more target data generated simultaneously in a memory while efficiently using a storage area of the memory.

The data trace circuit of the present invention is
A memory selection value storage unit for storing a memory selection value for selecting at least one of the plurality of memories;
A data input unit for inputting one or more target data;
Based on the memory selection value stored in the memory selection value storage unit, the same number of memories as the number of target data input by the data input unit are used as the memory group for storing the one or more target data. A memory group selection unit for selecting from the memories of
Based on the number of target data input by the data input unit, the memory selection value stored in the memory selection value storage unit is selected to select a memory other than the memory group selected by the memory group selection unit. A memory selection value updating unit that updates the value to

  According to the present invention, for example, the same number of memories as the number of simultaneously generated target data can be selected, and one or more simultaneously generated target data can be simultaneously stored in each memory. Further, by selecting the memory for storing the target data in order from the plurality of memories, an equal amount of the target data can be stored in the plurality of memories. That is, each storage area of a plurality of memories can be used efficiently.

2 is a hardware configuration diagram of the integrated circuit 100 according to Embodiment 1. FIG. 6 is a diagram showing a state of a shake hand of a request in the first embodiment. FIG. 3 is a configuration diagram of a request suppression circuit 200 according to Embodiment 1. FIG. 4 is a table illustrating an example of input / output values of a signal processing circuit 220 according to the first embodiment. 3 is a configuration diagram of a trace buffer 300 according to Embodiment 1. FIG. 4 is a table illustrating an example of input / output values of a selection control circuit 313 and input values of memories (330 to 333) according to the first embodiment. 4 is a table showing an example of input / output values of a buffer management circuit 350 and input values of memories (330 to 333) according to the first embodiment. 3 is a table illustrating an example of input / output values of a buffer management circuit 350 according to the first embodiment.

Embodiment 1 FIG.
A description will be given of a mode in which one or more simultaneously generated data are simultaneously stored in the trace buffer while efficiently using the storage area of the trace buffer.

FIG. 1 is a hardware configuration diagram of an integrated circuit 100 according to the first embodiment.
A hardware configuration of the integrated circuit 100 according to the first embodiment will be described with reference to FIG.

The integrated circuit 100 includes a CPU 110, a cache memory 120, a DRAM controller 130, a CPU bridge 140, and a trace buffer 300 (an example of a data trace circuit).
The integrated circuit 100 includes a bus controller 101, a DMA controller 102, an SRAM controller 103, and an I / O bridge 104.
Further, the integrated circuit 100 includes a reset circuit, a clock circuit, and the like (not shown).
An LSI (Large Scale Integration) is an example of an integrated circuit.

  The bus controller 101 controls devices such as the DMA controller 102, the SRAM controller 103, the I / O bridge 104, the DRAM controller 130, or the CPU bridge 140 connected to the bus 109.

  The DMA controller 102 controls DMA transfer of data performed between devices. DMA is an abbreviation for Direct Memory Access.

  The SRAM controller 103 controls SRAM (Static RAM) or FROM (Flash ROM). RAM is an abbreviation for Random Access Memory, and ROM is an abbreviation for Read Only Memory.

  The I / O bridge 104 controls input / output devices. In the figure, “I / O” means an input / output device.

The DRAM controller 130 controls a DRAM (Dynamic RAM).
The CPU bridge 140 controls data transfer of the CPU 110 performed via the bus 109.
The DRAM controller 130 and the CPU bridge 140 include a request suppression circuit 200 (an example of a data suppression circuit) described later.

  The CPU 110 processes data, and the cache memory 120 stores data processed by the CPU 110. CPU is an abbreviation for Central Processing Unit.

  The CPU 110 reads data without (1) using the cache memory 120 or (2) without using the cache memory 120.

(1) When the cache memory 120 is used, the CPU 110 reads target data from the cache memory 120 as follows.
When the target data is stored in the cache memory 120, that is, when a cache hit occurs, the CPU 110 reads the target data from the cache memory 120.
If the target data is not stored in the cache memory 120, that is, if a cache miss occurs, the cache memory 120 sends a write request to the DRAM controller 130 via the signal line 121W in order to write the stored data to the DRAM. Send. Then, the cache memory 120 transmits a read request to the DRAM controller 130 via the signal line 121R in order to read out target data from the DRAM. The write request and the read request include information regarding data to be written or data to be read, such as a command, a data length, and an address.
The cache memory 120 that is the sender of each request corresponds to a master of AXI (Advanced extensible Interface), and the DRAM controller 130 that is the receiver of each request corresponds to a slave of AXI.
The signal line 121W and the signal line 121R are signal lines (also referred to as interconnect signal lines) that connect the cache memory 120 and the DRAM controller 130 without passing through the bus 109. The signal line 121W corresponds to an AXI write address channel, and the signal line 121R corresponds to an AXI read address channel. In addition to the write address channel, there are a write data channel for communicating data and a write response channel for communicating response signals. In addition to the read address channel, there is a read data channel (not shown) for communicating data and response signals. The sender of the write response channel and the read data channel is the DRAM controller 130.

  (2) When the cache memory 120 is not used, the CPU 110 transmits a write request to the CPU bridge 140 via the cache memory 120 and the signal line 122W, and sends a read request to the CPU bridge 140 via the cache memory 120 and the signal line 122R. To send to. The signal line 122W corresponds to an AXI write address channel, and the signal line 122R corresponds to an AXI read address channel.

FIG. 2 is a diagram showing a state of a shake hand of a request in the first embodiment.
In both cases (1) and (2), communication of each request is established when the shake hand is established (see T2 in FIG. 2). The shake hand is a communication method in which communication is established when a VALID signal (also referred to as a valid signal) is significant and a READY signal (also referred to as a preparation signal) is significant. The significance of the VALID signal means that the sender of the request transmits a VALID signal that means that the request is valid. In addition, the fact that the READY signal is significant means that the READY signal that means that the receiver of the request can receive the request is transmitted. In FIG. 2, the VALID signal is significant (VALID = 1) and the READY signal is significant (READY = 1) at the timing of T2. That is, the shake hand is established at the timing of T2.

Since the signal line 121W and the signal line 121R are independent, a write request for the signal line 121W and a read request for the signal line 121R may be established at the same time.
Similarly, since the signal line 122W and the signal line 122R are independent, a write request for the signal line 122W and a read request for the signal line 122R may be established at the same time.
Further, four requests, that is, a write request for the signal line 121W, a read request for the signal line 121R, a write request for the signal line 122W, and a read request for the signal line 122R may be established simultaneously.

  The request suppression circuit 200 of the DRAM controller 130 and the CPU bridge 140 is a circuit that suppresses at least one of a write request and a read request that are simultaneously established.

  The trace buffer 300 is a circuit that simultaneously stores requests simultaneously output from the request suppression circuit 200 of the DRAM controller 130 and the request suppression circuit 200 of the CPU bridge 140.

FIG. 3 is a configuration diagram of the request suppression circuit 200 according to the first embodiment.
The configuration of the request suppression circuit 200 provided in the DRAM controller 130 (see FIG. 1) will be described with reference to FIG. The CPU bridge 140 (see FIG. 1) includes a similar request suppression circuit 200.

The request suppression circuit 200 (an example of a data suppression circuit) includes a first selection circuit 210 (a data suppression input unit, a first AND circuit 231 and a second AND circuit 232. The AND circuit has a plurality of inputs. This is a logical product circuit that outputs a logical product obtained from values.
Furthermore, the request suppression circuit 200 includes a signal processing circuit 220 (an example of a data selection unit and an inhibition number counting unit), a mode register 221 (an example of a mode value storage unit), and a count register 222.

The first selection circuit 210 inputs a write request from the signal line 121 </ b> W, inputs a read request from the signal line 121 </ b> R, and inputs a selection signal from the signal processing circuit 220.
Then, the first selection circuit 210 outputs a request (except for the VALID signal) selected by the selection signal among the write request and the read request.

  The first AND circuit 231 receives a VALID signal (AWVALID) included in the write request and a READY signal (AWREADY before processing) generated by the DRAM controller 130 with respect to the write request. The AWREADY signal before processing is generated from the write buffer empty state of each slave (130, 140) and the busy state of the memory or bridge write, and originally from the slave to the master as part of the signal line 121W and the signal line 122W. It was what was being sent. When the value of the input VALID signal and the value of the input READY signal are both “1 (significant)”, the first AND circuit 231 outputs the VALID signal indicating “1” (for write request). Is output. In other cases, the first AND circuit 231 outputs a VALID signal (for write request) indicating “0 (not significant)”.

  The second AND circuit 232 inputs a VALID signal (ARVALID) included in the read request and a READY signal (ARREADY before processing) generated by the DRAM controller 130 regarding the read request. The ARREADY signal before processing is generated from the read buffer empty state of each slave (130, 140) and the busy state of memory or bridge read, and originally from the slave to the master as part of the signal line 121R and signal line 122R. It was what was being sent. When the value of the input VALID signal and the value of the input READY signal are both “1”, the second AND circuit 232 outputs a VALID signal (for read request) indicating “1”. In other cases, the second AND circuit 232 outputs a VALID signal (for read request) indicating “0”.

  The mode register 221 is a storage unit that stores a mode value indicating the type of operation mode. There are two types of operation modes: a suppression mode that suppresses at least one of a write request and a read request that are established simultaneously, and a non-inhibition mode that does not perform suppression. This mode can be set to 0 or 1 by means such as writing by a program or setting of an external pin of the LSI.

  The count register 222 stores the number of times that write requests or read requests are suppressed, that is, the number of suppressed write requests and read requests.

The signal processing circuit 220 includes a VALID signal (AWVALID) included in the write request, a VALID signal (ARVALID) included in the read request, a READY signal (AWREADY) before processing related to the write request, and READY before processing related to the read request. The signal (ARREADY) and the mode value stored in the mode register 221 are input.
Then, the signal processing circuit 220 outputs a selection signal corresponding to the value of each input signal and the input mode value to the first selection circuit 210, the first AND circuit 231 and the second AND circuit 232. .
Further, the signal processing circuit 220 processes each READY signal according to the value of each input signal and the input mode value. Each READY signal is output to the cache memory 120. See Non-Patent Document 2 for a description of each READY signal output to the cache memory 120.
Further, the signal processing circuit 220 increments the count value stored in the count register 1 by 1 when the write request and the read request are simultaneously established in the inhibition mode and a selection signal for selecting one of the requests is output. . That is, the signal processing circuit 220 functions as a performance monitor circuit (also referred to as a performance counter) that counts the number of requests to be inhibited. The read path of this performance monitor circuit is outside the specified range of this embodiment.

FIG. 4 is a table showing an example of input / output values of the signal processing circuit 220 according to the first embodiment.
An example of input / output values of the signal processing circuit 220 in the first embodiment will be described with reference to FIG. Note that the signal processing circuit 220 may store and use the table shown in FIG. 4 as data.

  In FIG. 4, the mode value “1” means the inhibition mode, and the mode value “0” means the non-inhibition mode. Further, “dc” (don't care) means an arbitrary value (the same applies to each table described below).

An input value of item number “1” means that a write request and a read request are established simultaneously when the suppression mode is designated.
Since the inhibition mode is designated, the signal processing circuit 220 processes the ARREADY signal value from “1” to “0”, and outputs a selection signal “0” for selecting a write request. Thereby, a read request can be suppressed.
However, the signal processing circuit 220 may process the AWREADY signal value from “1” to “0” instead of the ARREADY signal value, and output a selection signal “1” for selecting a read request. Thereby, a write request can be suppressed.
Further, the signal processing circuit 220 may process both the signal values of ARREADY and AWREADY from “1” to “0” and output a selection signal indicating an arbitrary value. Thereby, both a write request and a read request can be suppressed. Although not shown, the count register 222 is incremented only with this item number “1”, and the other item numbers are not counted up.

An input value of item number “2” means that a write request and a read request are established at the same time when the suppression mode is not designated.
Since the inhibition mode is not designated, the signal processing circuit 220 outputs both the AWREADY and ARREADY signal values “1” as processed signal values. The signal processing circuit 220 outputs a selection signal indicating an arbitrary value. As a result, write requests or read requests are suppressed. However, the write request signal line 201A and the read request signal line 201A are provided between the request suppression circuit 200 and the trace buffer 300, and the request suppression circuit 200 transmits both the write request and the read request to the trace buffer 300. May be output.

An input value from item number “3” to item number “7” means that at least one of the write request and the read request is not established.
In this case, the signal processing circuit 220 outputs AWREADY indicating a value before processing or an arbitrary value as AWREADY after processing regardless of whether or not the inhibition mode is designated. Similarly, the signal processing circuit 220 outputs ARREADY indicating a value before processing or an arbitrary value as ARREADY after processing. Further, the signal processing circuit 220 outputs a selection signal for selecting an established request or an arbitrary request.

Returning to FIG. 3, the request output from the request suppression circuit 200 will be described.
When the selection signal “0” for selecting the write request is output to the first selection circuit 210 and the first AND circuit 231, the processed write request signal is sent from the request suppression circuit 200 via the signal line 201A. The data is output to the trace buffer 300.
The processed write request takes a value equivalent to the logical product of the write request (except for the VALID signal) output from the first selection circuit 210 and the value output from the first AND circuit 231. The first AND circuit 231 is a logical product of the VALID signal (AWVALID) of the write request, the selection signal output from the signal processing circuit 220, and the READY signal (AWREADY) before processing for the write request. Output the value.

When the selection signal “1” for selecting a read request is output from the signal processing circuit 220, the processed read request is output from the request suppression circuit 200 to the trace buffer 300 via the signal line 201A.
The processed read request takes a value equivalent to the logical product of the read request (except for the VALID signal) output from the first selection circuit 210 and the value output from the second AND circuit 232. The second AND circuit 232 calculates the logical product of the VALID signal (ARVALID) of the read request, the selection signal output from the signal processing circuit 220 and the READY signal (AWREADY) before processing for the read request. Output the value.

  In this way, the request signal is narrowed in half by the signal processing circuit 220, but if there are not only two processed VALID signals, it is not possible to distinguish between the three of write, read, and no signal. There is an extra. Note that the same effect can be obtained by using a total of two of one logical sum of each logical product and one selection signal.

  In FIG. 3, a signal processing circuit 220 (also referred to as a combinational circuit) that operates according to a combination of signal values of each input signal processes each READY signal. Each READY signal may be generated as a flip-flop output. Note that the flip-flop circuit prevents the output of each READY signal after processing from being delayed. Each VALID signal before one cycle is input, and each READY signal after processing is output at the next cycle. Also good. However, in order to prevent the AXI protocol from being destroyed, a state machine is required in which the value of each READY signal one cycle before is set to “0” in advance and transitions to “1” when the condition is satisfied.

  As described above, the request suppression circuit 200 can suppress at least one of a write request and a read request that are simultaneously established.

FIG. 5 is a configuration diagram of the trace buffer 300 according to the first embodiment.
The configuration of the trace buffer 300 in the first embodiment will be described with reference to FIG.

The trace buffer 300 (an example of a data trace circuit) includes a first selection circuit 311 (an example of a data input unit), a second selection circuit 312 (an example of a data input unit), and a selection control circuit 313.
The trace buffer 300 includes four input registers, a first input register 320 to a fourth input register 323, and four memories, a first memory 330 to a fourth memory 333.
The trace buffer 300 includes an output circuit 340 and an output register 341.
The trace buffer 300 includes a buffer management circuit 350 (an example of a memory group selection unit, a memory selection value update unit, an entry designation unit, and an entry designation value update unit).
The trace buffer 300 includes a sector point register 351 (an example of a memory selection value storage unit), a first write point register 352 (an example of an entry specification value storage unit), and a second write point register 353 (an entry specification value storage). Part of an example).

Hereinafter, the write request or read request output from the request suppression circuit 200 of the DRAM controller 130 (see FIG. 1) is referred to as “request (A)”, and is output from the request suppression circuit 200 of the CPU bridge 140 (see FIG. 1). The write request or read request is called “request (B)”.
Request (A) and request (B) include data, data length, address, VALID signal, READY signal, and the like.

The first selection circuit 311 and the second selection circuit 312 receive the request (A) and the request (B), and input selection signals (Sa, Sb) from the selection control circuit 313.
Then, the first selection circuit 311 and the second selection circuit 312 output the request selected by the selection signal (Sa, Sb) out of the request (A) and the request (B) to the two input registers. .
The output destination of the request output from the first selection circuit 311 is the first input register 320 and the third input register 322, and the output destination of the request output from the second selection circuit 312 is the second input register. A register 321 and a fourth input register 323.
The selection signal output to the first selection circuit 311 is denoted as “Sa”, and the selection signal output to the second selection circuit 312 is denoted as “Sb”.

The selection control circuit 313 inputs VALID signals (Va, Vb) included in each of the request (A) and the request (B), and inputs a sector pointer (SECTP) from the sector point register 351.
Then, the selection control circuit 313 outputs selection signals (Sa, Sb) to the first selection circuit 311 and the second selection circuit 312 according to the value of the VALID signal and the value of the sector pointer.
The VALID signal included in the request (A) is described as “Va”, and the VALID signal included in the request (B) is described as “Vb”.

The first input register 320 receives a request from the first selection circuit 311, stores the input request, and outputs the stored request to the first memory 330.
The second input register 321 receives a request from the second selection circuit 312, stores the input request, and outputs the stored request to the second memory 331.
The third input register 322 receives a request from the first selection circuit 311, stores the input request, and outputs the stored request to the third memory 332.
The fourth input register 323 receives a request from the second selection circuit 312, stores the input request, and outputs the stored request to the fourth memory 333.

Each memory from the first memory 330 to the fourth memory 333 has a plurality of storage areas (also referred to as entries), and the storage area is designated by an address input to the port (Aw).
Each memory (330 to 333) receives a request from each input register (320 to 323). “D0” to “D3” in the figure mean ports to which requests are input.
The first memory 330 to the third memory 332 receive the write pointer (WPTRa) from the first write point register 352 and the write enable signal from the buffer management circuit 350. The fourth memory 333 receives a write pointer (WPTRb) from the second write point register 353 and receives a write enable signal from the buffer management circuit 350. “Aw” in the figure means a port to which an address is inputted by a write pointer, and “WE0” to “WE3” in the figure means a port to which a write enable signal is inputted.
Each memory (330 to 333) stores a request according to the write pointer and the write enable signal. The request is an example of trace data (target data) stored in each memory of the trace buffer 300.
The write pointer indicates a value (an example of an entry specification value) that specifies a storage area for storing a request, and the write enable signal indicates a value that specifies whether to store a request.

  When the trace buffer (request) is requested to be read from the trace buffer 300, each of the memories (330 to 333) reads the requested trace data from the storage area and outputs the read trace data to the output circuit 340. . “Do” in the figure means a port to which trace data is output.

The output circuit 340 inputs the trace data from each memory (330 to 333) and outputs the input trace data to the output register 341.
The output register 341 receives the trace data from the output circuit 340 and outputs the input trace data to the input / output device via the bus 109.

The buffer management circuit 350 inputs the VALID signals (Va, Vb) included in each of the request (A) and the request (B), and inputs the sector pointer (SECTP) from the sector point register 351.
Then, the buffer management circuit 350 outputs a write enable signal to each memory (330 to 333) according to the value of the VALID signal and the value of the sector pointer.
Further, the buffer management circuit 350 sets new write pointers (WPTRa, WPTRb) in the first write point register 352 and the second write point register 353 in accordance with the value of the VALID signal and the value of the sector pointer. That is, the buffer management circuit 350 updates the write pointers stored in the first write point register 352 and the second write point register 353.
Note that the buffer management circuit 350 outputs a read pointer to each memory (330 to 333) when the reading of the trace data is requested. The read pointer designates a storage area from which trace data is read. Note that the first memory 330 to the fourth memory 333 have ports and signal lines to which a read pointer that is a read address is input. They are not shown in the figure.

Further, the buffer management circuit 350 sets a new sector pointer in the sector point register 351 in accordance with the value of the VALID signal and the value of the sector pointer. That is, the buffer management circuit 350 updates the sector pointer stored in the sector point register 351.
The sector pointer indicates a value (an example of a memory selection value) for selecting a memory (330 to 333) storing a request.

The sector point register 351 stores the sector pointer, and outputs the stored sector pointer to the selection control circuit 313 and the buffer management circuit 350.
The sector point register 351 receives a new sector pointer from the buffer management circuit 350 and stores the input new sector pointer.

The first write point register 352 stores the first write pointer (WPTRa), and outputs the stored first write pointer from the first memory 330 to each of the third memories 332. The first write point register 352 receives a new first write pointer from the buffer management circuit 350 and stores the input first write pointer.
The second write point register 353 stores the second write pointer (WPTRb), and outputs the stored second write pointer to the fourth memory 333. The second write point register 353 receives a new second write pointer from the buffer management circuit 350 and stores the input second write pointer.

FIG. 6 is a table showing an example of input / output values of the selection control circuit 313 and input values of the memories (330 to 333) according to the first embodiment.
An example of input / output values of the selection control circuit 313 and input values of the memories (330 to 333) in the first embodiment will be described with reference to FIG. Note that the selection control circuit 313 may store and use the table shown in FIG. 6 as data.

The input values (Va = 1, Vb = 1) from item number “1” to item number “4” mean that requests (A, B) are established at the same time. The sector pointer (SECTP) indicates any value from “0” to “3”.
In the case of the item numbers “1” and “3” (SECTP = 0 or 2), the selection control circuit 313 sends a selection signal (Sa, Sb) indicating “0” to the first selection circuit 311 and the second selection circuit 312. Output to. As a result, the request (A) is inputted to the first memory 330 (D0) and the third memory 332 (D2), and the request (B) is sent to the second memory 331 (D1) and the fourth memory 333 (D3). ) Is entered.
In the case of the item numbers “2” and “4” (SECTP = 1 or 3), the selection control circuit 313 sends the selection signal (Sa, Sb) indicating “1” to the first selection circuit 311 and the second selection circuit 312. Output to. As a result, the request (B) is inputted to the first memory 330 (D0) and the third memory 332 (D2), and the request (A) is sent to the second memory 331 (D1) and the fourth memory 333 (D3). ) Is entered.

The input values (Va, Vb) from item number “5” to item number “12” mean that one of request (A) and request (B) is established, and the other is not established.
In the case of the item numbers “5”, “7”, “9”, and “11” (SECTP = 0 or 2), the selection control circuit 313 outputs a selection signal (Sa) designating a valid request to the first selection circuit 311. . As a result, a valid request is input to the first memory 330 (D0) and the third memory 332 (D2).
In the case of the item numbers “6” “8” “10” “12” (SECTP = 1 or 3), the selection control circuit 313 outputs a selection signal (Sb) designating a valid request to the second selection circuit 312. . As a result, a valid request is input to the second memory 331 (D1) and the fourth memory 333 (D3).

The input value (Va = 0, Vb = 0) of the item number “13” means that neither the request (A) nor the request (B) is established.
In this case, the selection control circuit 313 outputs selection signals (Sa, Sb) indicating arbitrary values to the first selection circuit 311 and the second selection circuit 312 regardless of the value of the sector pointer (SECTP).

FIG. 7 is a table showing an example of input / output values of the buffer management circuit 350 and input values of the memories (330 to 333) according to the first embodiment.
An example of input / output values of the buffer management circuit 350 and input values of the memories (330 to 333) according to the first embodiment will be described with reference to FIG. Note that the buffer management circuit 350 may store and use the table shown in FIG. 7 as data.

The input values (Va = 1, Vb = 1) from item number “1” to item number “4” mean that requests (A, B) are established at the same time.
In this case, the buffer management circuit 350 selects two memories (WEx) from the first memory 330 to the fourth memory 333 according to the value of the sector pointer (SECTP). Then, the buffer management circuit 350 outputs a write enable signal indicating “1” to the two selected memories, and outputs a write enable signal indicating “0” to the remaining two memories.
For example, in the case of the item number “1”, the buffer management circuit 350 outputs the write enable signal “1” to the first memory 330 (WE0) and the second memory 331 (WE1), and the third memory 332 ( The write enable signal “0” is output to WE2) and the fourth memory 333 (WE3).
The write enable signal indicating “1” is a signal for storing a request, and the write enable signal indicating “0” is a signal for not storing a request.

The input values of the item numbers “5” to “12” mean that one of the request (A) and the request (B) is established and the other is not established.
In this case, the buffer management circuit 350 selects one memory (WEx) from the first memory 330 to the fourth memory 333 according to the value of the sector pointer (SECTP). Then, the buffer management circuit 350 outputs a write enable signal indicating “1” to one selected memory, and outputs a write enable signal indicating “0” to the remaining three memories.

The input value (Va = 0, Vb = 0) of the item number “13” means that neither the request (A) nor the request (B) is established.
In this case, the buffer management circuit 350 outputs a write enable signal indicating “0” to all the memories (330 to 333) regardless of the value of the sector pointer (SECTP).

Here, a specific example of the storing operation for storing the request (A, B) will be described based on FIG. 6 and FIG.
In item number “1” in FIGS. 6 and 7, the request (A, B) is simultaneously established.
In the item number “1” in FIG. 6, the request (A) is input to the first memory 330 (D0) and the third memory 332 (D2), and the second memory 331 (D1) and the fourth memory are input. The request (B) is input to 333 (D3).
In the item number “1” of FIG. 7, the write enable signal “1” is input to the first memory 330 (WE0) and the second memory 331 (WE1), and the third memory 332 (WE2) and the fourth memory The write enable signal “0” is input to the memory 333 (WE3).
As a result, the first memory 330 stores the request (A), the second memory 331 stores the request (B), and the third memory 332 and the fourth memory 333 store the request (A, B). I don't remember.
In the case of item number “2” to item number “3”, the same storage operation is performed, and requests (A, B) established at the same time are simultaneously stored in different memories.
In the case of item number “5” to item number “12”, only one of the requests (A, B) is established, and only the established request is stored in the memory.
In the case of the item number “13”, since the request (A, B) is not established, the request (A, B) is not stored in the memory.

FIG. 8 is a table showing an example of input / output values of the buffer management circuit 350 according to the first embodiment.
The operation of the buffer management circuit 350 after the above storage operation is performed will be described with reference to FIG. The buffer management circuit 350 may store and use the table shown in FIG. 8 as data.

In the case of the item number “1”, the request (A, B) is stored in the first memory 330 (WE0) and the second memory 331 (WE1) (see FIG. 7).
The buffer management circuit 350 sets the sector pointer (SECTP) value “0” to “0” so that the next request (A, B) is not stored in the first memory 330 (WE0) and the second memory 331 (WE1). Add 2 ”. That is, the buffer management circuit 350 updates the value of the sector pointer to “2 (= 0 + 2)”.
Further, the buffer management circuit 350 does not update the value of the write pointer (WPTRa, WPTRb). The next request (A, B) is a third memory 332 (WE2) identified by the same number as the storage area of the first memory 330 and the second memory 331 in which the current request (A, B) is stored. ) And the fourth memory 333 (WE3). For example, when the current request (A, B) is stored in the first storage area of the first memory 330 and the second memory 331, the next request (A, B) is the third memory 332 and the first memory 332 It is stored in the first storage area of the fourth memory 333. That is, when the memory (332, 333) equal to or greater than the maximum number of requests (two or more) input to the trace buffer 300 remains without being specified by the write enable signal, the buffer management circuit 350 uses the write pointer (WPTRa, WPTRb) is not updated.

In the case of the item number “2”, the request (A, B) is stored in the second memory 331 (WE1) and the third memory 332 (WE2) (see FIG. 7).
The buffer management circuit 350 sets the sector pointer (SECTP) value “1” to “1” so that the next request (A, B) is not stored in the second memory 331 (WE1) and the third memory 332 (WE2). Add 2 ”. That is, the buffer management circuit 350 updates the value of the sector pointer to “3 (= 1 + 2)”.
The buffer management circuit 350 does not update the value of the write pointer (WPTRb). One request (A) of the next requests (A, B) is identified by the same number as the storage areas of the second memory 331 and the third memory 332 in which the current request (A, B) is stored. This is to be stored in the storage area of the fourth memory 333.
The buffer management circuit 350 adds “1” to the value of the write pointer (WPTRa). This is to prevent the remaining request (A) from the next request (A, B) from being overwritten in the storage area of the first memory 330 in which the previous request is stored.

In the case of the item number “3”, the request (A, B) is stored in the third memory 332 (WE2) and the fourth memory 333 (WE3) (see FIG. 7).
The buffer management circuit 350 sets the sector pointer (SECTP) value “2” to “2” so that the next request (A, B) is not stored in the third memory 332 (WE2) and the fourth memory 333 (WE3). Add 2 ”. However, since the value of the sector pointer is any one of “0” to “3”, the value of the sector pointer after adding “2” is not “4” but “0”. That is, the buffer management circuit 350 updates the value of the sector pointer to “0”.
The buffer management circuit 350 adds “1” to the value of the write pointer (WPTRa, WPTRb). This is to prevent subsequent requests from being overwritten in the storage area in which the previous request is stored among the storage areas of the first memory 330 to the fourth memory 333. That is, when one request is stored in each memory (330 to 333), the buffer management circuit 350 updates the value of the write pointer (WPTRa, WPTRb). In this addition, if the last value of the entry is incremented by 1 in this addition, the pointer value returns to 0.

In the case of the item number “4”, the request (A, B) is stored in the fourth memory 333 (WE3) and the first memory 330 (WE0) (see FIG. 7).
The buffer management circuit 350 sets the sector pointer (SECTP) value “3” to “3” so that the next request (A, B) is not stored in the fourth memory 333 (WE3) and the first memory 330 (WE0). Add 2 ”. However, since the value of the sector pointer is one of “0” to “3”, the value of the sector pointer after adding “2” is “1” instead of “5”. That is, the buffer management circuit 350 updates the value of the sector pointer to “1”.
The buffer management circuit 350 adds “1” to the value of the write pointer (WPTRb). This is to prevent subsequent requests from being overwritten in the storage area of the fourth memory 333 in which the current request (A) is stored.
The buffer management circuit 350 does not update the value of the write pointer (WPTRa). The next request (A, B) is stored in the second memory 331 and the third memory 332 identified by the same number as the storage area of the first memory 330 in which the current request (B) is stored. It is for doing so.

In the case of the item number “5” to the item number “12”, the buffer management circuit 350 updates the sector pointer (SECTP) and the write pointer (WPTRa, WPTRb) in the same manner as the item numbers “1” to “4”. To do.
However, since the number of requests stored in the memories (330 to 333) is “1”, the value added to the sector pointer is “1”.

  In the case of the item number “13”, since there is no request stored in the memory (330 to 333), the buffer management circuit 350 does not update the sector pointer (SECTP) and the write pointer (WPTRa, WPTRb).

  By appropriately updating the sector pointer (SECTP) and the write pointer (WPTRa, WPTRb) by the buffer management circuit 350, the amount of requests stored in the memories (330 to 333) can be equalized. That is, it is possible to prevent the request storage destination from being concentrated in a specific memory. As a result, there is no free storage area from the specific memory, and it is possible to prevent a new request from being overwritten before a request is read from the storage area of the specific memory. As a result, the trace buffer 300 can efficiently use the storage area of each memory and store more requests.

According to the first embodiment, for example, the following effects can be obtained.
Even when point-to-point interconnect transactions (for example, requests) occur simultaneously, they can be captured in the trace buffer and recorded without leaking information necessary for system performance analysis.
By inserting a circuit (for example, request suppression circuit 200) that suppresses simultaneous generation of transactions into an interconnect circuit (for example, DRAM controller 130, CPU bridge 140), the number of transactions that can be simultaneously written in the trace buffer Even if many transactions occur at the same time, some transactions can be enabled to reduce the number of transactions that occur simultaneously.
Since the simultaneous generation of transactions is suppressed, signal lines between the interconnect circuit and the trace buffer can be reduced. When one transaction is selected from two transactions, the number of signal lines is reduced to ½ of the conventional number. When one transaction is selected from four transactions, the number of signal lines is ¼ of the conventional number. Can be reduced. However, the effect of reducing the number of signal lines varies depending on the layout method of the interconnect circuit.

The first embodiment may be in the following form.
The request is an example of trace data (target data) stored in the trace buffer 300. The trace buffer 300 may store data other than requests.
Each of the request suppression circuits 200 of the DRAM controller 130 and the CPU bridge 140 inputs three or more data established simultaneously, suppresses at least one of the data, and stores one or a plurality of remaining data in the trace buffer 300. You may output.
The trace buffer 300 may input three or more data at the same time and simultaneously store the three or more data input at the same time.
The number of memories provided in the trace buffer 300 may be two or three. The number of memories provided in the trace buffer 300 may be five or more.
The following control may be performed. Instead of using the second write point register 353, a circuit for subtracting 1 from the value of the first write point register 352 is used, or instead of using the first write point register 352, the second write point register 353 A circuit that adds 1 to the value is used. Then, the addition / subtraction condition is obtained from the sector point register 351 and controlled so that the value of the port Aw of the memory (330 to 334) to be written is equivalent to the operation of FIG.

100 integrated circuit, 101 bus controller, 102 DMA controller, 103
SRAM controller, 104 I / O bridge, 109 bus, 110 CPU, 120 cache memory, 121W, 121R signal line, 122W, 122R signal line, 130 DRAM controller, 140 CPU bridge, 200 request suppression circuit, 201A, 201B signal line, 210 First selection circuit, 220 Signal processing circuit, 221 Mode register, 222 Count register, 231 First AND circuit, 232 Second AND circuit, 300 Trace buffer, 311 First selection circuit, 312 Second selection Circuit, 313 selection control circuit, 320 first input register, 321 second input register, 322 third input register, 323 fourth input register, 330 first memory, 331 second memory, 332 third Memory 333 4th Memory, 340 output circuit, 341 output register, 350 buffer management circuit, 351 sector point register, 352 first write point register, 353 second write point register.

Claims (7)

A memory selection value storage unit for storing a memory selection value for selecting at least one of the plurality of memories;
A data input unit for inputting one or more target data;
Based on the memory selection value stored in the memory selection value storage unit, the same number of memories as the number of target data input by the data input unit are used as the memory group for storing the one or more target data. A memory group selection unit for selecting from the memories of
Based on the number of target data input by the data input unit, the memory selection value stored in the memory selection value storage unit is selected to select a memory other than the memory group selected by the memory group selection unit. A memory selection value updater for updating to the value of
A data trace circuit comprising: Each of the plurality of memories comprises a plurality of entries;
The data trace circuit includes:
An entry designation value storage unit for storing an entry designation value for designating each entry of the plurality of memories;
An entry designating unit that designates an entry that stores one target data of the one or more target data in each memory of the memory group based on the entry specified value stored in the entry specified value storage unit When,
When target data is stored one by one in the plurality of memories, an entry specified value update unit that updates the entry specified value stored in the entry specified value storage unit;
The data trace circuit according to claim 1, further comprising: The entry specified value update unit does not update the entry specified value when a memory equal to or more than the maximum number of target data input to the data input unit remains without being selected by the memory group selection unit. The data trace circuit according to claim 2. A data trace circuit according to any one of claims 1 to 3 and one or more data suppression circuits,
Each data suppression circuit
A data suppression input section for inputting a plurality of data;
A data selection unit that selects any of the plurality of data input by the data suppression input unit;
A data suppression output unit that outputs the data selected by the data selection unit to the data trace circuit as the target data;
An integrated circuit comprising: Each data suppression circuit includes a mode value storage unit that stores a mode value indicating whether or not to operate the data suppression function.
The data selection unit selects any one of the plurality of data when the mode value stored in the mode value storage unit indicates a value for causing the data suppression function to function. The integrated circuit according to claim 4. 5. The data suppression circuit includes a suppression number counting unit that counts the number of data that is not output by the data suppression output unit among the plurality of data input by the data suppression input unit. The integrated circuit according to claim 5. A data trace method using a data trace circuit comprising a memory selection value storage unit, a data input unit, a memory group selection unit, and a memory selection value update unit,
The memory selection value storage unit is a storage unit that stores a memory selection value for selecting at least one of a plurality of memories.
The data input unit inputs one or more target data,
Based on the memory selection value stored in the memory selection value storage unit, the memory group selection unit uses the same number of memories as the number of target data input by the data input unit as the one or more target data. Select from the plurality of memories as a memory group to be stored,
The memory selected value is stored in the memory selection value storage unit by the memory group selection unit based on the number of target data input by the data input unit. A data tracing method comprising updating to a value for selecting a memory other than a group.

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