JP6054688B2 - Programmable array control circuit and programmable array control method - Google Patents

Description

  The present invention relates to a circuit and method for controlling a programmable array.

  The programmable array is one of semiconductor elements that can constitute a desired logic circuit at the designer's hand.

  In the programmable array, the following procedure is required to make the user circuit operable after the power is turned on. That is, (1) User circuit configuration information is read from an external memory into a built-in RAM (Random Access Memory). (2) The configuration information of the read user circuit is expanded and configured on the RAM. (3) The user circuit is initialized by a reset signal supplied from the outside.

  After the above procedure is completed, initial values are set in the registers of the user circuit, and the operation of the user circuit starts.

  In the related art, when the development (configuration) of the user circuit on the programmable array is completed, a signal notifying the completion is supplied to the reset circuit, and the reset circuit generates a reset signal from the configuration end signal, and the user The circuit was being initialized.

  Further, it takes time until the reset signal supplied from the outside is canceled in order for the user circuit to be operable.

  In such a programmable array configuration, it is necessary to wait for the operation of the external reset circuit in the initialization process of the user circuit.

  Therefore, there is a problem that it takes a long time until the user circuit becomes operable after the configuration is completed.

  Patent Document 1 discloses a field programmable gate array (FPGA) in which a fixed region is provided outside a user region where a user circuit is developed, and the fixed region has a reset circuit. The reset circuit provided in the fixed area generates an initialization signal based on a signal notifying the end of the configuration operation, and supplies the initialization signal to the user area to initialize the user circuit. Thereby, input / output terminals from the FPGA to the external reset circuit can be reduced.

  However, in the configuration in which the clock for controlling the operation timing is shared between the user area and the fixed area, such as the programmable gate array disclosed in Patent Document 1, the rising edge of the clock and the edge of the control signal may collide. is there.

  That is, when the timing of releasing the reset signal that initializes the user area and the rising edge of the clock overlap, a state occurs in which the counter value becomes indefinite.

  For example, in a flip-flop, when a reset release and a clock rise collide, the value indicated by the flip-flop becomes indefinite. In such a state, the counter does not operate normally.

  For this reason, it is necessary to control so that the period during which the reset signal is released is separated from the clock edge period. However, in a programmable array in which a large number of functional blocks are integrated, it is difficult to temporally separate the operation of each element.

  In response to this problem, Patent Document 2 discloses a semiconductor integrated circuit that performs control to stop the clock operation before and after reset so that the clock edge and the reset release edge do not overlap.

JP-A-10-209281 JP 2006-163531 A

  In the semiconductor integrated circuit disclosed in Patent Document 2, each time from when the supply of the clock is stopped to the release of the reset signal and from the release of the reset to the restart of the supply of the clock is counted as a control clock number (for example, 128). ) To measure.

  That is, the semiconductor integrated circuit disclosed in Patent Document 2 waits for the stability of the phase synchronization circuit to provide a sufficient length of time required for synchronization of the clock before and after the reset is released. Controls to stop the clock operation. This avoids a collision between the reset release and the clock edge, and ensures the stability of the reset release.

  However, the semiconductor integrated circuit disclosed in Patent Document 2 measures a predetermined number of clocks with a counter in a clock / reset control circuit. That is, the time until the user circuit becomes operable is limited by a predetermined length by counting the number of clocks and cannot be shortened. Therefore, it is difficult to increase the speed further.

  The present invention has been made in view of the above points, and an object thereof is to provide a programmable array control circuit and a programmable array control method that enable a user circuit to operate in a short time.

  In order to achieve the above object, a programmable array control circuit according to the present invention is a programmable array control circuit that operates a user circuit by developing the user circuit in the user circuit unit, and the user circuit is expanded in the user circuit unit. Reset signal control means for issuing a reset signal for initializing the user circuit after completion, and clock line control means for issuing a clock permission signal for driving the clock line of the user circuit section when the output of the reset signal is completed. It is characterized by having.

  In order to achieve the above object, a programmable array control method of the present invention is a method for controlling a programmable array having a user circuit unit, and the step of developing the user circuit in the user circuit unit and the development of the user circuit are completed. The method includes a step of issuing a reset signal for initializing the user circuit later, and a step of issuing a clock permission signal for driving the clock line of the user circuit unit when the output of the reset signal is completed.

  According to the present invention, the user circuit can be operated in a short time after the development of the user circuit configuration information.

1 shows an example of a configuration of a programmable array according to a first embodiment of the present invention. It is a flowchart which shows an example of the procedure of the control method of the programmable array which concerns on the 1st Embodiment of this invention. An example of the structure of the programmable array which concerns on the 2nd Embodiment of this invention is shown. An example of the structure of the reset control part which concerns on the 2nd Embodiment of this invention is shown. It is a timing chart explaining an example of operation of a programmable array concerning a 2nd embodiment of the present invention. It is a timing chart which shows an example of operation of a programmable array control circuit concerning a 2nd embodiment of the present invention. It is a timing chart which shows an example of operation of a programmable array control circuit concerning a 2nd embodiment of the present invention. An example of the structure of the bit counter contained in the programmable array which concerns on the 2nd Embodiment of this invention is shown. It is a timing chart explaining an example of operation of a bit counter contained in a programmable array in related technology. It is a timing chart explaining an example of operation | movement of the bit counter contained in the programmable array contained in the 2nd Embodiment of this invention. An example of the structure of the flip-flop contained in the programmable array which concerns on the 1st implementation failure of this invention is shown. It is a timing chart explaining an example of operation | movement of the flip-flop contained in the programmable array in related technology. It is a timing chart explaining an example of operation of a flip flop contained in a programmable array concerning a 2nd embodiment of the present invention. An example of the structure of the programmable array which concerns on the 3rd Embodiment of this invention is shown. The example of the structure of the interface of the programmable array which concerns on the 3rd Embodiment of this invention is shown. It is a timing chart explaining an example of operation of a programmable array concerning a 3rd embodiment of the present invention.

The best mode for carrying out the invention will be described in detail with reference to the drawings. However, the present invention is not limited to the embodiments described below.
[First Embodiment]
[Constitution]
FIG. 1 is a block diagram showing an example of a configuration of a programmable array according to the first embodiment of the present invention.

  With reference to FIGS. 1 and 2, the operation of the programmable array according to the present embodiment will be described.

  In FIG. 1, the programmable array includes a reset control unit 3 and a user circuit unit 4, and the reset control unit 3 includes a reset pulse control unit 31 and a clock line control unit 33.

  When a user circuit is constructed (configured) in the user circuit unit 4, user circuit configuration information is input to the user circuit unit 4 from the outside of the programmable array. When the development of the user circuit is completed, the user circuit unit 4 requests the reset pulse control unit 31 to reset.

  The reset pulse control unit 31 outputs a reset pulse to the user circuit unit 4 (FIG. 2, step S101). When the reset pulse output is completed (FIG. 2, step S102 YES), the reset pulse control unit 31 notifies the clock line control unit 33 of the completion of the reset pulse and requests the user circuit unit 4 to drive the clock line.

  The clock line control unit 33 outputs a clock permission pulse signal that permits driving of the clock line to the user circuit unit 4 (FIG. 2, step S103). When receiving the clock permission pulse signal, the user circuit unit 4 drives the clock line of the user circuit unit 4 (FIG. 2, step S104).

  The reset control unit 3 in the programmable array according to the present embodiment outputs a reset signal for initializing the user circuit 4, and when the output of the reset signal is completed, instructs the user circuit 4 to drive the clock line of the user circuit 4. Issue. Thereby, the release of the reset pulse and the clock edge are temporally separated.

Further, unlike the semiconductor integrated circuit disclosed in Patent Document 2, it is not necessary to wait for a predetermined time set sufficiently long for stable clock operation until the start of clock driving, and output of the reset signal can be completed. After confirmation, for example, driving of the clock can be started with several counts. For this reason, a programmable array is provided in which the start-up is fast and the state of the user circuit is stable by avoiding the collision between the reset release edge and the rising edge of the clock.
[Second Embodiment]
[Constitution]
[Programmable array]
FIG. 3 is a block diagram showing an example of the configuration of a programmable array according to the second embodiment of the present invention.

  The programmable array includes a memory unit 1, a configuration control unit 2, a reset control unit 3, and a user circuit unit 4.

  The memory unit 1 includes a non-volatile memory, and can be stored without losing internal data even when power is not supplied. The memory unit 1 captures and holds user circuit configuration information a from the outside.

  When the user circuit is constructed in the user circuit unit 4, the memory unit 1 outputs the user circuit configuration information c to the user circuit unit 4 using the configuration start signal b input from the configuration control unit 2 as a trigger. The memory unit 1 outputs a data transfer completion signal d to the configuration control unit 2 when the transfer of the user circuit configuration information c is completed.

  When the power supply voltage supplied to the programmable array reaches an operable voltage value after the power is turned on, the configuration control unit 2 outputs a configuration start signal b to the memory unit 1. After the configuration control unit 2 inputs the data transfer completion signal d from the memory unit 1, the user circuit unit 4 outputs the user circuit development completion signal i when the user circuit development is completed. When receiving the user circuit development completion signal i, the configuration control unit 2 outputs a reset control request signal e to the reset control unit 3.

  When the reset control request signal e is input from the configuration control unit 2, the reset control unit 3 outputs a reset pulse signal f, a data permission pulse signal g, and a clock permission pulse signal h to the user circuit unit 4.

The user circuit unit 4 expands the user circuit therein based on the user circuit configuration information c input from the memory unit 1. When the user circuit unit 4 completes the development of the user circuit, the user circuit unit 4 outputs a user circuit development completion signal i to the configuration control unit 2. The user circuit unit 4 further initializes the user circuit with the reset pulse signal f input from the reset control unit 3. Further, the user circuit unit 4 starts driving the data line in the user circuit by the input of the data permission pulse signal g, and starts driving the clock line by the input of the clock permission pulse signal h.
[Reset controller]
FIG. 4 shows an example of the configuration of the reset control unit according to the second embodiment of the present invention.

  The reset control unit 3 includes a reset pulse control unit 31, a data line control unit 32, and a clock line control unit 33.

  When the reset control request signal e output from the configuration control unit 2 is input, the reset pulse control unit 31 outputs the reset pulse signal f to the user circuit unit 4. Subsequently, the reset pulse control unit 31 outputs a reset pulse output completion signal 3 a to the data line control unit 32.

  When the reset pulse output completion signal 3 a output from the reset pulse control 31 is input, the data line control unit 32 outputs a data permission pulse signal g that permits driving of the data line to the user circuit unit 4. Subsequently, the data line control unit 32 outputs a data permission pulse output completion signal 3 b to the clock line control unit 33.

When the data permission pulse output completion signal 3b output from the data line control section 32 is input, the clock line control section 33 outputs a clock permission pulse signal h that permits driving of the clock line to the user circuit section 4. .
[Operation]
Next, the operation of the control circuit of the programmable array according to the present embodiment will be described in detail with reference to the timing charts and block diagrams of FIGS.
[Programmable array]
FIG. 5 is a timing chart for explaining an example of the operation of signals transmitted and received in the programmable array according to this embodiment shown in the block diagram of FIG.

  User circuit configuration information a is taken in and stored in the memory unit 1 from the outside.

  When the programmable array is powered on and reaches a predetermined operable voltage, the configuration control unit 2 outputs a configuration start signal b to the memory unit 1.

  When the configuration start signal b is input, the memory unit 1 outputs the user circuit configuration information stored therein as user circuit configuration information c to the user circuit unit 4. When the memory unit 1 completes the transfer of all data of the user circuit configuration information, the memory unit 1 outputs a data transfer completion signal d to the configuration control unit 2.

  The user circuit unit 4 expands the user circuit based on the user circuit configuration information, and outputs the user circuit expansion completion signal i to the configuration control unit 2 when the expansion of the user circuit is completed.

  When receiving the user circuit development completion signal i, the configuration control unit 2 outputs a reset control request signal e to the reset control unit 3.

  When the reset control request signal e output from the configuration control unit 2 is input, the reset control unit 3 continuously transmits a reset pulse signal f, a data permission pulse signal g, and a clock permission pulse signal h to the user circuit unit 4. And output.

The rise timing of each signal is controlled by the clock timing indicated by the clock cycle.
[Reset controller]
FIG. 6 is a timing chart for explaining an example of the operation of signals transmitted and received in the reset control unit 3 according to this embodiment shown in the block diagram of FIG.

  First, a reset control request signal e is output from the configuration control unit 2 to the reset pulse control unit 31.

  When the reset control request signal e is input, the reset pulse control unit 31 outputs a reset pulse signal f to the user circuit unit 4, and when the reset pulse is completed, subsequently outputs a reset pulse to the data line control unit 32. A completion signal 3a is output.

  When the data line control unit 32 receives the reset pulse output completion signal 3 a output from the reset pulse control unit 31, the data line control unit 32 outputs a data permission pulse signal g to the user circuit unit 4, and subsequently to the clock line control unit 33. On the other hand, a data permission pulse output completion signal 3b is output.

  When receiving the data permission pulse output completion signal 3 b from the data line control unit 32, the clock line control unit 33 outputs a clock permission pulse signal h to the user circuit unit 4.

The rise timing of each signal is controlled by the clock timing indicated by the clock cycle.
[User circuit section]
FIG. 7 is a timing chart for explaining an example of the operation from the initialization of the user circuit to the activation of the user circuit for signals transmitted and received in the user circuit unit according to the present embodiment.

  Normally, a reference value or the like that is referred to at the time of activation is indefinite if the user circuit is simply developed on the memory. When the user circuit is activated, this indefinite state needs to be initialized by reset processing.

  The user circuit is initialized by the input of the reset pulse signal f output from the reset control unit 3.

  Next, in response to the input of the data permission pulse signal g output from the reset control unit 3, the data line in the user circuit unit 4 is driven from the initial state to a value necessary for the user circuit to operate.

  Further, a clock necessary for timing control of the operation of the element is driven on the clock line in the user circuit unit 4 by the input of the clock permission pulse signal h output from the reset control unit 3.

Next, the configuration and procedure will be specifically described with an example applicable as a user circuit developed in the user circuit unit 4.
[Bit counter example]
An example of the operation when a 4-bit counter is configured as a user circuit developed in the user circuit unit 4 will be described with reference to FIGS.

  For comparison, FIG. 9 shows an example of the operation when the present invention is not applied.

  FIG. 8 shows an example of the configuration of a 4-bit counter according to the present embodiment.

  The reset pulse signal f output from the reset control unit 3 is input to the CLR (clear) input terminal of the 4-bit counter 61.

  In addition, when the present invention is not applied, clock drive control is not performed. Therefore, a clock line is input to the CLK input terminal of the 4-bit counter 61 in the user circuit unit 4 after the user circuit is developed. Yes.

  FIG. 9 shows an example of signal operation in the 4-bit counter 61 when the present invention is not applied.

  As shown in FIG. 9, in the programmable array to which the present invention is not applied, the release timing of the reset pulse signal f and the timing of the rising edge of the clock may collide. When such a collision occurs, a timing error occurs in the bit counter. At this time, the counter internal state changed from the indefinite state to the initial state by the reset pulse signal f changes to the indefinite state. That is, the bit counter 61 is in an indefinite state at the start of the operation, and does not perform a normal count operation from “0”.

  Next, an example of the operation of a 4-bit counter as a user circuit developed in the user circuit unit 4 when the present invention is applied to a programmable array will be described with reference to FIGS.

  After the user circuit is developed in the user circuit unit 4, the reset pulse signal f is input from the reset control unit 3, and the 4-bit counter 61 is initialized.

  Next, the clock permission pulse signal h is input, and the input of the clock into the user circuit unit 4 is started.

Since the clock operation starts after the reset pulse signal is input and the initialization of the user circuit is completed, the release of the reset pulse signal and the rising edge of the clock are temporally separated. This eliminates the possibility of timing errors as illustrated in FIG. 9, and the bit counter 61 can always perform a normal counting operation.
[Example of flip-flop]
An example of operation when a flip-flop is configured as a user circuit developed in the user circuit unit 4 will be described with reference to FIGS.

  For comparison, FIG. 12 shows an example of the operation when the present invention is not applied.

  FIG. 11 shows an example of the configuration of the flip-flop according to this embodiment.

  The reset pulse signal f output from the reset control unit 3 is input to the CLR input terminal of the flip-flop 91 of FIG.

  When the present invention is not applied, data and clock drive control is not performed. Therefore, in the user circuit unit 4, the clock line is input to the CLK terminal of the flip-flop 91 after the user circuit is developed. Further, after the user circuit is developed, data is driven at an arbitrary timing and input to the D input terminal.

  FIG. 12 shows an example of the signal operation in the flip-flop 91 when the present invention is not applied.

  As shown in FIG. 12, in the programmable array to which the present invention is not applied, the release timing of the reset pulse signal f and the timing of the rising edge of the clock may collide. Furthermore, the change point of the data line of data input at an arbitrary timing may collide with the timing of the rising edge of the clock. When such a collision occurs, a timing error occurs in the flip-flop. At this time, the internal state of the flip-flop changed from the indefinite state to the initial state by the reset pulse signal f changes to the indefinite state at each timing. That is, since the flip-flop 91 can be in an indefinite state at the start of operation and at the time of data input, the flip-flop does not operate normally when it changes to such a state.

  Next, an example of the operation of a flip-flop as a user circuit developed in the user circuit unit 4 when the present invention is applied to a programmable array will be described with reference to FIGS.

  After the user circuit is developed in the user circuit unit 4, the reset pulse signal f is input from the reset control unit 3, and the flip-flop 91 is initialized.

  Next, in response to the data input, the data permission pulse signal g is input, the data line is driven, and the data line in the user circuit unit 4 is changed from the initial state to the driven state.

  Further, the clock permission pulse signal h is input, the clock line is driven, and the input of the clock into the user circuit unit 4 is started.

  After the reset pulse signal is input and the initialization of the user circuit is completed, if there is data input, the data enable pulse signal is input to change the state of the data line, and the clock enable pulse signal is input to Since the operation starts, the release of the reset pulse, the data change by the data line drive, and the clock edge change by the clock line drive are separated in time. This eliminates the possibility of timing errors as illustrated in FIG. 12, and the flip-flop 91 always operates normally.

  Furthermore, for the change in the state of the data line, it is necessary to stop the clock line in the user circuit unit 4 again in order to avoid a collision between the clock edge and the change point of the data line. For this reason, the data permission pulse signal g after the next time stops the clock line in the user circuit unit 4 before changing the state of the data line in the user circuit unit 4.

  The clock line in the user circuit unit 4 starts to operate again when the clock permission pulse signal h is input. Since the operation of the clock line is started by the clock permission pulse signal h issued after the change of the data line in the user circuit unit 4 is completed, the collision between the data line change point and the clock edge can be avoided. .

  The programmable array control circuit according to the present embodiment stores user circuit configuration information in the memory unit 1 in advance, and the memory unit 1 transfers the user circuit configuration information to the user circuit unit 4 according to an instruction from the configuration control unit 2. The configuration control unit 2 informs the reset control unit 3 of the completion of the development of the user circuit information in the user circuit unit 4. The reset control unit 3 first outputs a reset pulse for initializing the user circuit to the user circuit unit 4 according to an instruction from the configuration control unit 2, and then drives a data line to operate the user circuit. Finally, the clock line is driven.

Thereby, the user circuit unit 4 is initialized by a reset generated inside the programmable array, and elements such as flip-flops and counters configured as user circuits can operate without causing a timing error. Further, it becomes unnecessary to supply a reset signal from an external circuit to the user circuit unit 4, and the user circuit becomes operable immediately after the configuration is completed.
[Third Embodiment]
FIG. 14 is a block diagram showing an example of a configuration of a programmable array according to the third embodiment of the present invention.

  The programmable array according to the third embodiment is obtained by adding an interface 43 for data input / output with the outside to the user circuit unit 4 in addition to the programmable array according to the second embodiment. Since the other configuration is the same as that of the second embodiment, the description thereof is omitted.

  In the programmable array according to the third embodiment, the interface 43 included in the user circuit unit 4 captures, for example, a processor command j output from an external processor.

  FIG. 15 shows an example of the configuration of the interface 43 included in the user circuit unit 4 of the programmable array according to the third embodiment.

  The interface 43 includes a decode circuit unit 41 and a reset pulse generation unit 42.

  The decode circuit unit 41 receives a processor command j from an external processor and decodes the processor command j. The signal obtained by decoding is output to the reset pulse generator as a reset command 4a.

  The reset pulse generation unit 42 generates a reset pulse based on the reset command 4a input from the decode circuit unit 41, and outputs it as a reset pulse 4b in the user circuit.

  At this time, the clock line in the user circuit unit 4 stops the clock in order to avoid the collision between the release of the reset pulse 4b and the clock edge. The reset pulse generator outputs a clock stop pulse signal 4c.

  In the second embodiment, the reset is issued to the user circuit only at the timing immediately after the user circuit configuration information is expanded. However, in the programmable array according to the present embodiment, the user circuit is in normal operation. Even if it exists, it can be reset from an external processor at an arbitrary timing.

  In the third embodiment, an interface is provided in the user circuit and a processor command input from the outside is decoded. However, the present invention is not limited to this.

  A processor may be mounted in the user circuit, and a reset pulse may be generated according to an instruction from the outside and output to the user circuit.

  According to the programmable array of the third embodiment, the user circuit is temporarily removed from the user circuit unit in order to return to the initial state when the user circuit changes to an indeterminate state due to factors such as mixed noise. There is no need to re-deploy the user circuit, and it may be instructed to issue a reset pulse from the outside. Thereby, the user circuit which changed to the indefinite state can be quickly returned to the initial state.

  FIG. 16 shows an example of the operation of signals in the interface 43 when a processor command j is input from the outside.

  A reset pulse 4b is issued by a processor command j input from the outside, and the user circuit is initialized. At this time, the clock in the user circuit unit 4 is stopped, and the occurrence of an indefinite state due to the release of the reset pulse and the collision with the clock edge is suppressed. When the clock permission pulse signal is input again, the clock operation resumes.

  The programmable array control circuit according to the present embodiment sequentially performs reset output, data line driving, and clock line driving for the user circuit, and makes the user circuit usable at the shortest timing at which no timing error occurs. Therefore, the user circuit can operate immediately after the user circuit configuration information is expanded.

  Moreover, since the programmable array control circuit according to the present embodiment generates a reset by the reset control unit, an external reset control circuit for the user circuit is not necessary.

  Furthermore, since the programmable array control circuit according to the present embodiment can store the user circuit configuration information in advance by configuring the memory unit with a nonvolatile memory, the user circuit configuration information can be transferred immediately after the power is turned on. Can be deployed.

  The present invention is preferably applied to a programmable array in which a user's desired program is developed and operated on a memory. The present invention is applicable to a small and stable high-speed programmable array that is stable in operation with respect to a reset signal that starts to be used in a short time after the power is turned on and that does not require an external reset control circuit.

DESCRIPTION OF SYMBOLS 1 Memory part 2 Configuration control part 3 Reset control part 4 User circuit part 31 Reset pulse control part 32 Data line control part 33 Clock line control part 41 Decoding circuit part 42 Reset pulse generation part 43 Interface 61 4 bit counter 91 Flip-flop

Claims (4)

A programmable array control circuit for operating the user circuit by developing the user circuit in a user circuit unit,
A reset signal control means for issuing a reset signal for initializing the user circuit after deployment of the user circuit to the user circuit unit is completed;
A data line control means for issuing a data line permission signal for driving the data line of the user circuit after the output of the reset signal is completed;
A clock line control means for issuing a clock permission signal for driving the clock line of the user circuit unit after the output of the reset signal is completed ;
After the data line permission signal output is completed, the clock line control means issues the clock permission signal,
The programmable array control circuit, wherein the data line permission signal issued again after the data line permission signal is issued stops driving the clock line of the user circuit unit . An interface for inputting processor commands from the outside;
The interface issues a reset signal that re-initializes the user circuit based on the processor command,
The programmable array control circuit according to claim 1 , wherein the re-reset signal stops driving a clock line of the user circuit. A method for controlling a programmable array having a user circuit unit,
Developing a user circuit in the user circuit unit;
Issuing a reset signal for initializing the user circuit after deployment of the user circuit is completed;
Issuing a data line permission signal for driving a data line of the user circuit after the output of the reset signal is completed;
Issuing a clock permission signal for driving a clock line of the user circuit unit after the output of the reset signal is completed;
After the data line permission signal is issued, when the data line permission signal is issued again, stopping driving the clock line of the user circuit unit,
The method of controlling a programmable array, wherein the clock permission signal is issued after the data line permission signal output is completed . Entering processor commands from outside,
Issuing a re-reset signal to re-initialize the user circuit based on the processor command;
The method of controlling a programmable array according to claim 3, further comprising a step of stopping driving of the clock line of the user circuit by the re-reset signal .

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