JP6060775B2 - Reset circuit - Google Patents

Description

  The present invention relates to a reset circuit.

  Conventionally, in order to prevent abnormal operation such as system runaway due to power supply voltage drop, there is known a reset IC that monitors the power supply voltage, generates a low level output when the voltage falls below a predetermined voltage, and resets the microcomputer. Yes. In this reset IC, for example, in order to monitor voltages of two systems of 3.3 V and 5.0 V, for example, as shown in FIG. 2, the microcomputer 130 has two input ports (inputs # 1 and # 2). I need it.

  On the other hand, if one input port of the microcomputer 130 is required, for example, as shown in FIG. 3, the logic of two input signals output from the reset ICs 110 and 120 driven by different voltages is used. In order to achieve this, a logic circuit (which is substantially OR but operates because of negative logic and the AND gate 140) needs to be added. Furthermore, in order to operate the logic circuit stably. It is necessary to prepare a separate power supply (15V).

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a reset circuit capable of monitoring two systems of voltages with one input port without using a power source other than the power source to be monitored. And

Reset circuit of the present invention to solve the problems described above, a reset circuit for outputting a reset signal from the output terminal, a first to a first power supply, is input to the first power supply is connected A reset circuit; a second power supply; a second reset circuit having an input terminal connected to the second power supply; a first resistor having one end connected to the first power supply; A second resistor having one end connected to a power source, an emitter connected to the output end of the first reset circuit, the other end of the first resistor, and the output end, and a base connected to the second reset And a PNP transistor in which an output terminal of the circuit and the other end of the second resistor are connected and a collector is grounded.

  ADVANTAGE OF THE INVENTION According to this invention, the reset circuit which can monitor voltage of two systems stably with one input port can be provided.

It is a block diagram which shows the structure of the reset circuit which concerns on embodiment of this invention. It is a block diagram which shows the structure of the reset circuit of the prior art example 1. FIG. It is a block diagram which shows the structure of the reset circuit of the prior art example 2. FIG.

  DESCRIPTION OF EMBODIMENTS Hereinafter, a mode for carrying out the present invention (hereinafter referred to as this embodiment) will be described in detail with reference to the accompanying drawings. Note that the same numbers are assigned to the same elements throughout the description of the present embodiment.

(Configuration of the embodiment)
FIG. 1 is a block diagram showing the configuration of the reset circuit 10 according to the present embodiment. The reset circuit 10 according to the present embodiment includes a reset IC 11 (first reset circuit), a reset IC 12 (second reset circuit), resistors R1, R2, and RB, a PNP transistor (hereinafter simply referred to as TR1), It is comprised including.

The reset IC 11 is an IC having an output terminal of an open drain (oven collector) driven by a 3.3V power supply (first power supply). When the 3.3V power supply becomes a predetermined voltage or lower, a low level reset is performed. A signal is generated and output from the output terminal P 0 of the reset circuit 10 to the input port P 1 of the microcomputer 13. As a result, the microcomputer 13 is reset. Similarly, the reset IC 12 is an IC having an open drain output terminal, which is driven by a 5.0 V power source (second power source), and when the 5.0 V power source becomes a predetermined voltage or lower, a low level reset signal is output. Generated and output from the output terminal P 0 of the reset circuit 10 to the input port P 1 of the microcomputer 13. As a result, the microcomputer 13 is reset.

The microcomputer 13 as a reset target circuit performs arithmetic processing according to a program recorded in a built-in memory, and controls peripheral LSIs and the like not shown. Here, each reset signal generated by the reset ICs 11 and 12 is fetched from the output terminal P0 of the reset circuit 10 via one port P1, and reset processing is performed.

  The resistor R1 is a pull-up resistor having one end connected to a 5.0V power source (second power source) and the other end connected to the base of TR1. The resistor R2 is a pull-up resistor having one end connected to the 3.3V power source (first power source) and the other end connected to the emitter of TR1. The resistor RB is a base resistor connected between the output terminal of the reset IC 12 and the base of TR1.

TR1 is used to prevent interference between the reset IC11 output operated by the 3.3V power supply and the reset IC12 output operated by the 5.0V power supply. In addition to the resistor R2 described above, the emitter is connected to the output terminal of the reset IC 11 and the input port P1 of the microcomputer 13 via the output terminal P0 of the reset circuit 10, and the base is connected to the resistor R1 described above. The output terminal (open drain) of the reset IC 12 is connected, and the collector is grounded.

(Operation of the embodiment)
Hereinafter, the operation of the reset circuit 10 according to the present embodiment shown in FIG. 1 will be described in detail.

  First, the operation of the reset IC 11 will be described. When the voltage of 3.3V (first power supply) becomes a predetermined voltage or less and the reset IC 11 operates, the reset input for one input port P1 of the microcomputer 13 becomes Low level. At this time, since the output of the reset IC 12 is at a high level and is input to the base of TR1, the TR1 does not operate. Therefore, the output of the reset IC 12 is not transmitted to the input port P1 of the microcomputer 13, and as a result, The input port P1 of the microcomputer 13 becomes low level and the microcomputer 13 is reset.

  When the voltage of the 3.3V power supply further decreases, the voltage becomes lower than the operating voltage of the reset IC 11 and the output becomes a high impedance state. However, since the 3.3 V power supply line whose voltage has dropped is connected to the input port P1 of the microcomputer 13 via the resistor R2, the potential of the input port of the microcomputer 13 is maintained at the low level. Therefore, the reset state of the microcomputer 13 is also maintained. At this time, since the output of the reset IC 12 is at a high level and is supplied to the base, TR1 does not operate. Therefore, the output of the reset IC 12 is not transmitted to the input port P1 of the microcomputer 13, and as a result, the input port P1 is Becomes Low level. For this reason, the microcomputer 13 can take the low level signal through the input port P1 and perform the reset process.

  Next, the operation of the reset IC 12 will be described. When the reset IC 12 operates when the voltage of 5.0 V (second power supply) becomes equal to or lower than the predetermined voltage, the Low level is input to the base of TR1, and as a result, TR1 operates. Here, when TR1 operates, the potential of the emitter of TR1 becomes Low level, the input port P1 of the microcomputer 13 becomes Low level, and the microcomputer 13 is reset.

  When the voltage of the 5.0V power supply further decreases, the output voltage becomes lower than the operating voltage of the reset IC 12 and the output becomes a high impedance state. Here, instead of the reset IC 12, the 5.0 V power supply line having a reduced voltage is connected to the base of the TR 1 via the resistor R 1, so the base potential of the TR 1 becomes the low level, and therefore the TR 1 continues. Thus, the emitter potential is maintained at a low level. At this time, the output of the reset IC 11 is at a high level, but since the TR1 is operating and the collector is grounded, the potential of the input port P1 of the microcomputer 13 is maintained at a low level. Therefore, the reset state of the microcomputer 13 is also maintained. Although the description has been given above with the example of the 5.0V power supply and the 3.3V power supply, the present invention is not limited to this and can be performed with any combination of voltages. However, it is recommended that the voltage of the power source connected to the reset IC 11 be lower than the voltage of the power source connected to the reset IC 12. This is because if the base voltage of TR1 is lower than the emitter voltage, TR1 may be turned on and the level of P1 may be lowered to the base voltage even when the power supply is in a normal state (voltage that does not require resetting). .

(Effect of embodiment)
As described above, according to the reset circuit 10 according to the present embodiment, the voltage of the first power supply (3.3 V power supply) is lowered and the output of the first reset circuit (reset IC 11) is in a high impedance state. Even if the operation becomes impossible, the input port of the reset target circuit (microcomputer 13) is set to the same potential as the voltage of the first power supply by the first resistor (R2). At this time, interference due to the output of the second reset circuit can be avoided by the PNP transistor (TR1). Conversely, even if the second voltage drops and the output of the second reset circuit becomes in a high impedance state and becomes inoperable, the second resistor (R1) makes the input port the same as the voltage of the second power supply. Set to potential. For this reason, two systems of voltage monitoring can be stably performed by one input port P1 of the microcomputer 13. Therefore, the circuit scale can be reduced, the component mounting density can be reduced, and the cost can be reduced.

  As mentioned above, although preferred embodiment of this invention was explained in full detail, it cannot be overemphasized that the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiments. Further, it is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  DESCRIPTION OF SYMBOLS 10 ... Reset circuit, 11 ... Reset IC (1st reset circuit), 12 ... Reset IC (2nd reset circuit), 13 ... Microcomputer (circuit to be reset), TR1 ... PNP transistor, R1, R2, RB ... Resistance

Claims (1)

A reset circuit for outputting a reset signal from an output terminal,
A first power source;
A first reset circuit having an input terminal connected to the first power supply;
A second power source;
A second reset circuit having an input terminal connected to the second power supply;
A first resistor having one end connected to the first power source;
A second resistor having one end connected to the second power source;
The emitter is connected to the output end of the first reset circuit, the other end of the first resistor, and the output end , and the base is connected to the output end of the second reset circuit and the other end of the second resistor. And a PNP transistor whose collector is grounded,
A reset circuit comprising:

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