JP6072710B2 - Hardware abnormality monitoring device - Google Patents

Description

  This invention monitors the occurrence of error (bit corruption) in the data read from the memory, and determines whether the error is a fixed failure (hard error caused by hardware) or a transient error (soft error caused by another cause). The present invention relates to a hardware abnormality monitoring device to be detected.

In the conventional device, when memory is read, 1-bit corruption is detected by parity, or 1-bit corruption is detected and corrected by ECC, and when 2-bit corruption is detected, corrected data is used, or bit-garbled data is discarded. The failure processing was performed by continuing operation or detecting an abnormality.
Bit corruption is affected by noise and radiation in addition to fixed faults, and SEU (Single Event Upset) may cause a soft error. It can be said that it is more redundant to discard the data that is garbled or to correct the bit and continue the operation.
However, on the other hand, if failure processing is not performed in order to continue operation, normal operation continues while the abnormal state continues, and detection of a fixed failure may be delayed because it is not detected as a failure.
In order to deal with such a problem, a method has been devised (for example, Patent Document 1) in which the number of occurrences of bit corruption is counted and a fixed failure is determined from the number of error occurrences for each bit.

Japanese Patent Laid-Open No. 6-59920 (pages 2 and 3, FIG. 1)

As described above, if the garbled data is discarded or the operation is continued after correcting the bit, it is impossible to determine whether the failure is a fixed failure or a transient abnormality. Have.
In addition, there is also a problem that redundancy is lost if failure processing is performed by detecting bit corruption once in order to grasp fixed failures early.

  The present invention has been made in order to solve the above-described problems, and is a hardware abnormality monitoring device that can continue operation when a transient abnormality occurs and can detect a fixed failure while maintaining redundancy. The purpose is to obtain.

In the hardware abnormality monitoring device according to the present invention, a plurality of check circuits provided corresponding to each of the plurality of memories and detecting bit corruption of data read from the corresponding memories , any of the plurality of check circuits When a bit corruption of data is detected by the above, the counting unit that counts up, and the count value by this counting unit is compared with a predetermined threshold value, and when the count value reaches the threshold value, a plurality of memories The apparatus includes a failure determination unit that determines that a mounted device is defective.

According to the present invention, it provided corresponding to each of the plurality of memories, a plurality of check circuits for detecting a bit error of data read from the corresponding memory, bit error data by any of the plurality of check circuits When detected, the counting unit that counts up, and the count value by this counting unit is compared with a predetermined threshold value, and when the count value reaches the threshold value, the failure of the device equipped with a plurality of memories Therefore, it is possible to continue the operation in the case of a transient abnormality and to detect a fixed failure of the entire apparatus equipped with a plurality of memories .

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows the hardware abnormality monitoring apparatus by Embodiment 1 of this invention. It is a flowchart which shows the processing sequence of the hardware abnormality monitoring apparatus by Embodiment 1 of this invention. It is a block diagram which shows the hardware abnormality monitoring apparatus by Embodiment 2 of this invention. It is a flowchart which shows the processing sequence of the hardware abnormality monitoring apparatus by Embodiment 2 of this invention. It is a figure which shows the operation example at the time of determination of the soft error of the hardware abnormality monitoring apparatus by Embodiment 2 of this invention. It is a figure which shows the operation example at the time of determination of the fixed failure of the hardware abnormality monitoring apparatus by Embodiment 2 of this invention. It is a block diagram which shows the hardware abnormality monitoring apparatus by Embodiment 3 of this invention. It is a figure which shows the operation example at the time of determination of the soft error of the hardware abnormality monitoring apparatus by Embodiment 3 of this invention. It is a figure which shows the operation example at the time of determination of the fixed failure of the hardware abnormality monitoring apparatus by Embodiment 3 of this invention. It is a block diagram which shows the hardware abnormality monitoring apparatus by Embodiment 4 of this invention. It is a block diagram which shows the hardware abnormality monitoring apparatus by Embodiment 5 of this invention.

Embodiment 1 FIG.
Embodiment 1 of the present invention will be described below with reference to the drawings.
1 is a block diagram showing a hardware abnormality monitoring apparatus according to Embodiment 1 of the present invention.
In FIG. 1, a memory 1 stores data. The check circuit 2 detects or corrects bit corruption of data read from the memory 1 by ECC or parity check. The subsequent circuit 3 uses the read data after the check by the check circuit 2.
The abnormality monitoring unit 4 (counting unit) counts up the occurrence of bit corruption detected by the check circuit 2. The failure determination unit 5 compares the count value of the abnormality monitoring unit 4 with an arbitrary threshold value that is determined as a fixed failure, and determines whether there is a fixed failure.
The hardware abnormality monitoring device may be a computer or a device that is incorporated into a computer and used. In this case, the memory 1 and the check circuit 2 may be those of a computer.

Next, the operation will be described.
With reference to FIG. 2, the determination sequence for fixed faults will be described.
ST1 is an operation start of the hardware abnormality monitoring apparatus. In ST2, the check circuit 2 detects bit corruption (occurrence of abnormality) in the read data. If there is no bit corruption, the operation continues as it is, and if there is bit corruption, the process of ST3 is performed.
In ST3, the abnormality monitoring unit 4 counts up the number of occurrences of bit corruption. In ST4, the failure determination unit 5 compares the counter value in ST3 with an arbitrary threshold value determined as a preset fixed failure.
If the counter value is smaller than the threshold value, the operation is continued as it is. If the counter value is equal to or larger than the threshold value, it is determined in ST5 that a fixed failure has occurred.

According to the first embodiment, it is possible to detect whether a bit corruption is a fixed failure or a transient abnormality based on the number of occurrences of a bit corruption, reduce unnecessary failure processing when a transient abnormality occurs, and fix a fixed failure. Failure processing at the time of occurrence can be performed smoothly.
In addition, transient abnormalities continue to operate, and abnormalities with the possibility of fixed faults can be detected. it can.

Embodiment 2. FIG.
The second embodiment will be described below with reference to the drawings.
FIG. 3 is a block diagram showing a hardware abnormality monitoring apparatus according to Embodiment 2 of the present invention.
In FIG. 3, 1 to 5 are the same as those in FIG. In FIG. 3, a timer unit 6 is provided that is started when bit corruption occurs. Based on the counter value of the abnormality monitoring unit 4, the failure determination unit 5 makes a failure determination within the timer operation time of the timer unit 6.

  In the first embodiment, the failure determination unit 5 performs the failure determination based on the information from the abnormality monitoring unit 4 in FIG. 1, but in the second embodiment, the timer monitoring unit 4 and the timer unit are provided by providing the timer unit 6. By performing the failure determination based on the information of No. 6, it is possible to determine the fixed failure with higher accuracy.

Next, a fixed failure determination sequence according to the second embodiment will be described with reference to FIG.
In ST2, if the check circuit 2 checks that there is a bit error, it is checked in ST9 whether the timer is running. If not started, the timer is started in ST6. Here, the timer value is an arbitrary value set in advance based on the read access frequency and the write frequency of the memory 1.
Next, in ST3, after the abnormality monitoring unit 4 counts up the number of occurrences of bit corruption, in ST4, the failure determination unit 5 compares the counter value in ST3 with an arbitrary threshold value determined as a preset fixed failure. . If the counter value is smaller than the threshold value, the operation is continued as it is. If the counter value is equal to or larger than the threshold value, it is determined in ST5 that a fixed failure has occurred.
In ST2, it is confirmed in ST10 whether or not the timer has expired in the state where no abnormality has occurred. If the timer has expired, in ST8, the counter in ST3 is cleared, the timer is cleared, and the process goes to ST2.

FIG. 5 shows an example of timing at which bit corruption has occurred, but bit corruption above the threshold has not occurred within a certain period, and a soft error is determined.
In FIG. 5, the horizontal axis indicates the passage of time. When the bit corruption is detected, the number of occurrences of bit corruption is counted up and at the same time the timer is started. When the second bit corruption occurs, the timer has not expired, so the number of occurrences of bit corruption is counted up while the timer is operating.
In the example of FIG. 5, since the number of occurrences of bit corruption until the timer expires is smaller than a preset threshold value for determining a fixed failure, the fixed failure is not determined. It is determined that bit corruption did not occur at the frequency at which it was determined as a fixed failure (soft error).
The counter for the number of occurrences of bit corruption is cleared simultaneously with the expiration of the timer with a preset timer value.

FIG. 6 shows an example of timing when it is determined that bit corruption is due to a fixed failure. The time is shown on the horizontal axis. By detecting bit corruption, the timer is started simultaneously with counting up the number of occurrences of bit corruption. When the second bit corruption occurs, the timer has not expired, so the number of occurrences of bit corruption is counted up while the timer is operating. Here, since the number of occurrences is smaller than a preset threshold value for determining a fixed failure, the fixed failure is not determined.
Since the timer has not expired even when the third bit corruption occurs, the number of occurrences of bit corruption is counted up while the timer is operating. Now, assuming that the preset threshold value for determining a fixed failure is 3 times, the number of occurrences of bit corruption has reached the threshold value before the timer expires, so it is determined that the fixed failure has occurred.

  According to the second embodiment, the number of occurrences of bit corruption by the abnormality monitoring unit is counted by the time when the timer expires, and the occurrence of bit corruption is determined, so that it is possible to determine fixed failure with higher accuracy.

Embodiment 3 FIG.
The third embodiment will be described below with reference to the drawings.
FIG. 7 is a block diagram showing a hardware abnormality monitoring apparatus according to Embodiment 3 of the present invention.
In FIG. 7, 1 to 5 are the same as those in FIG. In FIG. 7, the timer unit 14 operates independently and gives a determination timing to the failure determination unit 5.

  In the second embodiment, the occurrence of bit corruption is notified to the abnormality monitoring unit 4 and the timer unit 6 and the failure determination is performed. However, in the third embodiment, the timer unit 14 operates independently and the failure determination is performed. The processing is simplified by notifying the unit 5 of the timing of failure determination.

FIG. 8 shows an example of timing at which bit corruption has occurred, but bit corruption above the threshold has not occurred within a certain period, and a soft error is determined. The time is shown on the horizontal axis.
The timer unit 14 generates a fixed failure determination timing based on an arbitrary timer value set in advance based on the read access frequency and the write frequency of the memory 1.
In FIG. 8, since the number of occurrences of bit corruption has not reached the threshold at the determination timing, it is not determined as a fixed failure, and the counter for the number of occurrences of bit corruption is cleared. It is determined that bit corruption did not occur at the frequency at which it was determined as a fixed failure (soft error).

FIG. 9 shows an example of timing when it is determined that bit corruption is due to a fixed failure. The time is shown on the horizontal axis.
The timer unit 14 generates a fixed failure determination timing based on a preset timer value. In FIG. 9, since the number of occurrences of bit corruption has reached the threshold at the determination timing, it is determined as a fixed failure.

  According to the third embodiment, it is possible to determine the fixed failure with higher accuracy by giving the determination timing of the failure determination unit 5 by the timer unit that operates independently.

Embodiment 4 FIG.
Hereinafter, the fourth embodiment will be described with reference to the drawings.
FIG. 10 is a block diagram showing a hardware abnormality monitoring device according to Embodiment 4 of the present invention.
In FIG. 10, 1 to 5 are the same as those in FIG. In FIG. 10, an address holding unit 7 that holds an abnormality occurrence address is provided, and the failure determination unit 5 creates a management table 15 that counts the number of occurrences for each address.

In the first embodiment, as shown in FIG. 1, only the occurrence of bit corruption is notified to the abnormality monitoring unit 4 and the failure determination is performed, but the fourth embodiment is a check for performing ECC and parity check. The circuit 2 notifies the address holding unit 7 of the address where the bit corruption has occurred.
The failure determination unit 5 manages the number of occurrences of bit corruption and the information on the occurrence of bit corruption and leaves it in the management table 15 so that the information can be provided so that failure processing can be performed smoothly when determining a fixed failure. I have to.
The failure determination unit 5 can also determine the failure by monitoring the number of occurrences of bit corruption for each address.

  According to the fourth embodiment, since the number of bit corruption occurrences is managed for each bit corruption occurrence address, failure processing can be performed smoothly when determining a fixed failure.

Embodiment 5. FIG.
Hereinafter, the fifth embodiment will be described with reference to the drawings.
FIG. 11 is a block diagram showing a hardware abnormality monitoring apparatus according to Embodiment 5 of the present invention.
11, 1 to 5 and 7 are the same as those in FIG. 10, and 14 is the same as that in FIG. In FIG. 11, the memory 1, the check circuit 2, and the subsequent circuit 3 have three series, and any abnormality occurrence is detected by the abnormality monitoring unit 4, the failure determination unit 5, the address holding unit 7, and the timer unit 14. .
That is, the memory A1, the check circuit A2, the subsequent circuit A3, the memory B8, the check circuit B9, the subsequent circuit B10, the memory C11, the check circuit C12, and the subsequent circuit C13. For this reason, the management table 16 created by the failure determination unit 5 manages the occurrence address and the number of occurrences for each memory.

In the first to fourth embodiments, it is determined whether or not there is a fixed failure with respect to bit corruption that has occurred in a certain memory. However, bit corruption may occur in a plurality of memories due to some common factor.
In the fifth embodiment, a bit corruption occurrence information and a bit corruption occurrence address of a plurality of memories are counted by one abnormality monitoring unit 4 and managed by a failure determination unit 5 to obtain a device (a device equipped with a plurality of memories). ) Monitoring the entire system for abnormalities so that fixed failures of the equipment can be detected early.

In FIG. 11, the memory A1, the check circuit A2, the subsequent circuit A3, the memory B8, the check circuit B9, the subsequent circuit B10, the memory C11, the check circuit C12, and the subsequent circuit C13 operate independently. Yes.
The check circuit A2, the check circuit B9, and the check circuit C12 notify the abnormality monitoring unit 4 of occurrence of bit corruption and also notifies the address holding unit 7 of the occurrence of bit corruption when bit corruption is detected.

  The failure determination unit 5 manages information from the abnormality monitoring unit 4 and the address holding unit 7 for each memory using the management table 16. Depending on the determination timing of the failure determination generated from an arbitrary timer value set in advance from the timer unit 14, the failure determination unit 5 determines the number of occurrences of bit corruption as a whole device or the number of occurrences of bit corruption per address, or memory The number of occurrences of bit corruption for each is compared with an arbitrary threshold value that is determined as a fixed failure that is set in advance, and it is determined whether or not there is a fixed failure.

  According to the fifth embodiment, a single failure determination unit manages bit corruption occurrence information and bit corruption occurrence addresses of a plurality of memories, thereby monitoring an abnormality in the entire device and finding a fixed failure of the device at an early stage. can do.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

1 memory, 2 check circuit, 3 subsequent circuit, 4 error monitoring unit, 5 failure determination unit,
6 Timer section, 7 Address holding section, 8 Memory B, 9 Check circuit B,
10 Subsequent circuit B, 11 Memory C, 12 Check circuit C, 13 Subsequent circuit C,
14 timer part, 15 management table, 16 management table.

Claims (4)

A plurality of check circuits provided corresponding to each of the plurality of memories and detecting bit corruption of data read from the corresponding memories;
A counting unit that counts up when bit corruption of the data is detected by any of the plurality of check circuits;
And a failure determination unit that compares a count value obtained by the counting unit with a predetermined threshold value and determines that a failure of the device in which the plurality of memories is mounted when the count value reaches the threshold value. A hardware abnormality monitoring device. The timer is started by detecting the first bit corruption of the data, and includes a timer unit for measuring a predetermined period of time,
2. The hardware abnormality according to claim 1, wherein the failure determination unit determines whether or not the device having the plurality of memories is failed when the count value reaches the threshold during the predetermined period. Monitoring device.   The hardware according to claim 1, further comprising a timer unit that measures a predetermined period and notifies the failure determination unit when the predetermined period has elapsed, and compares the count value with a threshold value. Wear abnormality monitoring device. An address holding unit that holds an address where bit corruption has occurred by the check circuit,
The hardware failure monitoring device according to any one of claims 1 to 3, wherein the failure determination unit stores the number of occurrences of bit corruption for each address.

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