JP6086017B2 - Data processing apparatus and data processing program - Google Patents

Description

  The present invention relates to extracting a mask pattern shape in LSI (Large Scale Integration) manufacturing.

  Currently, in the design of LSI manufacturing processes and mask pattern processing, mask patterns (simply referred to as patterns) of various design data are converted into MDP (Mask Data Preparation, mask data conversion processing) and OPC (Optical Proximity Effect Correction Processing). Thus, complex processing, rules between patterns, simulation verification, and arithmetic processing are performed.

  In order to efficiently shorten the verification period, it is known to verify whether layout data violates a design rule based on representative format data acquired from layout data.

JP 2006-244313 A

  Processing related to the design of an LSI manufacturing process has become more complicated, large-scale, and sophisticated in recent years as the chip processing scale has increased and the accuracy of pattern processing has been pursued.

  When performing these complex processes, the features and characteristics of the patterns that exist before processing are extracted and grasped in advance, and fed back as information necessary for improving the processing accuracy of pattern data processing and speeding up arithmetic processing. Is required. For example, in a pattern correction process such as OPC correction, for a pattern (for example, a hot spot) that is not good for the correction processing algorithm, it is determined in advance whether or not this hot spot pattern exists before the process. , It is required to avoid or modify the pattern.

  With the above-described technique for verifying whether layout data violates a design rule, it is difficult to grasp the presence of a hot spot in advance. Therefore, it has not been possible to efficiently extract hot spot shapes and features.

  In one aspect, an object of the present invention is to extract and grasp in advance the existence of a characteristic shape of a designed mask pattern.

  According to one aspect of the present embodiment, the data processing apparatus includes a storage unit that stores an array library in which a symbol array representing a partial shape of a mask pattern designed on a chip is stored, and a pattern indicated by design data. An extraction unit that extracts the partial shape by symbolizing a region to be extracted and searching the symbol array in the sequence library.

  Further, as means for solving the above problems, a program for causing a computer to function as the data processing apparatus, a recording medium recording the program, and a data processing method may be used.

  According to one aspect of the present embodiment, a characteristic shape of a mask pattern in LSI manufacturing can be efficiently extracted, and chip characteristics can be analyzed with high accuracy.

It is a figure for demonstrating the example of a method by data viewing. It is a figure for demonstrating the example of a method by pattern matching. It is a figure which shows the hardware constitutions of a data processor. It is a figure which shows the function structural example of a data processor. It is a flowchart figure for demonstrating an extraction process. It is a figure which shows the process example in STEP1 performed by the blocking part. It is a figure which shows the example of a symbol library. It is a figure for demonstrating the rule considered as the same symbol. It is a figure for demonstrating the symbolization process by a symbolization part. It is a figure for demonstrating the search process by a search part. It is a figure for demonstrating the data structure of labeling data. It is a figure which shows the example of a search process. It is a flowchart for demonstrating the registration process of a sequence library. It is a figure for demonstrating the outline | summary of the registration process of a symbol arrangement | sequence. It is a figure for demonstrating the registration process example of a symbol arrangement | sequence (continuation). It is a figure for demonstrating the registration process example of a symbol arrangement | sequence (continuation). It is a figure which shows the example of a data structure of a sequence library. It is a figure which shows the example of registration to a sequence library. It is a figure which shows the example of a result of an analysis process. It is a figure which shows the process example when not applying this Embodiment. It is a figure which shows the process example of the data processing apparatus to which this Embodiment is applied.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, a method (related art) for extracting a hot spot pattern shape or a characteristic shape portion when the present invention is not applied will be described.

  First, there is a method based on data viewing by a designer. FIG. 1 is a diagram for explaining an example of a method by data viewing. In FIG. 1, an example in which a designer displays a pattern shape BB222 on a display device using a computer device such as a personal computer (PC) based on design data configuration information 1a in which mask pattern data is hierarchized. It is shown. When the data 1b of the pattern shape BB222 is displayed on the display device, the designer visually confirms a shape that can be a hot spot.

  In this method, it is necessary for the designer to display and confirm the mask pattern data for each layer on the display device using the design data configuration information 1a, which is a burden on the designer. In addition, the extraction of shapes that can be hot spots differs in accuracy depending on the experience of the designer. There are cases where extraction cannot be performed with a certain degree of accuracy.

  As described above, it is possible to grasp the local and special pattern in the chip in the LSI, but it takes too much man-hours if it is by a person such as a designer, and if many similar shapes are included, It is inaccurate for human vision, and it is very difficult to grasp the entire chip.

  There is also a method of extracting a shape that can be a hot spot by pattern matching. FIG. 2 is a diagram for explaining a method example by pattern matching. In FIG. 2, hot spot patterns that the correction algorithm is not good at are registered in the library 2a in advance. It is determined whether or not the pattern exists in the chip by determining the pattern shape [A], [B], [C] registered in the library 2a and represented by each pattern shape and the mask pattern data 2b. ] Are compared with each other to extract the pattern type.

  The pattern matching technique is a technique in which target pattern figures and cells are registered in advance as a library, and the registered pattern is found in a search target (in-chip pattern here). Pattern matching technology not only detects patterns and cells that completely match the pattern data registered in the library, but also gives tolerance values to the previously registered library called loose matching. The versatility of extraction can also be improved.

  Identification and extraction of pattern features (for example, hot spot pattern shape) by data viewing or pattern matching technology is a technology for recognizing the presence or absence of a registered pattern by repeatedly searching for a target pattern. These technologies are search operations for a target pattern to be extracted, but when there are a wide variety of target patterns and all of them are searched, the pattern matching technology has a huge search target, and the search is performed. Since the time is enormous, it becomes unrealistic.

  In this embodiment, in the identification and extraction of a wide variety of pattern features, a general-purpose pattern library is easily created and registered, and all the patterns existing in the chip are labeled. Since the collected information is classified and stored, it is understood how many patterns exist in the chip.

  Therefore, in this embodiment, all the chip pattern data is symbolized, and the features of the pattern shape are identified and classified based on the symbol array library representing the figure. These classified information is applied to all patterns in the chip, pattern information is accumulated, and the shape, appearance frequency, appearance location (Map), etc. of all pattern information are output as chip characteristics.

  The data processing apparatus according to the present embodiment has a hardware configuration as shown in FIG. FIG. 3 is a diagram illustrating a hardware configuration of the data processing apparatus. In FIG. 3, a data processing apparatus 100 is a terminal controlled by a computer, and includes a central processing unit (CPU) 11, a random access memory (RAM) 12, a read-only memory (ROM) 13, and an auxiliary memory. The device 14 includes an interface (I / F) device 15, a display device 16, a communication device 17, a keyboard 18, a mouse 19, and a drive device 19. The CPU 11, RAM 12, ROM 13, auxiliary storage device 14, I / F 15, and drive device 19 are connected to the bus B. The display device 16, the communication device 17, and the input device 18 are connected to the bus B via the I / F device 15.

  The CPU 11 controls the data processing device 100 according to a program stored in the main storage device 12. The RAM 12 and the ROM 13 serve as main storage devices, and store programs executed by the CPU 11, data necessary for processing by the CPU 11, data obtained by processing by the CPU 11, and the like. Further, a partial area of the RAM 12 is allocated as a work area used for processing by the CPU 11.

  The auxiliary storage device 14 uses a hard disk drive, and stores data such as programs for executing various processes. A part of the program stored in the auxiliary storage device 14 is loaded into the RAM 12 and executed by the CPU 11 to realize various processes. The storage unit 130 corresponds to the RAM 12, the ROM 13, and the auxiliary storage device 14.

  The input device 14 includes a keyboard 18a, a mouse 18b, and the like, and is used for a user to input various information necessary for processing by the data processing device 100. The display device 15 displays various information required under the control of the CPU 11.

  The communication device 17 is a device that is connected to, for example, the Internet, a LAN (Local Area Network), etc., and controls communication with an external device. Communication by the communication device 17 is not limited to wireless or wired communication.

  A program that realizes processing performed by the data processing apparatus 100 is provided to the data processing apparatus 100 by a storage medium 20 such as a CD-ROM (Compact Disc Read-Only Memory). That is, when the storage medium 20 storing the program is set in the drive device 19, the drive device 19 reads the program from the storage medium 20, and the read program is installed in the auxiliary storage device 14 via the bus B. Is done. When the program is activated, the CPU 11 starts its processing according to the program installed in the auxiliary storage device 14. The medium for storing the program is not limited to a CD-ROM, and any medium that can be read by a computer may be used. As a computer-readable storage medium, in addition to a CD-ROM, a portable recording medium such as a DVD disk or a USB memory, or a semiconductor memory such as a flash memory may be used.

  FIG. 4 is a diagram illustrating a functional configuration example of the data processing apparatus. In FIG. 4, the data processing apparatus 100 mainly includes an extraction unit 40 and an array library registration unit 50. The storage unit 130 also stores design data 31, a layer table 32, a symbol library 33, labeling data 34, an array library 35, feature extraction data 36, and library graphic data 37.

  The extracting unit 40 includes a blocking unit 41, a symbolizing unit 42, a searching unit 43, an analyzing unit 44, a result output unit 45, and a new sequence library creating unit 46.

  The blocking unit 41 identifies a layer on which a pattern such as a wiring is formed from the design data 31 and the layer table 32, and blocks it with an arbitrary block size.

  The symbolization unit 42 refers to the symbol library 33 and converts the pattern shape into symbols by a predetermined symbolization method in units of dots for each block. One dot size is arbitrarily set based on the minimum line width or the minimum interval.

  The search unit 43 performs a label search that searches the sequence library 35 for the symbol sequence corresponding to the data converted by the symbolization unit 42. The label search is a search for the same symbol arrangement for the entire block. The search unit 43 performs labeling on the same symbol arrangement, and stores the corresponding data portion as labeling data 34. The search unit 43 can perform the processing efficiently by skipping the labeled data portion.

  The analysis unit 44 acquires search results of all blocks from the labeling data 34, and analyzes the appearance frequency, the cumulative number, and the like for each pattern shape having the same feature.

  The result output unit 45 outputs the chip feature collection data 36 indicating the analysis result by the analysis unit 44 to the storage unit 130 and displays it on the display device 16.

  The new sequence library creation unit 46 relates to the new sequence when the search unit 43 determines that the symbol sequence created by the symbolization unit 42 is a new sequence, that is, when it does not exist in the sequence library 35. Create a library. A new sequence is added to the sequence library 35.

  The sequence library registration unit 50 includes a blocking unit 51, a symbolization unit 52, a selection unit 53, and a registration unit 54.

  The blocking unit 51 identifies a layer on which a pattern such as a wiring is formed from the library graphic data 37 and the layer table 32 and blocks the layer with an arbitrary block size. In the first creation of the sequence library 35, arbitrary library graphic data 37 is used instead of the design data 31 in the blocking unit 41 of the extraction unit 40.

  The symbolizing unit 52 refers to the symbol library 33 and converts the pattern shape into symbols by a predetermined symbolizing method in units of dots for each block. One dot size is arbitrarily set based on the minimum line width or the minimum interval. The same processing as the symbolizing unit 42 of the extracting unit 40 is performed.

  The selection unit 53 acquires one or more symbol areas to be registered in the sequence library 35 in one block.

  The registration unit 54 registers the symbol of the area selected by the selection unit 53 as a symbol array to be registered in the array library 35. At the time of registration in the array library 35, the registration unit 54 groups the pattern shapes so that they can be recognized as the same pattern shape even if the pattern shape is shifted vertically or horizontally. In addition to preventing erroneous recognition of the pattern shape due to misalignment, unnecessary registration data can be reduced.

  Data stored in the storage unit 130 will be described.

  The design data 31 includes data on wiring, connections, cells, etc. of all layers of the designed chip, and the data is managed for each layer. In the layer table 32, layer (layer) information is registered in advance.

  The symbol library 33 is a library in which one symbol is associated with each partial shape of the pattern in the dot. The pattern shape is referred to when symbolizing the pattern shape, and the pattern shape in an arbitrary region is replaced with a symbol for each dot in the region.

  The labeling data 34 is data obtained by labeling the symbol arrangement detected once with respect to the design data 31 of the pattern shape feature extraction target. Feature extraction processing can be performed efficiently by labeling the same symbol arrangement.

  The array library 35 is a data file that stores a symbol array converted as a library by making the pattern shape in a predetermined area correspond to the shape of the predetermined area. In the arrangement library 35, the same pattern shape is managed as the same group only by shifting to the upper, lower, left or right.

  The feature extraction data 36 indicates the analysis result of the pattern shape that is the feature extracted from the design data 31 analyzed by the analysis unit 44.

  The library graphic data 37 has one or more pattern shapes recognized in advance by the designer.

  Next, an extraction process for extracting pattern shape features performed by the data processing apparatus 100 will be described. FIG. 5 is a flowchart for explaining the extraction process. In FIG. 5, in the data processing apparatus 100, the blocking process is performed by the blocking unit 41 of the extraction unit 40 (STEP 1).

  In STEP 1, the blocking unit 41 reads the design data 31, sets layer information registered in advance from the layer table 32 (step S 11), and refers to the design data 31 to process layer data. The region is decomposed (step S12), and the entire chip is blocked (fielded) in units of layers (step S13). After the blocking, the blocking unit 41 develops a mask pattern for each block in the work area of the storage unit 130 (step S14).

  The size of one block to be blocked is not particularly set and is set to an arbitrary size. A layer unit is a hierarchical structure of design data. Each layer constituting the structure, for example, an ISO layer, a transistor layer, or a metal layer. There is.

  Next, the extraction unit 40 performs a symbolization process by the symbolization unit 42 (STEP 2). Steps S15 to S17 correspond to STEP2.

  In STEP 2, the symbolizing unit 42 refers to the symbol library 33 and performs symbol conversion on all patterns in one block according to the symbolization rule (step S 15).

  The size of the area converted into one symbol managed by the symbol library 33 is a rectangle defined by one dot. In addition, although one dot varies depending on the technology, it is set to be equal to or smaller than the minimum line width / interval of the target technology (arbitrary).

  The symbolizing unit 42 expands the symbol map 6a (FIG. 9) in which each dot in one block is replaced with one symbol in the work area of the storage unit 130 (step S16), and reads the symbol label (step S17). .

  Next, the extraction unit 40 performs a search process by the search unit 43 (STEP 3). Steps S18 to S22 correspond to STEP3.

  In STEP 3, the search unit 43 searches the symbol-converted data in one block for a location that matches each symbol sequence in the sequence library 35 that is lexicographically present, and detects a location that matches the symbol sequence. If so, a label search is performed (step S18).

  In the label search, by referring to the labeling data 34, an already recorded labeled area is skipped. Further, when the symbol search classified into the same group by the sequence library 35 is detected in the symbol map 6a (FIG. 9) by the label search, it is determined that they have the same shape.

  The search unit 43 records the place where the symbol arrangement once detected matches as the labeling data 34 (step S20), and skips the place when searching with the next symbol arrangement.

  Then, the search unit 43 determines whether or not the search with reference to the sequence library 35 in the block has been completed (step S20). It is determined whether or not the search has been completed for all the labels in the sequence library 35. If there is an unsearched label in the sequence library 35, the search unit 43 returns to step S18 and repeats the same processing described above.

  On the other hand, when the search is completed for all the labels in the sequence library 35, the search unit 43 determines whether there is a new sequence (step S20-2). That is, it is determined whether or not there is a dot area in the block for which label search has not been completed yet.

  When there is a new sequence, the search unit 43 registers the new sequence of the dot area in which no symbol sequence is detected in the sequence library 35 by the new sequence library creation unit 46 (step S25).

  As will be described later with reference to FIG. 14, the new sequence library creation unit 46 extracts symbols from a predetermined upper left corner according to the shape of the symbol area of the new sequence, and each time it wraps within the symbol area, the return symbol “* ”And extracting to the lower right end of the symbol area, a registration symbol array is created and registered in the sequence library 35. After registration, the extraction unit 40 proceeds to step S20 and causes the search unit 43 to record it as the labeling data 34.

  On the other hand, when there is no new arrangement, that is, when there is no undetected dot area and the whole area can be filled with any symbol arrangement, the search unit 43 finishes labeling for the whole area in the block. And labeling data 34 is used to classify the block (step S21).

  After the intra-block classification, the search unit 43 determines whether there is an unprocessed block (step S22). When the search unit 43 determines that there is an unprocessed block, the extraction unit 40 repeats the above-described processing from the processing by the symbolizing unit 43.

  On the other hand, when the search unit 43 determines that there is no unprocessed block, that is, it is determined that the processing has been completed for all blocks, the extraction unit 40 performs analysis processing by the analysis unit 44 (STEP 4). Step S23 corresponds to STEP4.

  The analysis unit 44 analyzes the appearance frequency and accumulation of the symbol arrangement in the entire designed chip using the intra-block classification result for each block by the search unit 43 (step S23).

  After the analysis, the extraction unit 40 performs a result output process by the result output unit 45 (STEP 5). Step S24 corresponds to STEP5.

  The result output unit 45 stores, in the storage unit 130, the feature extraction data 36 relating to the features of the mask pattern in one chip obtained by analyzing the appearance frequency and accumulation of the symbol array by the analysis unit 44 (step S24). ). In addition, the result output unit 45 displays the feature extraction data 36 on the display device 16.

  With the feature extraction data 36, it is possible to form a histogram of the shape and frequency of all patterns, map the appearance location, etc., and properly understand the characteristics of the chip.

  In the extraction process described above, by performing pattern symbolization, it is possible to grasp a pattern or library that has been searched, and when there is an area that has not been detected by the search within the block, that is, within one block If a symbol array that is not labeled in (2) remains, it is possible to maintain the undetected state and proceed to the next step. The symbol sequences that have not been detected are registered in the sequence library 35 as needed by the new sequence library creation unit 40, so that the characteristics of the entire chip (for example, the shape of the mask pattern) can be extracted without omission.

  A processing example in STEP 1 (steps S11 to S14) performed by the blocking unit 51 will be described with reference to FIG. FIG. 6 is a diagram illustrating a processing example in STEP 1 performed by the blocking unit. In FIG. 6, the same step number is assigned in association with the processing in STEP 1.

  The blocking unit 51 sets a layer on which a mask pattern is formed from the design data 31 and the layer table 32 (step S11). The blocking unit 51 decomposes the data area with respect to the set layer (step S12), and blocks it with an arbitrary size (step S13).

  The blocking unit 51 performs pattern development for each block after the blocking (step S14). Data relating to the shape of the mask pattern is developed in the work area of the storage unit 130.

  The symbol library 33 will be described with reference to FIGS. FIG. 7 is a diagram illustrating an example of a symbol library.

  In FIG. 7A, a pattern within one dot is registered in the symbol library 33. The reference mask pattern partial shape and the symbol are managed in association with each other, and the symbol library 33 is represented in a finite manner. One dot is divided into four. The partial shape of the mask pattern is classified by a combination of 0 to 4 fills of four rectangles in one dot. Symbols A to P are associated with the 16 combinations of fills. The symbol A is associated with an empty dot that is not filled in any of the four rectangles in one dot.

  FIG. 7B and FIG. 7C show the filling patterns that are regarded as the same by the symbolization rule that is regarded as the same symbol, which will be described later. In FIG. 7A, the symbol A in which the entire dot is empty and the symbol F in which the entire dot is filled are excluded.

  In FIG. 7B, “(dash) is added to the symbol shown in FIG. 7A, and in FIG. 7C,“ (double dash) is added to the symbol shown in FIG. 7A. Show. FIG. 7B and FIG. 7C are in a state where the partial shapes are shifted in opposite directions. FIG. 7B shows a case where the partial shape is shifted to the outside of one dot, and FIG. 7C shows a case where the partial shape is shifted to the inside of one dot.

  FIG. 8 is a diagram for explaining a symbolization rule regarded as the same symbol. In FIG. 8, four vertices of one dot are LU, RU, RD, and LD clockwise from the upper left.

  Symbolization rule 1: The partial shapes in one dot contacting only one vertex at the same position are considered to be the same.

  The partial shape of the symbol B in FIG. 7A is in contact with only the vertex LU. Like the symbol B ′ in FIG. 7B and the symbol B ″ in FIG. 7C, the partial shapes in contact with only the vertex LU are all considered to be the same as the partial shape of the symbol B.

  Similarly, the partial shapes of the symbol C ′ in FIG. 7B and the symbol C ″ in FIG. 7C that are in contact with only the vertex RU are the same as the partial shape of the symbol C in FIG. Is considered.

  Further, the partial shapes of the symbol D ′ in FIG. 7B and the symbol D ″ in FIG. 7C that are in contact with only the vertex LD are the same as the partial shape of the symbol D in FIG. Consider.

  Furthermore, the partial shapes of the symbol E ′ in FIG. 7B and the symbol E ″ in FIG. 7C that are in contact with only the vertex RD are the same as the partial shape of the symbol E in FIG. Consider.

  Symbolization rule 2: It is considered that the partial shapes in one dot contacting the left and right or upper and lower vertices of the same position are the same.

  The partial shape of the symbol G in FIG. 7A is in contact with the left and right vertices LD and RD. Like the symbol G ′ in FIG. 7B and the symbol G ″ in FIG. 7C, the partial shapes in contact with the vertex LD and the vertex RD are all considered to be the same as the partial shape of the symbol G.

  Similarly, the partial shape of the symbol H ′ in FIG. 7B and the symbol H ″ in FIG. 7C contacting the two left and right vertices LU and RU is the partial shape of the symbol H in FIG. Is considered the same.

  Further, the partial shape of the symbol I ′ in FIG. 7 (B) and the symbol I ″ in FIG. 7 (C) in contact with the two upper and lower vertices LU and LD is the partial shape of the symbol I in FIG. 7 (A). Consider identical.

  Furthermore, the partial shape of the symbol J ′ in FIG. 7B and the symbol J ″ in FIG. 7C that are in contact with the upper and lower vertices RU and RD is the partial shape of the symbol J in FIG. Consider identical.

  Symbolization rule 3: Partial shapes in one dot that are in contact with two vertices on a diagonal line in the same direction are considered to be the same.

  The partial shape of the symbol K in FIG. 7A is in contact with the two vertices LU and RD on the diagonal line. Like the symbol K ′ in FIG. 7B and the symbol K ″ in FIG. 7C, the partial shapes in contact with the vertex LU and the vertex RD are all considered to be the same as the partial shape of the symbol K.

  Similarly, the partial shape of the symbol L in FIG. 7A that touches the two vertices LD and RU on the diagonal line, the portion of the symbol L ′ in FIG. 7B and the symbol L ″ in FIG. 7C. The shape is considered the same.

  Symbolization rule 4: Partial shapes within one dot that are in contact with three vertices at the same position are considered to be the same.

  The partial shape of the symbol M in FIG. 7A is in contact with the three vertices LU, vertices LD, and vertices RD. Like the symbol M ′ in FIG. 7B and the symbol M ″ in FIG. 7C, the partial shapes in contact with the vertex LU, the vertex LD, and the vertex RD are all the same as the partial shape of the symbol M. Is considered.

  Similarly, the partial shape of the symbol N in FIG. 7A that contacts the three vertices LD, RU, and RD, the symbol N ′ in FIG. 7B, and the symbol N ″ in FIG. 7C. The partial shape is considered to be the same.

  Further, the partial shape of the symbol O in FIG. 7A that contacts the three vertices LU, the vertex RU, and the vertex RD, the symbol O ′ in FIG. 7B, and the symbol O ″ in FIG. 7C. The shape is considered the same.

  Further, the partial shape of the symbol P in FIG. 7A that touches the three vertices LD, LU, and RU, the symbol P ′ in FIG. 7B, and the symbol P ″ in FIG. 7C. The shape is considered the same.

  Thus, based on the number of vertices touched by the partial shape in one dot and the positional relationship between the touching vertices, the shifted partial shapes can be regarded as the same.

  FIG. 9 is a diagram for explaining the encoding process by the encoding unit. In FIG. 9, the symbolizing section 42 refers to the symbol library 33 for each block, symbolizes the partial shape of the mask pattern one by one in order, and develops the symbol map 6a. When one dot is in a partial shape, it touches all four vertices, so the symbol F is acquired from the symbol library 33 and “F” is stored in the storage unit 130 in association with the dot position.

  The search process after the encoding process by the encoding unit 42 will be described in detail with reference to FIG. FIG. 10 is a diagram for explaining search processing by the search unit. In FIG. 10, after the symbolization process, the search unit 43 of the extraction unit 40 sets a symbol map position (step S50). The search unit 43 sets the coordinate system in the block and starts the search process.

  The search unit 43 extracts the symbol arrays from the array library 33 in the descending order of the sequences, compares the symbol arrays with the symbol arrays in the block based on the symbol map position (step S51), and the symbol array of the array library 33 in the block. It is determined whether or not there is a matching part (step S52).

  If there is no portion that matches the symbol array of the sequence library 33, the search unit 43 acquires the next symbol sequence from the sequence library 33 (step S51-2), and repeats the processes of steps S51 and S52.

  When there is a portion that matches the symbol arrangement of the sequence library 33, the search unit 43 uses the shape information associated with the symbol arrangement and the position information of the portion that matches the symbol arrangement in the block as the labeling data 34. Register (step S53).

  The search unit 43 updates the symbol map 6a developed in the storage unit 130 by setting registered to the matched portion (step S54).

  Then, the search unit 43 determines whether or not all the symbol sequences in the sequence library 33 have been searched (step S55). The search unit 43 determines whether all the symbol sequences have been searched (step S55). If a symbol sequence that has not been searched remains in the sequence library 33, the search unit 43 proceeds to step S51-2 and repeats the same processing described above.

  On the other hand, when all the symbol sequences in the sequence library 33 have been searched, the search unit 43 sorts the labeling data 34 in the blocks (step S56). Sorting is performed based on shape information, coordinates and the like. Moreover, the frequency for every shape can be obtained by sorting by shape information.

  The extraction unit 40 ends the process in the search unit 43 and determines whether there is an unprocessed block (step S56). When there is an unprocessed block, that is, when the processing is completed for all the blocks in the chip, the extraction unit 40 sets the next block as a search target (step S56-2), returns to step S50, and performs the same as described above. Repeat the process.

  On the other hand, when there is no unprocessed block, the extraction unit 40 performs analysis processing by the analysis unit 44. The analysis unit 44 analyzes the appearance frequency and accumulation of each shape (step S58). The analysis may be performed for each block after sorting for each block, or may be performed for each layer after sorting for one entire layer. The analysis unit 44 acquires information such as a shape, a position, and an appearance frequency from the labeling data 34, analyzes the information as chip information, and performs recalculation. The analysis unit 44 obtains an analysis result using a histogram, a map, or the like.

  FIG. 11 is a diagram for explaining the data structure of labeling data. In FIG. 11, the labeling data 34 is labeled No. , Position information (region), shape, symbol arrangement, block No. , Items such as rotation angle and displacement.

  Label No. Is a number that is uniquely given to a matching symbol sequence in a portion that matches the symbol sequence of the sequence library 35. It is a number that is labeled once or multiple times in the same block. The position information (region) is coordinate information that identifies a portion that matches the symbol array of the array library 35. The position is specified on a scale with one dot as one scale. The region of the symbol array is specified.

  The shape information is information indicating the pattern shape represented by the symbol array. The symbol sequence indicates the symbol sequence of the sequence library 35 detected in the block. Block No. Is a number that identifies a block in the layer.

  The rotation angle indicates a rotation angle with respect to a reference shape (reference shape). Even when the rotation angles are different, the shape information is managed by the reference shape. The shift indicates the shift direction of the shape. Even when the pattern shapes are shifted and arranged, the shape information is managed by the reference shape.

  In FIG. 11, the label No. is assigned to the pattern in the block BL1. The example labeled in [1]-[5] is shown. In the labeling data 34 shown in FIG. The shape of [1] and the label No. The shape rotated by 90 degrees in [2] indicates that the same shape “I-character-1” is searched. Also, label No. The shape of [4] and label No. The shape displaced in the half dot LR direction of [5] indicates that the search was performed with the same shape “L-character −1”. The LR direction indicates a half-dot shift to the left or right, and if the UD direction is indicated, it indicates a half-dot shift upward or downward.

  Next, a search processing example of the search unit 43 will be described with reference to FIG. FIG. 12 is a diagram illustrating an example of search processing. In FIG. 12, the sequence library 35 which is a lexicographic entity has a label No. It is assumed that the symbol arrangement specified by [1], [2], [3],. The search unit 43 searches whether the same symbol arrangement exists in the block in order from the largest symbol arrangement. In this example, the search order is [1]-> [8]-> [3]-> ...-> [2].

  For the symbol map MP1, label No. Search with the symbol array of [1], label No. Two symbol sequences of [1] are detected. Next, label No. The area in which [1] is recorded is skipped and the label No. Search with the symbol sequence of [8], label No. One place of the symbol array of [8] is detected.

  Subsequently, label No. By skipping the area where [1] and [8] are recorded, the label No. Search with the symbol sequence of [3], label No. One symbol array of [3] is detected. In this way, the search process is sequentially performed, and the label No. Search with the symbol sequence of [2], label No. One place of the symbol array of [2] is detected.

  As described above, label search is performed in order from the largest symbol array, and label recording is performed on the labeling data 34 for each detection. When label recording is completed for the entire area of the block, a label is recorded in the labeling data 34 in association with the matched area by the same processing as described above for the next block.

  Next, registration processing by the sequence library registration unit 50 will be described. FIG. 13 is a flowchart for explaining the sequence library registration process. In FIG. 13, in the data processing apparatus 100, the blocking process is performed by the blocking unit 51 of the array library registration unit 50 (STEP 1). The processing of STEP 1 is the same as the processing of STEP 1 of the extraction unit 40 (FIG. 5), but library graphic data 37 is used instead of the design data 31.

  In STEP 1, the blocking unit 51 reads the library graphic data 37, sets layer information registered in advance from the layer table 32 (step S 71), and then refers to the library graphic data 37 to be processed. The layer data area is decomposed (step S72), and the entire chip is made into blocks (fields) in units of layers (step S73). After the blocking, the blocking unit 51 develops the mask pattern for each block in the work area of the storage unit 130 (step S74).

  Next, the sequence library registration unit 50 performs symbolization processing by the symbolization unit 52 (STEP 2). Steps S75 to S76 correspond to STEP2. In STEP 2, the symbolizing unit 52 refers to the symbol library 33 and performs symbol conversion on all patterns in one block according to the symbolization rule (step S 75).

  The size of the area converted into one symbol managed by the symbol library 33 is a rectangle defined by one dot, as in the case of the processing in the extraction unit 40.

  The symbolizing unit 52 develops a symbol map in which each dot in one block is replaced with one symbol in the work area of the storage unit 130 (step S76).

  Next, the sequence library registration unit 50 performs selection processing by the selection unit 53 (STEP 3). Step S77 corresponds to STEP3. In STEP 3, the selection unit 53 selects a symbol area (step S77). The size of the area to be selected is arbitrary. If the selected areas do not overlap each other, the position to be selected is arbitrary. The designer may select appropriately.

  Then, the sequence library registration unit 50 performs registration processing by the registration unit 54 on the selected symbol area (STEP 3). Steps S78 to S81 correspond to STEP4.

  In STEP 4, the registration unit 54 extracts symbols in a predetermined order from the symbol area selected by the selection unit 53 from the symbol map (step S78), and processes the symbol array for registration in the array library 35 (step S79). Steps S78 and S79 correspond to creating a symbol array.

  Further, the registration unit 54 uses the symbol array as a reference array, and creates a symbol array that is grouped by regarding the symbol array as substantially the same shape as the reference array (step S80). Then, the registration unit 54 registers the reference array and the grouped symbol array in the array library 35 (step S81). At the time of registration, it is desirable to search within the block by the symbol arrangement to be registered and to suppress the selection of matching symbol areas. The sequence library registration unit 50 ends this process.

  FIG. 14 is a diagram for explaining the outline of the symbol array registration process. In FIG. 14, STEP 3 and STEP 4 described in FIG. 13 are repeated until registration of the symbol array relating to the shape to be extracted is completed.

  In step S77 of STEP 3, the symbol area 8a selected in the block is a 4 × 6 dot area.

  In steps S78 and S79 of STEP 4, a symbol is extracted from the upper left end of the symbol area 8a, and a return symbol “*” is added every time it is turned back in the symbol area 8a. By extracting to the lower right end of the symbol area 8a, a symbol array of the symbol area 8a is created.

  A symbol array 8b “GGGG * HHHF * HHAF * GGGF * HHHH” is created for the symbol region 8a. Registered with “5”. Also, a symbol array that is considered to be substantially the same as the symbol array 8 b is created, grouped, and registered in the array library 35.

  An example of symbol array registration processing by repeating STEP 3 and STEP 4 will be described with reference to FIGS. 15 and 16 are diagrams for explaining an example of symbol array registration processing.

  FIG. 15 shows a processing example corresponding to STEP2 to STEP3 of FIG. A state where labeling is performed for each symbol area is shown for one block in which the symbol area is selected.

  FIG. 16 shows a state in which a symbol array is created from the labeled symbol area by the procedure described in FIG. 14 and registered in the array library 35. Label No. The symbol sequences [1] to [7] are registered in the sequence library 35.

  In FIG. 15 and FIG. 16, the symbol array of the extracted partial shape [1] is registered in the array library 35. Next, the symbol array of the partial shape [2] is also registered, and the symbol library of the partial shapes [3]... [7] is also registered in order, whereby the sequence library 35 is constructed.

  In the sequence library 35, symbol sequences representing as many characteristic shape parts as possible are registered. Since features cannot be found if the size is too large or too small, it is desirable that the partial shape be symbolized and registered as shown in FIG. Further, the rule for creating the symbol array for registration is as described with reference to FIG. 14, and the symbol array for registration is created in the order from top to bottom from left to right.

  The grouping process at the time of registration in the sequence library 35 will be described with reference to FIG. FIG. 17 is a diagram illustrating a data configuration example of the sequence library. In FIG. 17, the array library 35 has items such as a label, a deviation classification, a symbol array, and a symbol area size, and a symbol array is stored for each group.

  The partial shapes in the symbol area are classified in the form of similar characters, numerical values, etc., and information expressed by the characters, numerical values, etc. is called a label. The deviation classification includes four classifications: a standard without deviation, top and bottom (UD), left and right (LR), and top and bottom and left and right.

  The reference corresponds to a symbol array that shows a partial shape by filling in dots. Therefore, the symbol arrangement is represented by A, F, *. The vertical (UD) shift indicates that the reference symbol array (reference array) is a symbol array when shifted half a dot up or down. The left / right (LR) shift indicates that the reference array is a symbol array when shifted to the left by half a dot or to the right. The vertical / horizontal shift indicates that the reference array is a symbol array when shifted to the upper left, shifted to the upper right, shifted to the lower left, or shifted to the lower right.

  The symbol arrangement indicates a partial shape in the symbol region corresponding to the deviation classification with a symbol. The symbol area size indicates the symbol area with dots.

  In the array library 35 of FIG. 17, a group recognized as a label “U-shaped” and a group recognized as a label “T-shaped” are illustrated. In the “U-shaped” group, the reference symbol arrangement is “* FFF * AAF * FAF * AAF * FFF *”, and the symbol area size is “3 × 5” dots.

  In the vertical (UD) shift, the symbol arrangement is “* GGG * HHF * GAF * HAF * GGF * HHH *”, and the symbol area size is “3 × 6” dots. In the left / right (LR) shift, the symbol array is “* JFFI * AAJI * JIJI * AAJI * JFFI *”, and the symbol area size is “4 × 5” dots. In the vertical and horizontal misalignment, the symbol array is “* EGGD * CHOI * EDJI * CBJI * EGNI * CHHB *”, and the symbol area size is “4 × 6” dots.

  In the group of the label “T”, the reference symbol arrangement is “* FFF * AFA * AFA * AFA *”, and the symbol area size is “3 × 4” dots. In addition, symbol arrangements corresponding to vertical (UD), horizontal (LR), vertical and horizontal misalignments are shown.

  Next, the selection of the symbol area and the label of the pattern will be described with reference to FIG. FIG. 18 is a diagram illustrating an example of registration in the sequence library. In FIG. 18, a region indicated by a rectangle indicated by a dotted line is shown. A symbol area is selected so that a partial shape of a characteristic pattern can be extracted. The degree of freedom, extraction constraints, and the like are adjustable and can be arbitrarily set.

  FIG. 18A shows an example in which the extraction pattern changes depending on the selection method of the symbol area, although the partial shapes are the same. Even when the L / S shape and the L end shape are the same, registration in the sequence library 35 differs depending on whether the selection is made including the blank portion (left) or not (left). For example, in the case of the left, the labels “L / S-1” and “L end-1” are registered. In the case of the right, the labels “L / S-2” and “L end-2” are registered.

  FIG. 18B shows a similar pattern for registering a hot spot (dangerous part) pattern in which a bridge (BRIDGE) where the patterns are in contact with each other and a neck (NECK) where the pattern is disconnected occurs during pattern formation. The case where the L shape is registered is shown. For example, in the case of the left, it is registered as the label “L go-1”. In the case of the right, it is registered as the label “L go-2”.

  FIG. 18C shows an example of another partial shape that can become a hot spot. In the case of the similar joint shape, in the case of the left, it is registered as a label “co-join-1”. In the case of the right, it is registered as a label “Kou-2”. In this way, patterns such as rotation and mirror can be registered.

  FIG. 19 is a diagram illustrating an example of a result of the analysis process. In FIG. 19A, based on the feature extraction data 36 obtained from the labeling data 34, the labels are shown on the horizontal axis, and the total for each label is shown on the vertical axis. FIG. 19B shows a display example of a layer color-coded for each extracted label.

  In this way, characteristic partial shapes can be extracted with high accuracy by the symbolization processing based on the above-described symbolization rules, grouping of symbol arrays, and the like.

  In the data processing apparatus 100 according to the present embodiment described above, the extraction process of the characteristic shape portion of the mask pattern in the extraction unit 40 can be performed efficiently. Description will be made by comparing the case where the present embodiment is not applied (FIG. 20) and the case of the data processing apparatus 100 to which the present embodiment is applied (FIG. 21). FIG. 20 is a diagram illustrating a processing example when the present embodiment is not applied. FIG. 21 is a diagram illustrating a processing example of the data processing device to which the present embodiment is applied.

  As an example when the present embodiment of FIG. 20 is not applied, the number of libraries n = 3 and the number of partial shape data m = 6 in the block BL1 are illustrated.

  Each of the three types of labels [A], [B], and [C] registered in advance in the library and the partial shape data [a], [b], [c], and [d] in the block Matching with each other is performed. Each of the partial shape data [a] and [b] exists in two places in the block, and [c] and [d] exist in one place.

  The partial shape data [a] is a shape having a characteristic detected by the label [A], and the partial shape data [b] is a shape having a characteristic detected by the label [B]. The data [c] is assumed to have a shape having a feature detected by the label [C]. The partial shape data [c] and [d] are shapes having characteristics other than the labels [A], [B], and [C].

  In this matching processing example, the label [A] is matched with each of the partial shape data at the six locations, so that six combinations of processing are required. Similarly, the label [B] needs to be processed in six combinations. Similarly, for label [C], six combinations of processing are required. Therefore, matching processing is required for a total of 18 combinations.

  On the other hand, in the case of the data processing apparatus to which the present embodiment of FIG. 21 is applied, the number of libraries n = 3 and the number of partial shape data m = 6 in the block BL1 are illustrated as in FIG. . The label search in the present embodiment corresponds to matching when the present embodiment in FIG. 20 is not applied.

  Each of the three types of labels [a], [b], and [c] registered in advance in the library and the partial shape data [A], [B], [C], and [D] in the block A label search with each is performed. Each of the partial shape data [A] and [B] exists in two places in the block, and [C] and [D] exist in one place.

  The partial shape data [A] is a shape having a characteristic detected by the label [a], and the partial shape data [B] is a shape having a characteristic detected by the label [b]. It is assumed that the data [C] has a shape having the characteristics detected by the label [c]. The partial shape data [C] and [D] are shapes having characteristics other than the labels [a], [b], and [c].

  In the present embodiment, the partial shapes in the block BL1 are labeled [a]-> [b]-> [c] in the descending order of the symbol arrangement in the arrangement library 32 (which can be said to be in the descending order of the symbol area). Perform a label search with the data. On the other hand, the symbol area where the label search is confirmed is skipped without performing a label search with the next label in the sequence library 32.

  Therefore, the label search with the label [a] indicating the maximum symbol arrangement is performed on all of the partial shape data [A], [B], [C], and [D] in the block BL1, After confirming the coincidence between [a] and the two [A], the subsequent label search with the partial shape data [b] and [c] is not performed for the two [A].

  The label search with the label [b], which is the next largest symbol array after the label [a], except for the partial shape data [A] in the block BL1, the partial shape data [B], [C], and [D ], But after confirming the coincidence between [b] and the two [B], the label search for the subsequent partial shape data [C] is not performed for the two [B]. .

  Further, the label search with the label [c], which is the next largest symbol array after the label [b], is performed except for the partial shape data [A] and [B] in the block BL1. C] and [D].

  The combination of the shape portion type as viewed from the symbol area searched for the label in the block BL1 is two sets of the labels [a] and [b] in the upper partial shape data [B], and the upper partial shape data. [A] is one set with the label [a], and the upper partial shape data [D] is three sets with the labels [a], [b], and [c].

  The lower partial shape data [B] has two sets of labels [a] and [b], and the lower partial shape data [B] has two sets of labels [a] and [b]. The lower partial shape data [A] is one set with the label [a], and the lower partial shape data [C] is three sets with the labels [a], [b], and [c]. Thus, the number of combinations decreases in the second half of the search order, and the label search can be performed efficiently.

  Therefore, a label search is performed with a total of 12 combinations. Compared to the case where the present embodiment shown in FIG. 20 is not applied, it is possible to reduce six processes. The greater the amount of partial shape data in the block BL1, the greater the effect of the present embodiment.

  As described above, according to the present embodiment, all patterns in a chip can be searched and classified by label search that performs symbolization and labeling for sequentially appearing patterns, and can be processed quickly and easily. .

  By grasping all the chip characteristics such as the shape, appearance frequency, appearance location, etc. of the feature part of the pattern in the LSI chip, the presence, scale and occupation rate of patterns that can become hot spots before data processing, and further processing It becomes possible to grasp time and the like.

  Therefore, this embodiment has effects such as prediction of complex pattern processing such as MDP (mask data conversion processing) and OPC (optical proximity effect correction) processing, improvement of correction processing accuracy, and reduction of processing time. Play.

  The present invention is not limited to the specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims.

The following additional notes are further disclosed with respect to the embodiment including the above examples.
(Appendix 1)
A storage unit storing an array library in which a symbol array representing a partial shape of a mask pattern designed on a chip is registered;
A data processing apparatus comprising: an extraction unit that extracts a partial shape by symbolizing a region where a mask pattern indicated by design data is formed and searching the symbol array in the array library.
(Appendix 2)
A first symbolizing unit that develops a symbol map in which the region is symbolized in the storage unit;
A search unit that searches for the partial shape from the symbol map using the symbol array registered in the sequence library;
The data processing apparatus according to claim 1, further comprising an analysis unit that analyzes chip characteristics based on a search result obtained by the search unit.
(Appendix 3)
3. The data processing apparatus according to claim 2, wherein the analysis unit analyzes at least the appearance frequency or the cumulative number of the symbol array regarded as the same as the symbol array as a chip characteristic.
(Appendix 4)
The storage unit stores a symbol library having a pattern in which one symbol is associated with each position and number of the partial shape of a mask pattern in a dot indicating one unit, the position overlapping with the vertex of the dot,
The data processing apparatus according to claim 2, wherein the symbolizing unit expands the symbol map in the storage unit by referring to the symbol library and replacing the region with one symbol for each dot.
(Appendix 5)
The supplementary note 3 is characterized in that the symbolizing unit replaces a portion of a partial shape overlapping the vertex of the same dot as the one pattern in the pattern with the same symbol as the symbol corresponding to the one pattern. Data processing equipment.
(Appendix 6)
The partial shape of the mask pattern is registered in the array library in association with a label specifying each partial shape,
The search unit labels the region of the partial shape using the label associated with the symbol arrangement detected in the symbol map, and skips the labeled region in the search of the next partial shape. The data processing device according to any one of appendices 2 to 5, which is characterized by the following.
(Appendix 7)
The sequence library has a plurality of the symbol sequences,
The data processing apparatus according to claim 6, wherein the search unit searches the symbol map from the sequence library in descending order of the symbol sequence.
(Appendix 8)
The search unit, when detecting the symbol arrangement in the symbol map, stores labeling data indicating at least the label associated with the symbol arrangement and the position of the symbol arrangement in the storage unit. The data processing device according to appendix 6 or 7.
(Appendix 9)
9. The data processing apparatus according to appendix 8, wherein the analysis unit analyzes the chip characteristics by using the label and at least the appearance frequency for each label with reference to the labeling data.
(Appendix 10)
A supplementary note, comprising: an array library registration unit that symbolizes an area in which a mask pattern indicated by registration graphic data is formed and registers a symbol array corresponding to a partial shape of the mask pattern in the array library The data processing apparatus according to any one of 1 to 9.
(Appendix 11)
A second symbolizing unit that develops in the storage unit a symbol map that symbolizes an area in which the mask pattern indicated by the graphic data is formed;
A selection unit for selecting a symbol region from the symbol map developed by the second symbolization unit;
11. The data processing apparatus according to claim 10, further comprising: a registration unit that registers a symbol array in the symbol area in the array library.
(Appendix 12)
The registration unit uses the symbol arrangement in the symbol area as a reference symbol arrangement, and another symbol arrangement when the reference symbol arrangement is shifted up and down, left and right, or up and down and left and right within the length of one side of the dot. 12. The data processing apparatus according to claim 11, wherein the data processing device is created, the reference symbol array and the another symbol array are grouped and registered in the array library.
(Appendix 13)
In the array library for storing the symbol array representing the partial shape of the mask mask pattern designed on the chip stored in the storage unit, the region where the mask pattern indicated by the graphic data for registration is formed is symbolized, Register a symbol array corresponding to the partial shape of the mask pattern,
A data processing program for causing a computer to execute a process of extracting a partial shape by symbolizing a region where a mask pattern indicated by design data is formed and searching the symbol array in the array library.
(Appendix 14)
A data processing method executed by a computer,
In the array library for storing the symbol array representing the partial shape of the mask pattern designed on the chip stored in the storage unit, the area where the mask pattern indicated by the graphic data for registration is formed is symbolized, Register the symbol array corresponding to the partial shape of the mask pattern,
A data processing method comprising extracting a partial shape by symbolizing a region where a mask pattern indicated by design data is formed and searching the symbol array in the array library.
(Appendix 15)
In the array library for storing the symbol array representing the partial shape of the mask pattern designed on the chip stored in the storage unit, the area where the mask pattern indicated by the graphic data for registration is formed is symbolized, Register the symbol array corresponding to the partial shape of the mask pattern,
A computer-readable data storage program storing a data processing program for causing a computer to execute a process of extracting the partial shape by encoding a region where a mask pattern indicated by design data is formed and searching the symbol array in the array library Storage medium.

11 CPU
12 RAM
13 ROM
14 Auxiliary storage device 15 I / F device 16 Display device 17 Communication device 18 Input device 18a Keyboard 18b Mouse 19 Drive device 20 Storage medium 31 Design data 32 Layer table 33 Symbol library 34 Labeling data 35 Array library 36 Feature extraction data 37 For library Graphic data 40 Extraction unit 41 Blocking unit 42 Symbolization unit 43 Search unit 44 Analysis unit 45 Result output unit 46 New sequence library creation unit 50 Sequence library registration unit 51 Blocking unit 52 Symbolization unit 53 Selection unit 54 Registration unit 100 Data Processing device 130 storage unit

Claims (10)

A storage unit storing an array library in which a symbol array representing a partial shape of a mask pattern designed on a chip is registered;
A data processing apparatus comprising: an extraction unit that extracts a partial shape by symbolizing a region where a mask pattern indicated by design data is formed and searching the symbol array in the array library. A first symbolizing unit that develops a symbol map in which the region is symbolized in the storage unit;
A search unit that searches for the partial shape from the symbol map using the symbol array registered in the sequence library;
The data processing apparatus according to claim 1, further comprising an analysis unit that analyzes chip characteristics based on a search result obtained by the search unit. The storage unit stores a symbol library having a pattern in which one symbol is associated with each position and number of the partial shape of a mask pattern in a dot indicating one unit, the position overlapping with the vertex of the dot,
3. The data processing apparatus according to claim 2, wherein the symbolizing unit develops the symbol map in the storage unit by referring to the symbol library and replacing the region with one symbol for each dot. .   The symbolizing unit replaces a portion of a partial shape overlapping the vertex of the same dot as the one pattern in the pattern with the same symbol as the symbol corresponding to the one pattern. The data processing apparatus described. The partial shape of the mask pattern is registered in the array library in association with a label specifying each partial shape,
The search unit labels the region of the partial shape using the label associated with the symbol arrangement detected in the symbol map, and skips the labeled region in the search of the next partial shape. The data processing device according to claim 2, wherein the data processing device is a data processing device.   The search unit, when detecting the symbol arrangement in the symbol map, stores labeling data indicating at least the label associated with the symbol arrangement and the position of the symbol arrangement in the storage unit. The data processing apparatus according to claim 5.   An array library registration unit that symbolizes a region in which a mask pattern indicated by registration graphic data is formed and registers a symbol array corresponding to a partial shape of the mask pattern in the array library. Item 7. The data processing device according to any one of Items 1 to 6. A second symbolizing unit that develops in the storage unit a symbol map that symbolizes an area in which the mask pattern indicated by the graphic data is formed;
A selection unit for selecting a symbol region from the symbol map developed by the second symbolization unit;
The data processing apparatus according to claim 7, further comprising: a registration unit that registers a symbol array in the symbol region in the array library.   The registration unit uses the symbol arrangement in the symbol area as a reference symbol arrangement, and another symbol arrangement when the reference symbol arrangement is shifted up and down, left and right, or up and down and left and right within the length of one side of the dot. 9. The data processing apparatus according to claim 8, wherein the data processing apparatus is created, groups the reference symbol array and the another symbol array, and registers them in the array library. In the array library for storing the symbol array representing the partial shape of the mask pattern designed on the chip stored in the storage unit, the area where the mask pattern indicated by the graphic data for registration is formed is symbolized, Register the symbol array corresponding to the partial shape of the mask pattern,
A data processing program for causing a computer to execute a process of extracting a partial shape by symbolizing a region where a mask pattern indicated by design data is formed and searching the symbol array in the array library.