JP6087663B2 - Configuration information generating apparatus and control method thereof - Google Patents

Description

  The present invention relates to a power control technique in an array-type arithmetic device composed of a plurality of arithmetic elements and dynamically reconfigurable.

  With the miniaturization of elements due to advances in semiconductor manufacturing technology, an enormous number of transistors are integrated on large scale integrated circuits (LSIs). However, due to an increase in power during operation and an increase in power due to leakage current during non-operation, there is a limit to improvement in performance due to process miniaturization and higher processor frequency. Therefore, in recent years, information processing in which a plurality of arithmetic elements such as a central processing unit (CPU), a digital signal processor (DSP), a single arithmetic unit, or an arithmetic unit combining a plurality of arithmetic units are mounted on a single LSI. The device is drawing attention. This is because high computing performance can be obtained by performing processing in parallel using a plurality of computing elements.

  However, although the number of computing elements can be increased and the theoretical performance can be improved by increasing the scale and integration, performance improvement and power saving cannot be achieved at the same time unless measures are taken to suppress the increased power consumption. In the future, power integration is an important issue because it is expected that a large number of computing elements will be installed with higher functionality and higher performance.

  The power consumed in the semiconductor integrated circuit includes dynamic power, which is power consumed during a functional operation, and static power, which is power consumed to supply power to the circuit. The dynamic power is consumed due to a current that flows when charging and discharging a parasitic capacitance that is driven in accordance with a signal change and a current that flows when the transistor is switched, such as a through current. Therefore, dynamic power can be reduced by suppressing signal changes within a range that does not hinder functional operation. As a typical power saving technique based on such a principle, there is clock gating, which is widely used. On the other hand, static power is power consumed for charge and leakage current charged in the parasitic capacitance of the transistor. As the process becomes finer, parasitic capacitance tends to decrease and leakage current increases. In particular, along with the reduction in the thickness of the polysilicon gate oxide film, the leak current has been increasing exponentially for a while.

  In order to reduce the leakage current, it is effective to limit the voltage supplied to the transistor to be small or to cut it off. For this reason, as a technique aimed at reducing leakage power, generally, power-off of blocks driven by the same power supply is widely used. Power shutoff in a semiconductor integrated circuit means that a power supply path to a location (power control area) that is the target of power shutoff is connected to a power source using a power switch composed of a transistor. This technology switches between conduction and interruption. At present, leakage current does not show an exponential increase as before due to improvements in materials and manufacturing methods, but since it continues to increase linearly, power cut-off technology will continue to be important. It is thought that.

  That is, this power shut-off technology is used to efficiently reduce the leakage power even in a large scale semiconductor integrated circuit. It is possible to suppress power consumption by configuring a plurality of power cut-off areas and performing fine power management that partially cuts off the power of operation elements that are not in operation.

  By the way, in the circuit block that is the target of power shutoff, once the power is shut off, the electric charge accumulated in the capacity in the block is discharged and decreases with time, and disappears. Therefore, in order to operate the circuit again after shutting off the power, it is necessary to accumulate charges again in the capacitors in the circuit block. For this reason, additional time is required for accumulating charges, which causes a reduction in processing performance.

  In view of such a situation, for example, in Patent Document 1, an instruction for operating each arithmetic circuit is detected in advance, and one or more arithmetic circuits corresponding to the detected instruction are activated prior to execution of the operation. There has been proposed a microprocessor that performs arithmetic operations simultaneously using the arithmetic circuits described above.

JP 2004-178613 A

  Since higher functionality and higher performance are required in the future, integration using advanced manufacturing processes will progress, and a large number of PEs are expected to be installed. Therefore, in order to efficiently reduce the leakage power, it is necessary to configure a plurality of power control areas and perform fine power management that partially shuts off the power of the PE that is not operating.

  However, the more power supply control regions are provided, the larger the area of the power switch portion becomes, and in addition, the control of power shutoff and return becomes more complicated. Further, when controlling the power shut-off / return, it is necessary to supply charges corresponding to the capacity of the circuit block, which consumes power (also referred to as charge power). In other words, when processing is mapped on the processor array, if processing is distributed and distributed over a plurality of power control areas, extra charge power is consumed. In the technique of the above-mentioned patent document 1, the activation of the arithmetic unit is activated prior to the execution of the calculation, and the number of power supply restoration / shut-off cannot be reduced, so that the problem of the charge power cannot be dealt with. .

  The present invention has been made in view of the above-described problems, and an object of the present invention is to suitably reduce power such as leakage power and charge power in an array type arithmetic apparatus having a plurality of PEs.

In order to solve the above-described problems, the configuration information generation apparatus of the present invention has the following configuration. That is, a configuration information generating device that generates configuration information used in an array type arithmetic device having a plurality of circuit blocks each including one or more arithmetic elements and individually configured to be capable of power supply control. Includes information defining which one or more circuit blocks of the plurality of circuit blocks are to be used, and the configuration information generation device is configured to use N ( N is an integer greater than or equal to 3) acquisition means for acquiring configuration information, and when the configuration information used by the array-type arithmetic unit is changed from the first configuration information to the Nth configuration information in order, the power is off. In order to reduce the number of circuit blocks that are changed to the power-on state, the K + 1-th configuration information based on the K-th configuration information (K is an integer satisfying 1 ≦ K ≦ N−2) and the K + 2nd configuration information. It has a correction means for correcting the configuration information.

  ADVANTAGE OF THE INVENTION According to this invention, the technique which enables electric power reduction suitably in an array type arithmetic unit can be provided.

It is a figure which shows the whole structure of the data processor which concerns on 1st Embodiment. It is a figure which shows the internal structure of a circuit block. It is a figure which shows an example of the internal structure of a calculation element. It is a figure which shows an example of an internal structure of a router. It is a figure which shows an example of structure information. It is a figure which shows an example of the data format of structure information. It is a figure which shows the internal structure of a calculation process allocation part. It is a figure which shows the internal structure of a circuit block discrimination | determination part. It is a figure which shows the whole structure of the semiconductor device carrying the data processor which concerns on 1st Embodiment. It is a figure which shows an example of arrangement | positioning of the structure information in an external memory. It is a figure which shows the block configuration of a structure information generation apparatus. It is a figure which shows an example of a circuit block setting. It is a flowchart explaining the process which reproduces | regenerates configuration information. It is a flowchart explaining the process which calculates the frequency | count of power supply switching. It is a figure which shows an example of a circuit block selection list. It is a figure explaining the method of calculating the minimum frequency | count of power supply switching. It is a flowchart explaining a priority setting process. It is a figure which shows an example of a priority setting list | wrist. It is a flowchart explaining the process of a circuit block setting. It is a figure explaining the process of the change of the processing state in a data processor. It is a figure explaining the process of the change of the circuit block which configuration information selects. It is a figure which shows the generated circuit block selection list by way of example. It is a figure which shows the priority list produced | generated illustratively. It is a figure which shows the change of a data flow as an example. It is a figure which shows the change of a data flow as an example. It is a figure which shows the whole structure of the data processor which concerns on a modification. It is a figure which shows the internal structure of the arithmetic processing allocation part which concerns on 2nd Embodiment. It is a figure which shows the internal structure of a structure information generation part. It is a figure which shows the internal structure of the power supply switching frequency calculation part. It is a figure which shows the internal structure of a circuit block priority setting part.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are merely examples, and are not intended to limit the scope of the present invention.

(First embodiment)
As a first embodiment of the present invention, a data processing apparatus 100 (arithmetic system) including a dynamic reconfiguration circuit 106 that is an array type arithmetic apparatus will be described below as an example. In particular, an operation for generating configuration information that reduces the number of times of power supply switching in a circuit block in the dynamic reconfiguration circuit 106 will be described.

<1. Device configuration>
<1.1. Configuration of data processing apparatus>
FIG. 1 is a diagram showing an overall configuration of a data processing apparatus 100 according to the first embodiment. The data processing apparatus 100 includes a dynamic reconfiguration circuit 106, an operation processing allocation unit 105, and a power supply control unit 103. As will be described below, the data processing apparatus 100 performs processing using the dynamic reconfiguration circuit 106 based on configuration information 108 input from the outside. The configuration information 108 is generated by a configuration information generation device 1100 described later.

  The dynamic reconfiguration circuit 106 includes a plurality of circuit blocks 102 including at least one arithmetic element 101. Each computing element 101 and each router 104 are connected in one direction by a signal line 111. The signal line 111 is provided for each circuit block 102 as shown in FIG.

  The circuit block 102 is a block including the arithmetic element 101 and the router 104. The circuit block 102 is supplied with a power supply voltage VDD via a power switch 107 from a power supply circuit block (not shown). Each circuit block 102 is configured to be individually controllable (power cutoff and power supply switching). Each circuit block 102 is connected with a power switch 107 for switching between power shutdown and power supply.

  The arithmetic processing assigning unit 105 acquires the configuration information 108 and transmits circuit block information to the power supply control unit 103 via the signal line 114. Note that the assignment of the arithmetic processing described here means associating the processing with a component (the arithmetic element and the router) that executes the processing. Here, the setting value in the configuration information is written inside each component (calculation element or router), thereby assigning the process to the component.

  The arithmetic processing assignment unit 105 transmits the configuration information 108 to each circuit block 102 in parallel via the signal line 111 and then receives the configuration information 108 to be used next. In addition, after the transmission of the configuration information 108, the arithmetic processing assignment unit 105 transmits a signal instructing the arithmetic element 101 to start arithmetic processing via the signal line 117. The arithmetic processing allocation unit 105 receives a signal notifying the completion of processing via the signal line 112 when the arithmetic element 101 completes the arithmetic processing. Here, in order to transmit a signal instructing the start of the arithmetic processing from the arithmetic processing assigning unit 105 to each arithmetic element 101 in parallel, the same number of signal lines 117 as the number of arithmetic elements 101 are provided. In addition, since the arithmetic processing assignment unit 105 receives a signal for notifying the completion of processing in parallel from each arithmetic element 101, the same number of arithmetic elements 101 are provided for the signal lines 112.

  The power control unit 103 receives circuit block information from the arithmetic processing allocation unit 105 and switches the power switch 107 on and off via the signal line 110. In addition, the power control unit 103 notifies the arithmetic processing allocation unit 105 that the switching of the power switch has been completed via the signal line 113.

  FIG. 2 is a diagram illustrating an internal configuration of the circuit block 102. The calculation element 101 has four input units and output units, and the router 104 has eight input units and output units.

  The arithmetic element 101 is connected to the router by signal lines 201-208. The arithmetic element 101 is a processing unit that processes data supplied from the data input signal lines 201 to 204 and outputs processing data from the data output signal lines 205 to 208. The arithmetic element 101 receives a signal instructing the start of arithmetic processing from the arithmetic processing allocation unit 105 via the signal line 117. After the processing is completed, the arithmetic element 101 transmits a signal notifying the processing completion to the arithmetic processing assigning unit 105 via the signal line 112.

  The router 104 is connected to other routers adjacent in the circuit block by signal lines 209 to 216. Signal lines 210, 211, 213, and 215 are signal lines for the router 104 to receive data from other adjacent routers. On the other hand, signal lines 209, 212, 214, and 216 are signal lines for the router 104 to transmit data to other adjacent routers.

  FIG. 3 is a diagram illustrating an example of the internal configuration of the calculation element 101. The calculation element 101 includes a configuration information setting unit 301, a configuration information storage unit 302, a calculation processing unit 303, a data input unit 304, and a data output unit 305.

  The configuration information setting unit 301 receives the configuration information 108 via the signal line 111. In addition, the configuration information setting unit 301 transmits a setting value for switching the input to the data input unit 304 via the signal line 306. In addition, the configuration information setting unit 301 transmits a setting value for determining the processing content to the arithmetic processing unit 303 via the signal line 307. Further, the configuration information setting unit 301 transmits a setting value for switching output to the data output unit 305 via the signal line 308.

  FIG. 4 is a diagram illustrating an example of the internal configuration of the router 104. The router 104 includes a configuration information setting unit 401, a configuration information storage unit 402, and an input / output switching unit 403. The configuration information setting unit 401 receives the configuration information 108 via the signal line 111. The configuration information setting unit 401 transmits a setting value for switching input / output to the input / output switching unit 403 via the signal line 404.

  FIG. 5 is a diagram illustrating an example of the configuration information 108. This configuration information 108 defines the dynamic configuration of the data processing apparatus 100. The configuration information 108 is information including setting data 501 for the calculation element and setting data 502 for the router. Here, a case is shown in which there are X computation element setting data 501 and Y router setting data 502. That is, the configuration information 108 in FIG. 5 is data including settings for X computing elements and Y routers. FIG. 5 shows an example in which the configuration information for one component (arithmetic element or router) is N-bit binary data.

  FIG. 6 is a diagram illustrating an example of the data format of the configuration information. Here, an example is shown in which the same data format is used for both the setting data 501 for the calculation element and the setting data 502 for the router. The setting data includes an identification number (ID) 601, an address 602, and a setting value 603.

  The ID 601 is an identification number that is uniquely set for each computation element or router. The address 602 designates a writing area of the configuration information storage units 302 and 402 when the setting value 603 is written to each calculation element or the configuration information storage units 302 and 402 inside the router. A setting value 603 is a value for setting the operation of the computing element 101 and the router 104.

  FIG. 7 is a diagram illustrating an internal configuration of the arithmetic processing assignment unit 105. The arithmetic processing assigning unit 105 includes a configuration information receiving unit 701, a configuration information transmitting unit 702, an ID determining unit 703, and a circuit block determining unit 704. The configuration information receiving unit 701 transmits an instruction to read the configuration information 108 via the signal line 115 and receives the configuration information 108 via the signal line 116. Thereafter, the configuration information receiving unit 701 transmits the configuration information 108 to the ID determining unit 703 and the configuration information transmitting unit 702.

  The ID determination unit 703 receives the configuration information 108 from the configuration information reception unit 701 and transmits the ID 601 to the circuit block determination unit 704. The circuit block determination unit 704 receives the ID 601 from the ID determination unit 703 and outputs circuit block information via the signal line 114. For example, the circuit block determination unit 704 may be configured to internally include a table that associates the ID 601 with the circuit block.

  The configuration information transmitting unit 702 receives the configuration information 108 from the configuration information receiving unit 701 after being notified that the switching of the power switch is completed via the signal line 113. Thereafter, the configuration information transmission unit 702 transmits the configuration information 108 to the dynamic reconfiguration circuit 106 via the signal line 111. Further, the configuration information transmitting unit 702 receives the configuration information 108 that has made a round in the circuit block via the signal line 111. Further, the configuration information transmission unit 702 transmits a signal instructing the start of the arithmetic processing to each arithmetic element 101 via the signal line 117, and notifies the completion of the arithmetic processing from each arithmetic element 101 via the signal line 112. Receive a signal.

  FIG. 8 shows an example of the internal configuration of the circuit block determination unit 704. The circuit block determination unit 704 includes an ID information storage unit 801, an ID comparison unit 810, registers 802, 803, 805, and 806, OR circuits 811 and 812, and a circuit block information transmission unit 809.

  The ID information storage unit 801 is a unit that stores an ID set in each computation element or router. For example, the ID information storage unit 801 may be implemented by a ROM and ID information may be stored in advance. The ID comparison unit 810 receives the ID 601 transmitted via the signal line 707 and compares it with the ID stored in the ID information storage unit 801. The ID comparison unit 810 transmits the comparison result to the registers 805 and 806. As many ID comparison units 810 as the number of operation elements and routers in the dynamic reconfiguration circuit 106 are arranged. Here, as a result of comparison, if the IDs match, a logical value “1” is output as a comparison result, and if they do not match, a logical value “0” is output as a comparison result.

  The registers 805 and 806 hold the comparison result transmitted from the ID comparison unit 810. Each register is connected to the ID comparison unit 810 on a one-to-one basis through a signal line 804. The register 805 corresponds to the arithmetic element and router belonging to the first circuit block, and the register 806 corresponds to the arithmetic element and router belonging to the second circuit block. That is, the values of the registers 805 and 806 indicate which calculation element and router are selected by the configuration information 108.

  The OR circuit 811 calculates the logical sum of the values stored in the register 805 and transmits the result to the register 802. In addition, the OR circuit 812 transmits a result obtained by calculating a logical sum of the values stored in the register 806 to the register 803. That is, the values of the registers 802 and 803 indicate which circuit block is selected by the configuration information 108. The register 802 holds the values transmitted from the OR circuits 811 and 812, and then transmits the values to the circuit block information transmission unit 809.

  The circuit block information transmission unit 809 receives setting values from the registers 802 and 803 and transmits them to the signal line 114. Here, in order to reduce wiring, the setting values received from the registers 802 and 803 are serialized and transmitted when transmitting the setting values. However, the setting values received from the registers 802 and 803 may be transmitted in parallel if implementation is possible.

  The configurations of the arithmetic processing assignment unit and the circuit block determination unit are not limited to the configurations shown in FIGS. For example, a process equivalent to the circuit block of FIG. 7 may be realized by software processing using a CPU. If the circuit block information is included in the configuration information in advance, the configuration information may be transmitted directly from the configuration information receiving unit 701 to the circuit block determining unit 704 without including the ID determining unit 703. It ’s fine.

<1.2. Configuration of Semiconductor Device>
FIG. 9 is a diagram showing an overall configuration of a semiconductor device 908 equipped with the data processing apparatus 100 according to the first embodiment. The semiconductor device 908 includes a reconfiguration device 900 and an external memory 905. The reconfiguration device 900 includes a data processing apparatus 100, a CPU 901, a bus 902, an interface (I / F) 903, and an input / output unit (I / O) 904.

  The CPU 901 controls the entire reconfigurable device. A memory 905 is a memory (ROM / RAM) for storing configuration information 108, a boot program, an OS (operating system), and applications.

  FIG. 10 is a diagram illustrating an example of arrangement of configuration information in the external memory 905. Here, each piece of configuration information is stored in order from the upper address of the external memory 905 according to the switching order of the configuration information.

  That is, the configuration information 1001 is first configuration information for realizing the first data processing, and the configuration information 1002 is second configuration information for realizing the second data processing. Here, the first configuration information 1001 is stored in the first address area 1003, and the second configuration information 1002 is stored in the second address area 1004.

  An I / F 903 is an interface that communicates with the external memory 907. An I / O 904 is an interface for the reconstruction device 900 to input / output the configuration information 108 and data to be processed (image data or the like). The I / F 903 is a bus for communicating with the CPU 901, the data processing apparatus 100, the I / F 903, and the I / O 904.

<1.3. Configuration of Configuration Information Generation Device>
FIG. 11 is a diagram illustrating a block configuration of a configuration information generation apparatus 1100 that generates configuration information to be supplied to a semiconductor device.

  The CPU 1101 controls the entire apparatus. A ROM 1102 stores a boot program and BIOS, and a RAM 1103 is used as a work area of the CPU 1101 and stores an OS and applications. A hard disk drive (HDD) 1104 is an OS, an application for creating the configuration information 108, and a storage unit for storing various data.

  A keyboard 1105 and a mouse 1106 function as a user interface. The display control unit 1107 includes a video memory and a display controller. The display device 1108 receives the video signal from the display control unit 1007 and displays it. Reference numeral 1109 denotes an interface that communicates with various external devices. For example, by connecting the external memory 1110 illustrated in FIG. 11, the configuration information 108 created by the configuration information generation apparatus 1100 is written into the external memory 1110. .

<2. Operation of the device>
<2.1. Operation of data processing apparatus>
First, the operation of the arithmetic processing assignment unit 105 will be described. The configuration information receiving unit 701 requests the external memory 905 to read the configuration information 108 and receives the configuration information 1008 from the external memory 905 via the bus 902. After receiving the configuration information 108, the circuit block determination unit 704 determines a circuit block corresponding to the ID 601 by referring to a table that associates the ID 601 and the circuit block provided in the circuit block determination unit 704. Thereafter, the circuit block determination unit 704 transmits information about the determined circuit block to the power supply control unit 103.

  When the configuration information transmission unit 702 detects that the switching of the power switch 107 is completed from the power control unit 103, the configuration information transmission unit 702 transmits the configuration information 108 to the circuit block 102. For example, the configuration information transmission unit 702 transmits the configuration information 108 in units of data shown in FIG. 6 (that is, in units of N bits), and counts the number of times the data has been transmitted within the configuration information transmission unit 702. Hold the value. Further, for example, the configuration information transmission unit 702 receives the configuration information 108 in units of data illustrated in FIG. 6 via the signal line 111. The configuration information transmission unit 702 counts the number of times the configuration information 108 has been received within the configuration information transmission unit 702 and holds the value.

  The configuration information transmission unit 702 compares the internally counted value of the number of transmissions with the value of the number of receptions, and detects that the transmission of the configuration information 108 is complete when the values match. . That is, the configuration information transmission unit 702 detects that the transmission of the configuration information 108 is completed when the number of times the configuration information 108 is transmitted matches the number of times the configuration information 108 is received. When the configuration information transmission unit 702 detects that the transmission of the configuration information 108 is completed, the configuration information transmission unit 702 instructs the calculation element 101 to start the calculation process.

  Further, the configuration information transmission unit 702 receives the process completion notification from the calculation element 101, determines whether the process completion notification has been transmitted from all the calculation elements 101 assigned the calculation process, and completes the data processing. Detecting that After that, the configuration information receiving unit 701 requests the external memory 905 to read the next configuration information 108 and receives the next configuration information 108 from the external memory 905 via the bus 902.

  Next, the operation of the power control unit 103 will be described. After receiving the circuit block information from the arithmetic processing assigning unit 105, the power control unit 103 determines a circuit block that requires power supply or power shutoff, and a power switch 107 connected to the circuit block that requires power supply. Switch from off to on.

  The power supply control unit 103 notifies the arithmetic processing assignment unit 105 that the switching of the power switch is completed via the signal line 113 when a predetermined time has elapsed after switching the power switch 107 from OFF to ON. The predetermined time is set, for example, as the time for the circuit block voltage to reach a certain level. In addition, the power control unit 103 switches the power switch 107 connected to the circuit block that shuts off the power from on to off.

  Next, the operation of the computing element shown in FIG. 3 and the router shown in FIG. 4 will be described. The arithmetic element 101 receives the configuration information 108 transmitted via the signal line 111. Thereafter, the configuration information setting unit 301 inside the calculation element 101 determines whether the ID 601 of the configuration information 108 matches the ID set for itself (the calculation element 101).

  When the IDs match, the configuration information setting unit 301 writes the setting value 603 of the configuration information 108 to the configuration information storage unit 302 inside the calculation element 101 according to the address specified by the configuration information 108. On the other hand, if the IDs do not match, the configuration information setting unit 301 outputs the configuration information 108 to the signal line 111.

  The configuration information setting unit 301 inside the calculation element 101 transmits the setting value 603 to the data input unit 304, the data output unit 305, and the calculation processing unit 303 after the completion of the writing. Thereafter, the input switching of the data input unit 304, the output switching of the data output unit 305, and the processing setting of the arithmetic processing unit 303 are completed. With this processing setting, it is set from which signal line the data input unit 304 inputs data among the signal lines 201 to 204. In addition, it is set which signal line the data output unit 305 outputs from among the signal lines 205 to 208.

  After the transmission of the configuration information 108 is completed, each calculation element starts a calculation process for data to be processed (image data or the like). When the calculation process is completed, each calculation element notifies the calculation process assignment unit 105 of the completion of the process.

  The router 104 receives the configuration information 108 transmitted via the signal line 111. Thereafter, the configuration information setting unit 401 inside the router 104 determines whether the ID 601 of the configuration information 108 matches the ID set in the router 104.

  When the IDs match, the configuration information setting unit 401 writes the setting value 603 of the configuration information 108 to the configuration information storage unit 402 inside the router 104 according to the address specified by the configuration information 108. On the other hand, if the IDs do not match, the configuration information setting unit 401 outputs the first configuration information 108 to the signal line 111.

  The configuration information setting unit 401 transmits the setting value 603 to the input / output switching unit 403 after the writing is completed. Thereafter, input / output switching of the input / output switching unit 403 is performed.

  Whether the input / output switching unit 403 inputs data from any one of the signal lines 208 to 215 and outputs data from any one of the signal lines 204 and 216 to 222 according to the set value. Is set. For example, the setting is made such that data is input from the signal line 208 and the input data is output from the signal line 222.

<2.2. Operation of Semiconductor Device>
When the semiconductor device 908 is powered on, the CPU 901 executes a boot program stored in the external memory 905 to start up the semiconductor device 908. Next, the CPU 901 reads the configuration information 108 from the I / O 904 and instructs the external memory 905 to store the configuration information 108. After storing the configuration information 108 in the external memory 905, the CPU 901 instructs the data processing apparatus 100 to read the configuration information 108.

  The data processing apparatus 100 requests the external memory 905 to read the configuration information 108 and receives the configuration information 108 from the external memory 905 via the bus 902. For example, the configuration information 108 is read in the order of first configuration information and second configuration information.

  Thereafter, processing is allocated in accordance with the configuration information 108 within the data processing apparatus 100. After the processing assignment is completed, processing target data is input from the I / O 904 and data processing is executed inside the data processing apparatus 100. The data processing device 100 reads a plurality of pieces of configuration information in order, and switches the operation of the dynamic reconfiguration circuit 106.

<2.3. Operation of Configuration Information Generation Device>
When the configuration information generating apparatus 1100 is powered on, the CPU 1101 executes the boot program stored in the ROM 1102 and loads the OS stored in the HDD 1104 into the RAM. After that, by starting an application for creating the configuration information 108, it functions as a configuration information creation device.

  The configuration information 108 created by the configuration information generation apparatus 1100 is written into the external memory 905 of the semiconductor device 908, for example. At this time, for example, the configuration information 108 is input to the semiconductor device 908 via the I / O 904.

  Hereinafter, a process when the configuration information generation apparatus 1100 generates the configuration information 108 will be described. The configuration information generation apparatus 1100 executes an application process in the CPU 1101 after starting an application that creates the configuration information 108.

  The user inputs data processing information using a keyboard and a mouse. For example, a program in which the contents of data processing are described is input as data processing information. The CPU 1101 acquires data processing information input by a user operation and stores it in the RAM 1103. Thereafter, the CPU 1101 reads the data processing information stored in the RAM 1103 and executes processing for generating configuration information.

  Note that the configuration information generation apparatus 1100 performs mapping of processing to the computation element 101 using data processing information when generating configuration information for the first time. However, the configuration information generation apparatus 1100 regenerates (corrects) the configuration information based on the first configuration information generated after the mapping is executed. In particular, in the first embodiment, the circuit block selected by each configuration information is discriminated, and the circuit block 102 selected by each configuration information is reselected so that the number of times of power supply switching to the circuit block is reduced. The corrected configuration information is generated.

  Here, as an example, the data processing apparatus 100 reads a plurality of configuration information one after another in the order of first configuration information → second configuration information → third configuration information and switches processing operations. explain. In particular, here, a method for regenerating configuration information that minimizes the switching of power on and off will be described.

  FIG. 12 is a diagram illustrating an example of circuit block setting indicating the configuration of the circuit block. Here, circuit block settings are used as input data as a constraint when generating configuration information. The circuit block setting includes information on the circuit block to which each arithmetic element and router belong.

  The circuit block setting may be, for example, table information in which each calculation element and router ID are set in the first column and the circuit block ID is set in the second column as shown in FIG. Here, the circuit block ID is an identification number (ID) that is uniquely set for each circuit block in order to identify each circuit block. For example, the circuit block ID is set as shown in FIG. FIG. 12B shows an example in which a unique ID is set for each of the 16 circuit blocks.

  FIG. 13 is a flowchart illustrating a process for regenerating configuration information. This process is executed by the CPU 1101 executing an application. Here, an example will be described in which three pieces of configuration information generated first are processed to generate one piece of corrected configuration information. Specifically, first, the corrected second configuration information is generated based on the original first to third configuration information that are used continuously. Next, processing is executed using the second to fourth configuration information (the corrected second configuration information and the original third to fourth configuration information), and the corrected third configuration information is obtained. Generate. Thereafter, the same processing is repeated to generate each piece of configuration information.

  In step S1301, the number of configuration information is acquired and substituted for N. In step S1301, K is set to “1”. Here, N is the number of pieces of configuration information to be input (N pieces of configuration information (N is an integer of 3 or more)). K is a variable used in the processing of FIG.

  In step S1302, the ID selected by the Kth to (K + 2) th configuration information is acquired. Then, based on the circuit block setting shown in FIG. 12A, the ID is compared with the circuit block to determine the circuit block to be used in each piece of configuration information. Also, the number of circuit blocks used for each configuration information is calculated.

  In step S1303, based on the determination result of the circuit block in step S1302, the actual number of power supply switching times of each circuit block when switching the configuration information from the Kth to the K + 1th is calculated (calculation of the number of control target blocks). . Details of the processing in step S1303 will be described later with reference to FIG.

  In step S1304, when the configuration information is switched from the Kth to the K + 1th, based on the determination result in S1302, the minimum number of times of switching from power-off to on is calculated (minimum value calculation).

  FIG. 16 is a diagram for explaining a method of calculating the minimum number of power supply switching times. In FIG. 16, the following values are set for the values of A, B, and C, respectively.

A: Number of circuit blocks selected by the Kth configuration information B: Number of circuit blocks selected by the K + 1st configuration information C: Number of circuit blocks selected by the K + 2nd configuration information Step S1305 Then, the actual number of times of power supply switching calculated in step S1303 is compared with the minimum number of times of power supply switching calculated in step S1304 to determine whether the number of times is the minimum. As a result of the determination, if the number of times of switching is the minimum, configuration information is not generated and the process is terminated. As a result of the determination, if the number of times of switching is not the minimum, the process proceeds to the next process.

  In step S1306, the priority of the circuit block selected by the (K + 1) th configuration information is set from the information of the circuit block selected by the Kth and (K + 2) th configuration information. Details of the processing in step S1306 will be described later with reference to FIG.

  In step S1307, the circuit block selected by the (K + 1) th configuration information is set based on the priority set in step S1306. Details of the processing in step S1307 will be described later with reference to FIG.

  In step S1308, 1 is added to the variable K. In step S1309, it is determined whether K is N−1 or more. As a result of the determination, if K is N−1 or more, the process proceeds to step S1310. As a result of the determination, if K is less than N−1, the process is re-executed from step S1302. In this way, the configuration information is changed so that the number of circuit blocks subject to power supply control is reduced when the first configuration information is changed in order from the first configuration information to the Nth configuration information.

  In step S1310, the calculation element and router included in the circuit block set in step S1307 are selected, the ID setting 601 and the setting value 603 of the calculation element 101 and router 104 of each configuration information are changed, and the configuration information is output. To do. That is, the ID setting of the (K + 1) th configuration information is changed to the IDs of the computing element 101 and the router 104 in the circuit block set in step S1307. Also, when changing the data flow, the input / output setting values of the computing element 101 of the (K + 1) th configuration information and the router 104 are changed so that the input / output setting is in line with the data flow. The change of the setting value when changing the data flow will be described later with reference to FIGS.

  In the above description, the example in which three pieces of first generated configuration information are processed and one piece of corrected configuration information is generated has been described. However, two pieces of first generated configuration information are processed, You may comprise so that the structure information after correction may be produced | generated one. For example, specifically, first modified second configuration information is generated based on the original first to second configuration information. Next, processing is executed using the second to third configuration information (the corrected second configuration information and the original third configuration information) to generate corrected third configuration information. Thereafter, the same processing may be repeated to generate each piece of configuration information.

  FIG. 14 is a flowchart for explaining the process (S1303) for calculating the number of times of power supply switching. FIG. 15 is a diagram exemplarily showing a circuit block selection list 1501 generated during the execution of the processing of FIG.

  The list 1501 is a list indicating whether or not a circuit block is selected by configuration information. The leftmost column indicates the circuit block ID, and the first to third columns indicate whether the circuit block is selected by the configuration information. Here, the value is “1” when the circuit block is selected according to the configuration information, and the value is “0” when the circuit block is not selected. The list 1501 is empty when the process of step S1302 is completed.

  In step S1401, K is substituted for variable M. Here, M is a variable used in the processing of FIG. In step S1402, one of the circuit blocks not included in the list 1501 in FIG. 15 is arbitrarily selected.

  In step S1403, it is determined whether the circuit block selected in step S1402 is the circuit block selected in the Mth configuration information. If it is determined that the circuit block is selected by the Mth configuration information, the process proceeds to step S1404. If it is determined that the circuit block is not selected by the Mth configuration information, the process proceeds to step S1405. move on.

  In step S1404, the value of the Kth column in the list is set to “1”. In step S1405, the value of the Kth column in the list is set to “0”. In step S1406, M is incremented by one.

  In step S1407, it is determined whether M is equal to or greater than K + 2. As a result of the determination, if M is K + 2 or more, the process proceeds to step S1408. If the result of determination is that M is less than K + 2, the process returns to step S1403.

  In step S1408, it is determined whether the list 1501 includes setting values for all circuit blocks. As a result of the determination, if the list 1501 does not include setting values for all circuit blocks, the process returns to step S1402. On the other hand, as a result of the determination, if all the circuit blocks are included in the list 1501, the process proceeds to step S1408.

  In step S1409, the number of times of power supply switching is calculated based on the list of FIG. 15 generated by the processing in steps S1401 to S1408. The number of times of switching the power supply of each circuit block can be obtained, for example, by the following logical operation.

Number of times of switching = A￣ / B + B￣ / C (1)
Here, “A” is the value of the first column, “B” is the value of the second column, and “C” is the value of the third column. ￣ represents negation (NOT). According to Expression (1), the number of times of switching the power supply of each circuit block is obtained as a value represented by a binary number.

  FIG. 17 is a flowchart illustrating the priority setting process (S1306). FIG. 18 is a diagram exemplarily showing a priority setting list 1801 generated by the processing of FIG.

  The left side of the list 1801 indicates the ID of the circuit block, and the right side indicates the priority setting of each circuit block. In this setting, for example, values 1, 2, and 3 are set in order from the lowest priority to the highest priority. The list 1801 is empty when the process of step S1306 is completed.

  In step S1701, one arbitrary circuit block whose priority is not set in the list 1801 is specified. In step S1702, it is determined whether the circuit block specified in step S1701 is a circuit block selected in common in the Kth configuration information and the K + 2nd configuration information. If the circuit block is selected in common in the Kth configuration information and the K + 2nd configuration information, the process proceeds to step S1703. If the circuit block is not selected in common in the Kth configuration information and the K + 2nd configuration information, the process proceeds to step S1705.

  In step S1703, the priority of the circuit block is set to “3” which is relatively highest. In step S1705, it is determined whether the circuit block selected in step S1701 is a circuit block selected by either the Kth configuration information or the K + 2nd configuration information. If it is a circuit block selected by either the Kth and K + 2nd configuration information, the process proceeds to step S1706. If the circuit block is not selected in any of the Kth configuration information and the K + 2nd configuration information, the process proceeds to step S1707. In step S1706, the priority of the circuit block is set to “2”, which is the second highest relative. In step S1707, the priority of the circuit block is set to “1” which is relatively lowest.

  In step S1708, the setting value of the priority of the circuit block set in steps S1703, S1706, and S1707 is added to the right side of the list of FIG. In step S1709, it is determined whether the priority setting values of all circuit blocks selected in the (K + 1) th configuration information are included in the list generated in step S1708. If there is a circuit block that is not included in the list as a result of the determination, the process returns to step S1701. As a result of the determination, if the priority setting values of all circuit blocks are included in the list, the priority setting process is terminated.

  As described above, the priority of the circuit block selected by the (K + 1) th configuration information is set. Note that a new priority setting may be added to the processing flow of FIG. 17 by adding determination conditions other than those in steps S1702 and S1705. For example, the priority weight of the circuit block selected by the Kth configuration information may be set higher than the priority weight of the circuit block selected by the K + 2nd configuration information.

  FIG. 19 is a flowchart for explaining the circuit block setting process (S1307).

  In step S1901, the number of circuit blocks selected by the (K + 1) th configuration information is substituted for the variable m. Also, the value of the variable n is set to 0. Note that the variable m indicates the number of circuit blocks selected in the (K + 1) th configuration information, and the variable n indicates the number of circuit blocks selected in the process of FIG.

  In step S1902, the circuit block having the highest priority setting from the list 1801 is set to a selectable state. In step S1903, one of the circuit blocks selected in step S1902 is selected and added to the number n of circuit blocks.

  In step S1904, it is determined whether the result of addition in step S1903 is equal to or greater than the number of circuit blocks selected in the (K + 1) th configuration information (m ≧ n). If m ≧ n as a result of the determination, the process proceeds to step S1906. If m <n as a result of the determination, the process proceeds to step S1905.

  In step S1905, it is determined whether there is another selectable circuit block. As a result of the determination, if there is another selectable circuit block, the process of step S1903 is executed again. As a result of the determination, if there is no other selectable circuit block, the process proceeds to step S1906. In step S1906, the circuit block having the next lower priority is set to a selectable state. After the setting, the process returns to step S1903.

  In step S1907, it is determined that the corrected K + 1-th configuration information is generated using the circuit block selected in the processing of steps S1901 to S1906.

  In this way, the CPU 1101 generates the configuration information 108 so that the number of power supply switching operations is reduced. The generated configuration information 108 is read into the data processing apparatus 100 and used for setting the calculation elements and routers inside the data processing apparatus 100.

  Note that a step of reconstructing the data flow may be provided before executing step S1310. For example, after setting the circuit block to be used in the configuration information, the computing element 101 and the router 104 to be used are determined, and the data transfer route between the computing element 101 and the router 104 is searched to reconstruct the data flow. You can also take a technique.

<3. Operation Example of Data Processing Device Based on Generated Configuration Information>
A series of operations until the data processing apparatus 100 acquires the configuration information 108 from the external memory 905 and allocates arithmetic processing to the circuit block 102 along the configuration information 108 will be described.

  After receiving an instruction to read the configuration information 108 from the CPU 901, the data processing apparatus 100 reads the configuration information 108, determines a circuit block selected by the configuration information 108, and performs power source switching by the power control unit 103. Thereafter, the data processing apparatus 100 transmits the configuration information 108 to the circuit block 102 to set the operation of the arithmetic element and the router.

  After the above operation is completed, the data processing apparatus 100 starts arithmetic processing. When the operation process being executed is completed, the configuration information used in the next process is read from the external memory 905, and the same operation is repeated to execute the next operation process. In this way, the data processing apparatus 100 reads the configuration information in order, assigns arithmetic processing to the circuit block 102 along the configuration information 108, and executes the arithmetic processing.

  FIG. 20 is a diagram for explaining the process of changing the processing state in the data processing apparatus. Here, a case where the data processing apparatus 100 includes four circuit blocks is illustrated.

  In the processing state 2000a, after the data processing apparatus 100 is activated, the arithmetic processing assignment unit 105 acquires the first configuration information 1001 from the external memory 905, and determines the circuit block selected by the first configuration information 1001. The state until is shown.

  The circuit blocks 2001 to 2004 are in a state where the power is shut off (power off). The external memory 905 stores first configuration information 1001 and second configuration information 1002. The data processing apparatus 100 reads the first configuration information 1001 and the second configuration information 1002 in order, and switches the configuration of the dynamic reconfiguration circuit 106.

  First, the arithmetic processing allocation unit 105 acquires first configuration information 1001 from the external memory 905. Next, the arithmetic processing assigning unit 105 determines a circuit block selected by the first configuration information 1001. Here, the arithmetic processing assignment unit 105 determines that the circuit blocks selected by the first configuration information 1001 are the circuit blocks 2001 and 2002.

  In the processing state 2000b, after the arithmetic processing assignment unit 105 determines a circuit block, power is supplied to the circuit blocks 2001 and 2002, and arithmetic processing is assigned to the circuit blocks 2001 and 2002 based on the first configuration information 1001. Indicates the state.

  The arithmetic processing assignment unit 105 transmits information on the circuit blocks 2001 and 2002 to the power supply control unit 103. After receiving the information on the circuit blocks 2001 and 2002 from the arithmetic processing assigning unit 105, the power control unit 103 switches the power switch 107 connected to the circuit blocks 2001 and 2002 from off to on.

  Thereafter, the power control unit 103 notifies the arithmetic processing allocation unit 105 that the switching of the power switch 107 has been completed. Next, the arithmetic processing assignment unit 105 transmits the first configuration information 1001 to the circuit blocks 2001 and 2002.

  After receiving the first configuration information 1001, the arithmetic element 101 performs input switching of the data input unit 304, output switching of the data output unit 305, and processing setting of the arithmetic processing unit 303. After receiving the first configuration information 1001, the router 104 performs input / output setting of the input / output switching unit 403. In this way, the operation elements and router operations are sequentially set.

  The arithmetic processing assigning unit 105 receives again the first configuration information 1001 that has made a round in the circuit block, and detects that the transmission of the first configuration information 1001 has been completed. After the transmission of the first configuration information 1001 is completed, the arithmetic processing assignment unit 105 transmits a signal instructing each arithmetic element to start arithmetic processing. Thereafter, the computation element 101 starts computation processing. When the calculation process is completed, the calculation element 101 notifies the calculation process allocation unit 105 of the completion of the process.

  The processing state 2000c indicates a state after the data processing apparatus 100 completes the first data processing until the arithmetic processing is assigned to the circuit block along the second configuration information 1002.

  The arithmetic processing assignment unit 105 receives the processing completion notification from the arithmetic element 101, determines that the processing completion notification has been transmitted from all the arithmetic elements 101 to which the arithmetic processing is assigned, and performs first data processing. Detect that is complete. Thereafter, the arithmetic processing allocation unit 105 acquires the second configuration information 1002 from the external memory 905.

  Thereafter, according to the content of the second configuration information 1002, discrimination of circuit blocks and power supply switching are executed. Three circuit blocks 2001, 2002, and 2003 are selected in the second configuration information 1002, and the circuit block 2003 requires power supply switching. Therefore, the power control unit 103 switches the power switch 107 connected to the circuit block 2003 from off to on. Thereafter, calculation processing based on the second configuration information 1002 is assigned in the same manner as the calculation processing allocation based on the first configuration information 1002 described above.

  By repeating the above-described operation, the data processing apparatus 100 sequentially reads a plurality of pieces of configuration information 108 held in the external memory 905, and sequentially executes arithmetic processing based on the plurality of pieces of configuration information 108.

<Operation Example of CPU of Configuration Information Generation Device>
FIG. 21 is a diagram for explaining the process of selecting and changing circuit blocks selected by the configuration information. Specifically, the selection state 2101 indicates a circuit block selected by the first configuration information. Similarly, the selection state 2102 is a circuit block selected by the second configuration information, the selection state 2103 is a circuit block selected by the third configuration information, and the selection state 2104 is selected by the fourth configuration information. A circuit block is shown.

  When circuit blocks as shown in the selection states 2101 to 2104 are selected in the originally generated four pieces of configuration information, for example, the configuration information is modified so that it is selected as in the selection state 2100c. It ’s fine. That is, the circuit block selected by the second configuration information may be corrected as in the selection state 2401, and the circuit block selected by the third configuration information may be corrected as in the selection state 2501. By performing such correction, the number of times of switching the power supply of the circuit block associated with the transition of the configuration information is reduced.

  Below, the example which produces | generates the structure information used as the selection state 2100c from the structure information used as the selection state 2100a is demonstrated along the processing flow of FIG. The circuit block ID is set as shown in FIG.

  In step S1302, the circuit block selected by the first to third configuration information is determined, and the number of circuit blocks selected in each configuration information is calculated. Here, “6” circuit blocks are selected by the first configuration information, “9” circuit blocks are selected by the second configuration information, and circuit blocks are selected by the third configuration information. Is calculated as “12”.

  In step S1303, the number of times of switching the power source when switching the first to third configuration information is calculated. First, a circuit block selection list is generated along the processing of steps S1401 to S1407 in FIG.

  FIG. 22 is a diagram exemplarily showing a generated circuit block selection list. Next, the number of power supply switching is calculated from the circuit block selection list according to the equation (1). For the selection state 2100a, the number of times of power supply switching is “11”.

  In step S1304, when the first to third configuration information is switched, the number of times of switching the power supply that is minimized is calculated. The number of circuit blocks calculated in the process of step S1302 matches the condition number “1” among the determination conditions in FIG. Therefore, the minimum number of times of switching is obtained by subtracting the number of circuit blocks selected by the first configuration information from the number of circuit blocks selected by the third configuration information, and subtracting “6” which is the minimum number of times of power switching. obtain.

  In step S1305, the number of times calculated in step S1303 is compared with the number of times calculated in step S1304, and it is determined that the actual number is not the minimum. Accordingly, the process proceeds to step S1306. In step S1306, the priority of the circuit block used in the second configuration information is set. A priority list is generated according to the processing of FIG. FIG. 23 is a diagram exemplarily showing a priority list to be generated.

  In step S1307, a circuit block to be used in the second configuration information is set. At this time, referring to the priority setting in the priority list in FIG. 23, circuit blocks are selected in order from the circuit block with the highest priority. As a result of executing the processing of step S1307, the circuit block setting of the second configuration information becomes like the selection state 2401 in the selection state 2100b.

  In step S1308, one variable K is added. Here, K becomes “2”. In step S1309, it is determined whether K is equal to or greater than the number obtained by subtracting 1 from the number of pieces of configuration information input. Since K is “2” and the number obtained by subtracting 1 from the number “4” of the input configuration information is “3”, the determination is No. Therefore, the process of step S1302 is executed again.

  In step S1302, the circuit block selected by the second to fourth configuration information is determined, and the number of circuit blocks is calculated. The number of circuit blocks selected by the second configuration information is “6”, the number of circuit blocks selected by the third configuration information is “12”, and the number of circuit blocks selected by the fourth configuration information is “3”.

  In step S1303, the number of times of switching the power source when switching the second to fourth configuration information is calculated. For the selection state 2100b, the number of times of power supply switching is “6”.

  In step S1304, when the second to fourth configuration information is switched, the number of times of switching the power supply that is minimized is calculated. The number of circuit blocks calculated in the process of step S1302 matches the condition number “3” among the determination conditions in FIG. Therefore, the minimum number of times of switching is obtained by subtracting the number of circuit blocks selected by the second configuration information from the number of circuit blocks selected by the third configuration information, and subtracting “3”, which is the minimum number of times of power switching. obtain.

  In step S1305, the number of times calculated in step S1303 is compared with the number of times calculated in step S1304, and it is determined that the actual number is not the minimum.

  Thereafter, by executing the processing of step S1306 and step S1307, the circuit block setting of the third configuration information becomes like the selection state 2501 in the selection state 2100c.

  24 and 25 are diagrams exemplarily showing changes in data flow in the circuit block. The circuit block 102 is set with an ID similar to the ID described with reference to FIG.

  When the selection state 2102 is changed to the selection state 2401, the data flow shown in the upper part of FIG. 24 is changed to the data flow shown in the lower part of FIG. In this case, FIG. 24 shows that it is only necessary to shift the data flow setting to the left. Therefore, in this case, it is not necessary to change the input / output settings of the computation element 101 and the router 104, and only the IDs of the computation element 101 and the router 104 need be changed.

  On the other hand, when the selection state 2103 is changed to the selection state 2501, the data flow shown in the upper part of FIG. 25 is changed to the data flow shown in the lower part of FIG. In this case, the IDs of the calculation element 101 and the router 104 and the input / output settings of the calculation element 101 and the router 104 are changed.

  Note that a mechanism for reconstructing the data flow may be provided inside the configuration information generation unit 2701 in order to be able to cope with more complicated data flow changes. For example, after setting a circuit block to be used in the configuration information, a method of searching a data transfer route between the computing element 101 and the router 104 to reconstruct the data flow can be taken.

  In this way, the second and third configuration information out of the first to fourth configuration information is generated (regenerated) with the configuration information modified to change the circuit block to be selected. As a result, configuration information that reduces the number of times of power supply switching can be obtained.

  As described above, according to the first embodiment, it is possible to generate (regenerate) configuration information that reduces the number of times of switching power sources for circuit blocks. That is, it is possible to generate configuration information that can reduce charge power. For this reason, the data processing apparatus 100 assigns the arithmetic processing to the circuit block 102 based on the regenerated configuration information, so that it is possible to appropriately reduce power.

(Modification)
In the above description, the configuration information is read from the memory 905 outside the data processing apparatus 100. However, the configuration information may be held inside the data processing apparatus 100.

  FIG. 26 is a diagram illustrating an overall configuration of a data processing device according to a modification. Specifically, a configuration information holding unit 2601 is provided inside the data processing apparatus 100, and the configuration information is stored inside the configuration information holding unit 2601. In this configuration, the arithmetic processing assignment unit 105 reads the configuration information 108 held in the configuration information holding unit 2601 and transmits the configuration information to the dynamic reconfiguration circuit 106.

(Second Embodiment)
In the second embodiment, an example in which the configuration information 108 is generated inside the data processing apparatus 100 will be described.

<Description of configuration>
[Internal configuration of arithmetic processing assignment unit]
FIG. 27 is a diagram illustrating an internal configuration of the arithmetic processing assignment unit 105 according to the second embodiment. That is, here, the configuration information generation unit 2701 is added inside the arithmetic processing allocation unit 105, and the configuration information 108 is generated inside the arithmetic processing allocation unit 105. Note that the configuration information generation unit 2701 is a functional unit that implements processing similar to the processing illustrated in FIG.

  The configuration information generation unit 2701 receives information on the circuit block selected by the configuration information 108 from the circuit block determination unit 704, and sends a transmission instruction for the configuration information 108 to the configuration information transmission unit 702 via the signal line 2704. . In addition, the configuration information generation unit 2701 sends the regenerated configuration information 108 to the configuration information transmission unit 702 via the signal line 2703. Further, the configuration information generation unit 2701 outputs circuit block information via the signal line 114.

[Internal configuration of configuration information generator]
FIG. 28 is a diagram illustrating an internal configuration of the configuration information generation unit 2701. The configuration information generation unit 2701 includes a power supply switching number calculation unit 2801, a circuit block number calculation unit 2803, a circuit block priority setting unit 2804, and a circuit block setting unit 2805. In addition, the configuration information generation unit 2701 includes an ID / setting value change unit 2806, a switching frequency determination unit 2802, and a circuit block information transmission unit 2815.

  The power switching number calculation unit 1901 receives information on the circuit block selected by the configuration information 108. Then, the number of times of power supply switching necessary for assigning arithmetic processing along the configuration information 108 is calculated, and the calculation result is transmitted to the switching number determination unit 1902. The circuit block number calculation unit 2803 receives information on the circuit block selected by the configuration information 108. Then, the number of circuit blocks selected by each configuration information 108 is transmitted to the switching number determination unit 2802 and the circuit block priority setting unit 2804. The circuit block priority setting unit 2804 sets the priority of the circuit block according to the same processing as in step S1306 described above, and transmits priority setting information to the circuit block setting unit 1905.

  The circuit block setting unit 2805 selects a circuit block according to the same processing as in step S1307 described above, and transmits circuit block selection information to the ID / setting value changing unit 2806 and the circuit block information transmitting unit 2815. The ID / set value changing unit 2806 changes the ID according to the circuit block selection information received from the circuit block setting unit 2805 and regenerates the configuration information.

  The circuit block information transmission unit 2815 receives an instruction from the switching number determination unit 2802 via the signal line 2813, and either the circuit block information transmitted from the signal line 2812 or the circuit block information transmitted from the signal line 2814 Is output. The switching number determination unit 2802 receives information on the number of switchings from the power supply switching number calculation unit 2801 and information on the number of circuit blocks from the circuit block number calculation unit 2803, respectively. In addition, the switching number determination unit 2802 transmits a configuration information transmission instruction to the configuration information transmission unit 702 via the signal line 2704.

  The switching number determination unit 2802 instructs the circuit block information transmission unit 2815 via the signal line 2713 to output the circuit block information transmitted from the signal line 2812 or the circuit block information transmitted from the signal line 2814. To do. Further, the switching number determination unit 2802 controls the circuit block priority setting unit 2804 to set the priority via the signal line 2816.

[Internal configuration of power switch count calculation unit]
FIG. 29 is a diagram illustrating an internal configuration of the power supply switching frequency calculation unit 2801. The power switching number calculation unit 2801 includes a path switching unit 2901, registers 2902, 2903, 2904, 2907, 2908, 2-input ANDs 2905, 2906, and an adder 2909.

  The path switching unit 2901 receives circuit block information from the signal line 2702 and transmits a logical value “1” or “0” to the registers 2902, 2903, and 2904.

[Description of configuration of circuit block priority setting unit]
FIG. 30 is a diagram illustrating an internal configuration of the circuit block priority setting unit 2804. The circuit block priority setting unit 2804 includes a register selection unit 3003, registers 3001 and 3002, and a priority setting unit 3008.

  After receiving the circuit block information selected by the first configuration information from the signal line 2702, the register selection unit 3003 transmits the circuit block information to the register 3001. In addition, the register selection unit 3003 transmits circuit block information to the register 3002 after receiving the circuit block information selected by the third configuration information from the signal line 2702.

  The set value of the registers 3004 and 3006 is “1” when the first circuit block is selected, and the registers 3005 and 3007 are “1” when the second circuit block information is transmitted. That is, the setting value of the Nth bit of the registers 3001 and 3002 indicates whether or not the Nth circuit block is selected by the configuration information.

  Next, the priority is set as shown in FIG. 30B from the values of the corresponding bits in the registers 3001 and 3002. After setting the priority, the setting of the priority of each circuit block is output to the signal line 2810.

<Description of operation>
Below, operation | movement of the power supply switching frequency calculation part and the switching frequency determination part is demonstrated among the internal blocks of the structure information generation part 2701. FIG. The operation of other blocks of the configuration information generation unit 2701 is the same as the operation described with reference to FIG.

[Explanation of operation of power switching count calculation unit]
FIG. 29 is a diagram illustrating the operation of the power supply switching frequency calculation unit. First, first, second, and third circuit block selection information is stored in registers 2902, 2903, and 2904, respectively.

  The 2-input AND 2905 logically inverts the value of the Nth bit of the register 2902, calculates a logical product with the logical value of the Nth bit of the register 2903, and stores the calculated value in the register 2907. Similarly, the 2-input AND 2906 logically inverts the value of the Nth bit of the register 2903, calculates a logical product with the logical value of the Nth bit of the register 2904, and stores the calculated value in the register 2908.

  For example, since the logical value of the first bit of the register 2902 is “0” and the logical value of the first bit of the register 2903 is “1”, the logical value “1” is set to the first bit of the register 2907. "Is set. When the logical value “1” is set in the register 2907, it indicates that the circuit block is switched from power-off to on when switching from the first configuration information to the second configuration information.

  By performing similar processing for each block, it is possible to determine whether the power of each circuit block is switched from OFF to ON from the first processing to the second processing.

  Further, in order to detect the number of times of power supply switching when switching from the second configuration information to the third configuration information is performed, the logic value of the Nth bit of the register 2903 and the logic value of the Nth bit of the register 2904 are detected. A similar logical operation is performed using the value. The calculated logical operation result is stored in the registers 2907 and 2908. When logical values are stored in all the registers, the adder 2909 adds the values of the registers. Thereby, the number of power supply switching is calculated based on the number of logical values “1”. The number of power supply switching times calculated by the above operation is output via the signal line 2807.

[Explanation of operation of switching frequency judgment unit]
After receiving the information on the number of circuit blocks from the circuit block number calculation unit 2803, the switching number determination unit 2802 calculates the minimum value of the number of times of power supply switching by the determination unit shown in FIG. Thereafter, information on the number of times of switching is received from the power source switching number calculation unit 2801, and it is determined whether the number of times of switching the power source is the minimum.

  When the number of power source switching is not the minimum, the switching number determination unit 2802 gives an instruction to set the priority to the circuit block priority setting unit 2804 via the signal line 2816.

  Note that when the number of times of power supply switching is minimum, the configuration information is not regenerated, and the switching number determination unit 2802 instructs the configuration information transmission unit 702 to transmit the existing configuration information 108 via the signal line 2704. send. In addition, the switching number determination unit 2802 instructs the circuit block information transmission unit 2815 to output the circuit block information received from the signal line 2812 to the signal line 114.

  As described above, according to the second embodiment, configuration information is regenerated by the configuration information generation unit 2701 provided in the data processing apparatus 100. With this configuration, it is possible to generate (regenerate) configuration information that reduces the number of times of switching power sources for circuit blocks, as in the first embodiment. In particular, configuration information that reduces the number of times of power supply switching can be generated almost in real time.

(Other examples)
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

Claims (2)

A configuration information generating device that generates configuration information used in an array type arithmetic device each having a plurality of circuit blocks each including one or more arithmetic elements and configured to be individually power-controllable. Including information defining which one or more circuit blocks of the plurality of circuit blocks are to be used,
Obtaining means for obtaining N pieces (N is an integer of 3 or more) of configuration information used continuously in the array type arithmetic unit;
When the configuration information used by the array type arithmetic unit is changed in order from the first configuration information to the Nth configuration information, the number of circuit blocks that are changed from the power-off state to the power-on state is reduced. Correcting means for correcting the (K + 1) th configuration information based on the Kth (K is an integer satisfying 1 ≦ K ≦ N−2) configuration information and the K + 2nd configuration information;
A configuration information generating apparatus comprising: A control method for a configuration information generating device that generates configuration information used in an array type arithmetic device each including a plurality of circuit blocks each including one or more arithmetic elements and configured to be individually power-controllable. The information includes information defining which one or more circuit blocks of the plurality of circuit blocks are used, and the control method includes:
An acquisition step of acquiring N pieces of configuration information (N is an integer of 3 or more) used continuously in the array type arithmetic unit;
When the configuration information used by the array type arithmetic unit is changed in order from the first configuration information to the Nth configuration information, the number of circuit blocks that are changed from the power-off state to the power-on state is reduced. A correction step of correcting the (K + 1) th configuration information based on the Kth configuration information (K is an integer satisfying 1 ≦ K ≦ N−2) and the K + 2nd configuration information;
A method for controlling a configuration information generating apparatus, comprising:

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