JP6089840B2 - Synchronization control device, synchronization control method, and synchronization control program - Google Patents

Description

  The present invention relates to a synchronization control device, a synchronization control method, and a synchronization control program for controlling synchronization between a plurality of graphic cards.

  By arranging a plurality of display devices side by side to create a large screen and displaying the video of each part divided by each display device, it is possible to display one video on a large screen in which a plurality of display devices are arranged. Has been done. This is realized, for example, by attaching a plurality of graphic cards to a computer that performs video display processing and connecting a plurality of display devices.

  A technique for embedding a synchronization signal in a serial interface for video data connected to a plurality of display panels is known. In addition, a technique of a multi-display device is known in which adjacent displays are connected by an interface provided with interfaces in four surrounding directions, and data can be transferred between the displays. In addition, a technique for performing overlap processing on joints of multi-screens is known.

JP 2004-145353 A JP 2003-280624 A JP-A-10-83170

  When a plurality of display devices are arranged and operated as one screen as described above, it is necessary to synchronize the image display between the display devices.

  For example, in recent years, contents to be displayed in 3D in TV programs, movies, games, and the like have increased, and along with this, household televisions and PCs (Personal computers) having a 3D display function have been spreading. There are several technologies for realizing 3D display. Basically, images for the right eye and left eye are displayed on one screen, and the user can wear the right eye to the right eye through his / her glasses. Only the image for the left eye is visible, and only the image for the left eye is visible to the left eye. The right-eye image and the left-eye image are given parallax, and each image can be viewed stereoscopically by looking at each image.

  Among technologies for realizing such 3D display, there is a technique in which a shutter function is provided on glasses worn by a user. In this technique, when the right-eye image is displayed on the television, the right-eye shutter of the glasses is opened and the left-eye shutter is closed, and when the left-eye image is displayed on the television, the left-eye of the glasses is displayed. The shutter is opened and the right-eye shutter is closed. For example, the image for the right eye and the image for the left eye are switched and displayed every 1/60 seconds, and the corresponding side shutter is opened accordingly, thereby realizing stereoscopic viewing of the image. If there is a difference between the switching of the image and the opening / closing timing of the shutter of the glasses, the user cannot view stereoscopically.

  When 3D display is performed on a screen in which a plurality of display devices are arranged, if there is a deviation in image display between the arranged display devices, a display image of a certain display device can be stereoscopically viewed, but another display device There is a possibility that the display image may not be stereoscopically viewed. Therefore, a technique for synchronizing the image display by a plurality of display devices with higher accuracy is desired.

  In one aspect, an object of the present invention is to provide a technique for controlling synchronization of image display between a plurality of graphic cards.

In one aspect, the synchronization control device includes a synchronization timing monitoring unit that monitors a synchronization timing of image output by the own graphic card among a plurality of graphic cards each mounted on a host computer bus via a bridge circuit ; A synchronization packet generator for generating a packet of a bus transaction for a specific memory space in which multicast is set, and a synchronization packet issuing unit for issuing the packet to the host computer bus when timing is detected; Is provided.

  According to the aspect of the present invention, it is possible to synchronize image display between a plurality of graphic cards.

It is a figure which shows the structural example of the display system by this Embodiment. It is a figure explaining the mechanism of PCH by this Embodiment. It is a figure which shows the function structural example of the graphic card by this Embodiment. It is a figure explaining the setting of the multicast space by this Embodiment. It is a figure which shows the example of the synchronous packet by this Embodiment. It is a figure explaining issue of the synchronous packet by this Embodiment. It is a figure explaining the synchronous control by this Embodiment. It is a synchronous control process flowchart by the master synchronous control part of the graphic card of the master of this Embodiment. It is a synchronous control processing flowchart by the slave synchronous control part of the graphic card of the slave of this Embodiment. It is a figure which shows the example of the priority definition of the virtual channel of PCIe by this Embodiment. It is a figure explaining the example of the synchronous packet transfer by the fixed priority of this Embodiment. It is a figure explaining the example of the mechanism of the time-based QoS of PCIe by this Embodiment. It is a figure explaining the example of the synchronous packet transfer by the arbitration table and equal priority of this Embodiment.

  Hereinafter, the present embodiment will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration example of a display system according to the present embodiment.

  The display system according to the present embodiment shown in FIG. 1 is a computer system that displays a 3D image on a screen formed by arranging a plurality of display devices, for example. In the display system shown in FIG. 1, the host 10 is a computer such as a tower-type PC that performs image display processing. The host 10 includes a CPU (Central Processing Unit) 11, a memory 12, a PCH (Platform Controller Hub) 13, and slots 14 (a to d).

  The CPU 11 is a central processing unit and plays a central role in system control. The CPU 11 includes a memory controller and is connected to a memory 12 that is a storage device. The PCH 13 is a chip in which the functions of the north bridge and the south bridge are integrated. The PCH 13 has an interface between the CPU 11 and peripheral devices such as a hard disk and a keyboard. The PCH 13 includes a PCIe (Peripheral Component Interconnect Express) interface as an option card interface. In the example illustrated in FIG. 1, the PCH 13 includes a 4-port PCIe interface. The slot 14 is called, for example, an option slot or an expansion slot, and an option card is mounted.

  The graphic card 20 is a kind of option card and has a function of inputting and outputting video as a signal. The graphic card 20 is also called a video card or a graphic board. An option card is also called an expansion card or an expansion board, and is a card that expands the functions of a computer. In the example shown in FIG. 1, it is assumed that the graphic card 20 is a card that inputs and outputs 3D video. The graphic card 20 has its own control unit and memory, and can execute programs such as firmware.

  LCD (Liquid Crystal Display) panels 30 (a to d) are display devices. As shown in FIG. 1, each LCD panel 30 (ad) is connected to a graphic card 20 (ad), respectively. In the display system shown in FIG. 1, the image to be displayed is divided into four images by the host 10, and each image is output to the LCD panel 30 (ad) through the graphic card 20 (ad).

  In general, the graphic card 20 has an independent clock, and thereby operates at an independent timing. Therefore, it is necessary to perform synchronous control of output to the LCD panel 30 between the graphic cards 20. If the synchronization control is not performed, there is a possibility that the output to the LCD panel 30 is shifted between the graphic cards 20, and accurate 3D display cannot be performed.

  FIG. 2 is a diagram for explaining the mechanism of PCH according to the present embodiment.

  In the PCH 13, the bus 130 is a general-purpose bus that connects the CPU 11 and a device (peripheral device) such as a PCIe bus. In the example of the present embodiment, each graphic card 20 mounted in each slot 14 is connected from the bus 130 through PCI to PCIe bus conversion.

  In the PCH 13, each PCIe interface includes a PCIe bridge 131 (a to e), and is bridged from the PCI bus 130 as a backbone by the PCIe bridge 131. The PCIe bridge 131 is a bridge of a PCI bridge image. Each PCIe slot 14 requires a PCIe bridge 131, in part, to determine the address of the PCIe device. The presence of the PCIe bridge 131 serves as a receiver for address setting from the host 10 side, and addresses can be set for the devices installed in the slots 14. Is possible.

  Since the PCIe bridge 131 exists between the individual devices, each device exists in a dedicated bus segment. Each device receives resource allocation of dedicated memory space and I / O (Input / Output) space from the OS (Operating System), and the bus transaction into the space is basically unicast style. . Therefore, normally, a bus transaction issued to one target device is not received by another device.

  The bus transaction is a series of processing such as reading and writing performed via the bus 130.

  PCIe also has a multicast function. In the present embodiment, notification of synchronization timing of image display is performed using a multicast bus transaction. More specifically, any one of the master graphic cards 20 performs a multicast of a bus transaction with respect to a specific memory space at a periodic image display synchronization timing, so that the synchronization timing of other graphic cards 20 can be adjusted. Make a notification. The graphic card 20 that has received the notification of the synchronization timing uses the notification as a display frame start trigger and outputs an image to the LCD panel 30.

  One of the plurality of graphic cards 20 mounted on the host 10 becomes the master graphic card 20. Further, the graphic cards 20 other than the master graphic card 20 become slave graphic cards 20. In this embodiment, the master graphic card 20 notifies the slave graphic card 20 of the synchronization timing.

  The master graphic card 20 may be determined before being inserted into the slot 14 of the host 10, or may be any graphic card by a device driver or the like after being inserted into the slot 14 by a function such as plug and play. 20 may be automatically set as the master. Further, any graphic card 20 installed in the slot 14 may be set as a master automatically or by a user's selection by an application that performs moving image processing that operates on the host 10.

  In the example of the present embodiment, as shown in FIG. 2, the graphic card 20a operates as a master, and the other graphic cards b to d operate as slaves. That is, the master graphic card 20a notifies each slave graphic card 20b-d of the synchronization timing using the PCI bus 130 in accordance with the synchronization timing of image output to its own LCD panel 30a. The slave graphic cards 20b to 20d output images to the LCD panels 30b to 30d in synchronization with the synchronization timing notification received from the master graphic card 20a.

  FIG. 3 is a diagram illustrating a functional configuration example of the graphic card according to the present embodiment.

  FIG. 3A shows a functional configuration example of the master graphic card 20a. The master graphic card 20 a includes a master synchronization control unit 210. The master synchronization control unit 210 includes a multicast setting unit 211, a synchronization timing monitoring unit 212, a synchronization packet generation unit 213, and a synchronization packet issue unit 214.

  The multicast setting unit 211 sets a specific memory space as a target of a multicast bus transaction. The bus transaction packet for the specific memory space set here is a packet for notifying the synchronization timing from the master graphic card 20a to the slave graphic cards 20b to 20d. Hereinafter, a packet for notifying the synchronization timing from the master graphic card 20a to the slave graphic cards 20b to 20d is referred to as a synchronization packet. A specific memory space set as a target of a multicast bus transaction is also called a multicast space.

  The synchronization timing monitoring unit 212 monitors the synchronization timing of image output by the own graphic card 20. For example, the synchronization timing monitoring unit 212 monitors a synchronization signal (for example, a vertical synchronization signal) of the image display of the own graphic card 20a itself, and determines that the synchronization timing has been detected when the synchronization signal is detected. . Note that the master graphic card 20a outputs an image to the LCD panel 30a in accordance with a synchronization signal for its own image display.

  When the synchronization timing is detected by the synchronization timing monitoring unit 212, the synchronization packet generation unit 213 generates a bus transaction packet for a specific memory space in which multicast is set, that is, the multicast space. The packet generated by the synchronization packet generation unit 213 becomes a synchronization packet.

  The synchronization packet issuing unit 214 issues the synchronization packet generated by the synchronization packet generating unit 213 to the bus 130 of the host 10 in which the own graphic card 20a is mounted. The issued synchronization packet is sent to the graphic cards 20b to 20d of each slave by the multicast function of PCIe. Note that isochronous transfer priority control may be specified for the issued synchronization packet.

  FIG. 3B shows a functional configuration example of the slave graphic card 20b. The other slave graphic cards 20c and 20d have the same configuration. The slave graphic card 20 b includes a slave synchronization control unit 220. The slave synchronization control unit 220 is a synchronization control unit on the graphic card 20b side serving as a slave in the synchronization control of the image output between the graphic cards 20 according to the present embodiment. The slave synchronization control unit 220 includes a multicast spatial information holding unit 221, a synchronization packet monitoring unit 222, and a synchronization signal generation unit 223.

  The multicast space information holding unit 221 stores information on a specific memory space in which multicast is set, that is, information on the multicast space.

  The synchronization packet monitoring unit 222 monitors reception of a synchronization packet issued by the master graphic card 20a. For example, the synchronous packet monitoring unit 222 stores a target address space of a packet of a bus transaction received by the graphic card 20b in a multicast space information holding unit 221, and is a specific memory space in which multicast is set, that is, a multicast space. If it is, it is determined that a synchronization packet has been received.

  The synchronization signal generation unit 223 generates a synchronization signal for image display of the own graphic card 20b when the synchronization packet monitoring unit 222 confirms reception of the synchronization packet. The slave graphic card 20b outputs an image to the LCD panel 30b in accordance with the synchronization signal generated by the synchronization signal generator 223.

  The master synchronization control unit 210 and the slave synchronization control unit 220 are realized by, for example, firmware that is operated by the control unit of the graphic card 20, respectively. The master synchronization control unit 210 and the slave synchronization control unit 220 may be realized by a dedicated hardware circuit.

  FIG. 4 is a diagram for explaining the setting of the multicast space according to the present embodiment.

  The memory space shown in FIG. 4 is a memory space in the host 10. A multicast space is set in the memory space of the host 10. In the memory space shown in FIG. 4, each group # 0 to # 3 is a block of 4K bytes. In the present embodiment, it is assumed that a space of up to four continuous 4 Kbyte blocks can be defined as a multicast space.

  For example, the multicast setting unit 211 of the master synchronization control unit 210 in the master graphic card 20a issues a request for setting a multicast space including the number of blocks desired as the multicast space to the configuration software operating on the host 10. . Upon receiving the request, the configuration software sets up the multicast space of the desired number of blocks, and information such as the base address of the multicast space, the number of blocks, etc. for each PCIe bridge 131 and each graphic card 20 by various drivers. Set.

  FIG. 5 is a diagram illustrating an example of a synchronization packet according to the present embodiment.

  The synchronization packet shown in the example of FIG. 5 is a PCIe memory-related transaction request packet. This bit definition is shown here. When the synchronization packet is issued from the master graphic card 20a, the bits defined in the synchronization packet are in the order of + 0 → + 1 →..., DW (Double Word) # 0 → DW # 1 →. Are converted into serial data in this order and sent to the PCIe link.

  The synchronization packet shown in FIG. 5 is a 32-bit CPU packet, which is a 3DW header type from Attribute to Address. Attribute is a part that defines the nature of the packet, for example, whether the request is a read or a write. The Length portion indicates the number of DWs of the synchronization packet data (Payload portion). BE is a byte enable, and indicates a valid byte at the time of writing the first DW and the last DW in the DW specified by Length. ReqID is used for routing in the requester direction when a completion packet is returned to the target request, and is a request agent ID corresponding to the address information of the request packet. Address is a part for designating a memory address that is a target of a read or write request.

  Payload is data of the number of DWs specified by Length that accompanies the synchronization packet, and write data is specified here in the write request. Payload is a variable length part that can be up to 1024 DW (4096 bytes) in length according to the specification of Length. In the example shown in FIG. 5, a minimum 1 DW Payload suitable for using a read request for a synchronous packet is shown.

  Since 0 indicates 1024 DW for the Length value, a request for 0 DW data cannot be issued. However, PCIe has a special read request called zero-length read. In this request, Length = 1 and BE are designated as all 0s. When this specification is made, 1DW meaningless data is returned from the target.

  In the synchronization packet, a specific memory space, that is, a multicast space is designated in the Address portion, thereby indicating that it is a synchronization packet. The multicast space is a memory space on the host 10 side that does not belong to any graphic card 20, and the target of the synchronization packet is the main memory space of the CPU 11. If this space is simply for a zero-length read request for a synchronization packet, the actual memory may or may not be implemented.

  FIG. 6 is a diagram for explaining issuance of a synchronization packet according to the present embodiment.

  When the master graphic card 20a detects the synchronization timing of its own image display, it issues a bus transaction synchronization packet to the multicast space. Here, the synchronization packet is assumed to be a read request packet for any group #X (X = 0 to 3) in the multicast space.

  Information about the multicast space is set in the PCIe bridge 131. The PCIe bridge 131 determines whether the packet is a multicast packet by confirming whether the target address space indicated in the received packet is a set multicast space. Since the synchronization packet issued from the master graphic card 20a is a packet of a bus transaction for the multicast space, it is sent to all the slave graphic cards 20b to 20d.

  Each slave graphic card 20b-d has already been notified of the multicast space targeted by the synchronization packet. When the target of the received packet is the corresponding multicast space, each graphic card 20b-d recognizes that the packet is a synchronization packet.

  FIG. 7 is a diagram for explaining the synchronization control according to the present embodiment.

  In FIG. 7, VSYNC (20a) indicates a synchronizing signal (here, a vertical synchronizing signal) in the master graphic card 20a. Similarly, VSYNC (20b), VSYNC (20c), and VSYNC (20d) indicate synchronization signals (here, vertical synchronization signals) in the slave graphic cards 20b to 20d, respectively. “R” indicates a synchronization packet using a read request.

  In the master graphic card 20, it is assumed that a synchronization signal is generated at a frame interval of 60 Hz, for example, and an image is output to the LCD panel 30a. In the master graphic card 20 a, the master synchronization control unit 210 generates a synchronization packet for the multicast space and issues it to the bus 130 when an image output synchronization signal is detected.

  Each slave graphic card 20b-d receives the synchronization packet issued from the master graphic card 20a. In each of the slave graphic cards 20b to 20d, the slave synchronization control unit 220 generates a synchronization signal in response to reception of the synchronization packet. Each slave graphic card 20b-d outputs an image to the corresponding LCD panel 30b-d in accordance with the generated synchronization signal.

  When a memory read request packet is used as a synchronization packet, a completion packet for returning read data from the memory is returned. However, the notification of the synchronization timing according to the present embodiment has no meaning.

  FIG. 8 is a flowchart of synchronization control processing by the master synchronization control unit of the master graphic card according to the present embodiment.

  In the master graphic card 20a, the synchronization timing monitoring unit 212 of the master synchronization control unit 210 determines whether a synchronization signal for image output from the own graphic card 20a to the LCD panel 30a has been detected (step S10). When the synchronization signal is detected (YES in step S10), the synchronization packet generation unit 213 generates a synchronization packet for a predetermined multicast space (step S11). The synchronization packet issuing unit 214 issues the generated synchronization packet to the bus 130 of the host 10 (step S12).

  FIG. 9 is a synchronization control processing flowchart by the slave synchronization control unit of the slave graphic card according to the present embodiment.

  In each slave graphic card 20b-d, the synchronization packet monitoring unit 222 of the slave synchronization control unit 220 determines whether or not a synchronization packet from the master graphic card 20a has been detected (step S20). More specifically, the synchronization packet monitoring unit 222 determines whether the target of the packet received by the graphic card 20 is the multicast space set as the target of the synchronization packet stored in the multicast space information holding unit 221. judge. When the target of the received packet is a multicast space set as the target of the synchronous packet, the synchronous packet monitoring unit 222 determines that the received packet is a synchronous packet. When the synchronization packet is detected (YES in step S20), the synchronization signal generation unit 223 generates a synchronization signal for image output to the LCD panels 30b to 30d by the own graphic cards 20b to 20d (step S21).

  In order to ensure the accuracy of notification of synchronization timing using a bus transaction according to the present embodiment, a QoS (Quality Of Service) function of PCIe may be used.

  The QoS function in PCIe indicates a function of a data transfer service for a device that requires a uniform capacity data transfer, which is generally called isochronous transfer, such as an audio sampling frequency and a video frame frequency. In PCIe, there are two QoS implementation methods, priority-based and timing-based.

  In priority-based QoS, isochronous transfer packets are differentiated from other packets and preferentially delivered. Priority-based QoS has long been used for packet switching services in telephone networks.

  In the timing-based QoS, the use of the bus is periodically scheduled in advance in a time zone for isochronous transfer and a time zone for other transfer (bulk transfer). For example, in a bus used in a PC or the like such as USB (Universal Serial Bus) or IEEE 1394, a fixed frame marker signal indicating the transfer cycle is output to the bus, and in a device or host that expects isochronous transfer, Data transfer is repeated at regular intervals and regular periods with reference to the marker signal.

  In PCIe, a virtual channel called a virtual channel is defined for one physical link, and the bus can be used as an independent pipe with differentiated transfer priorities. By using a high-priority virtual channel for the bus transaction for notifying the synchronization timing in this embodiment, it is distributed with priority over other bus transactions. This improves the accuracy of the synchronization frame interval notified to the slave graphic cards 20b to 20d.

  FIG. 10 is a diagram illustrating an example of priority definition of a PCIe virtual channel according to the present embodiment.

  In FIG. 10, VCx (x = 0 to 7) indicates a virtual channel. The maximum number of PCIe virtual channels is 8, and how many virtual channels the system supports depends on the chipset. The larger the value of x, the higher the priority of the virtual channel, and VC0 becomes the lowest priority virtual channel.

  As shown in FIG. 10, a plurality of virtual channels are divided into two groups, a group with a large value of x and a group with a small value of x. The group with a large value of x is a fixed priority group, and the value of x is small. The group can also be an equal priority group. In the fixed priority group, a fixed priority arbitration is performed in which a virtual channel having a large value of x is always given priority. In the equal priority group, the priority of the virtual channel picked up this time is set to the lowest priority in the next arbitration, and fair arbitration is performed regardless of the value of x. Any virtual channel can be set as the boundary between two groups.

  In the PCIe mechanism, the realization of QoS on a priority basis is assumed with fixed priority, and the realization of QoS on a timing basis is assumed with uniform priority. That is, even when there is a definite priority difference due to grouping between fixed priority and equal priority, QoS by the equal priority group is also realized.

  FIG. 11 is a diagram illustrating an example of synchronous packet transfer with a fixed priority according to the present embodiment.

  Here, an example in which two virtual channels of VC0 and VC1 are supported will be described. According to the PCIe fixed priority rule, of the two virtual channels, VC1 has a higher priority and VC0 has a lower priority. At this time, the transfer of the VC1 packet is prioritized, and the VC0 packet is transferred across the gap.

  In FIG. 11, “R” indicates the transfer of a synchronization packet. As shown in FIG. 11, if VC1 is designated for the synchronization packet, the synchronization packet is preferentially transferred at a predetermined synchronization interval, so that the accuracy of synchronization control between the graphic cards 20 is increased.

  FIG. 12 is a diagram for explaining an example of the mechanism of the time-based QoS of PCIe according to this embodiment.

  Here, an example in which two virtual channels of VC0 and VC1 are supported will be described. It is assumed that the boundary is set so that VC0 becomes an equal priority group and VC1 becomes a fixed priority group. In this example, isochronous transfer is performed by VC0 which is lower than VC1, and VC0 is specified in the synchronization packet issued from the master graphic card 20a. Isochronous transfer that must be given priority in terms of timing can be performed even in VC0 in a lower priority group than the fixed priority group because PCIe has a timing-based channel arbitration mechanism.

  As shown in FIG. 12, PCIe arbitration is performed in two stages of port arbitration and VC arbitration, and a packet to be output with the highest priority is finally determined. In FIG. 12, an ellipse in a broken line frame indicates port arbitration, and an ellipse in a solid line frame indicates VC arbitration.

  In the first-stage port arbitration, arbitration is performed to determine which port has priority for each virtual channel. As shown in FIG. 12, port arbitration is a cluster of VC arbitration. In the second-stage VC arbitration, when there are a plurality of virtual channels as a result of the port arbitration, arbitration is performed regarding which virtual channel is prioritized.

  To perform isochronous transfer in the equal priority group, scheduling to pick up packets in the port arbitration stage is divided into a time zone during which only a specific virtual channel is input and a time zone during which other virtual channels are exchanged. Do. This realizes isochronous transfer that preferentially handles a specific packet in a certain time zone.

  FIG. 13 is a diagram for explaining an example of synchronous packet transfer based on the arbitration table and the equal priority according to the present embodiment.

  Port arbitration is performed using an arbitration table. FIG. 13A shows an example of an arbitration table. When QoS is realized by uniform arbitration, a port to which a virtual channel is input is determined by performing time-based arbitration by scanning the arbitration table in a fixed time slot.

  The PCIe port arbitration method includes a mode in which a priority packet is selected for each packet input opportunity, in addition to the time-based method.

  In the arbitration table shown in FIG. 13A, a port number to be arbitrated is set for each virtual channel and for each time slot. In the example of the arbitration table shown in FIG. 13A, (0) shows port 0 in FIG. 12, (1) shows port 1 in FIG. 12, and (2) shows port 2 in FIG.

  An arrow in the example of the arbitration table shown in FIG. 13A means that the arbitration table scan is performed from left to right in order from the left end to the left end. For example, in the example of VC1 in the arbitration table of FIG. 13A, VC1 packets are taken in the order of port 0 → port 1 → port 2 → port 1 → port 0 (left end) →. It has been shown that

  In the arbitration table shown in FIG. 13, the designation of port 0 indicates an idle time slot in which no packet is input. In the arbitration example shown in FIG. 12, since the arbitration direction is port 0, port 0 is an empty port number that does not require packet pickup. By utilizing this fact, the arbitration table shown in FIG. 13 represents an idle time zone in which input is not accepted by specifying port 0.

  The ability to specify the port number in the time slot means that the port for inputting the virtual channel can be differentiated in terms of timing.

  For example, in the arbitration table shown in FIG. 13A, in the VC1 table, port 0 indicating idle is designated in the first time slot, and port 1 or port 2 is designated in the other time slots. In the VC0 table, port 1 is designated only for the first time slot, and port 0 indicating idle is designated for the other time slots. Therefore, the virtual channel picked up in the time slot of each time slot is as shown in FIG.

  From the arbitration table shown in FIG. 13A, it can be seen that only VC0 is picked up limitedly in the time slot of the first time slot at the left end. As shown in FIG. 13B, assuming that one time slot is 128 μs, the temporal advantage of VC0 is realized every 512 μs of four time slots. If port 1 is a port on the master graphic card 20 side in PCIe, priority control of isochronous transfer can be realized by designating VC0 as the virtual channel of the synchronization packet. In FIG. 13B, “R” indicates the issuance of a synchronization packet.

  As a result of arbitration using such a table, when a plurality of virtual channels are accepted in the same time slot, the simultaneously accepted virtual channels are sent to the next VC arbitration and the final packet is determined.

  VC arbitration is done either by automatic round robin without a table, or by using a table similar to a time-based table image, but the table here is not a regular scan table. , Scan table for each request opportunity. Regardless of which method is used, in the example shown in FIGS. 12 and 13, since there is only one virtual channel of the equal priority group VC0, the result of VC arbitration is VC0 as the output of the port arbitration. . The output of VC0 is the arbitration of fixed priority depending on the value of VCx and the output of VC1 of port arbitration which is a fixed priority group, and the final packet is selected and output.

  Note that the virtual channel number for performing priority control of isochronous transfer for the synchronization packet is set in the hardware of the graphic card 20 by, for example, configuration software operating on the host 10. Therefore, the virtual channel number set in the hardware is used every time the packet is issued without being conscious of ordinary software using the graphic card 20.

  In this way, for example, by using the QoS function in PCIe to perform priority control of isochronous transfer with respect to a synchronization packet, synchronization control between graphic cards 20 with high accuracy with suppressed variations in synchronization timing is possible.

  With the synchronization control technique according to the present embodiment described above, it is possible to synchronize image display by a plurality of graphic cards 20. In the synchronous control technique according to the present embodiment, since the synchronous control is performed using the general-purpose bus of the host 10, there is no need for a special signal line. In addition, it is not necessary to modify the existing bus transaction mechanism in order to realize the synchronization control technique according to this embodiment. Therefore, the synchronization control technique according to this embodiment can be realized at low cost.

  Although the present embodiment has been described above, the present invention can naturally be modified in various ways within the scope of the gist thereof.

  For example, in the example of the present embodiment, the example of the synchronization control of the graphic card that inputs and outputs 3D video has been described. However, the synchronization control of the graphic card that inputs and outputs 2D video also depends on the present embodiment. Application of synchronous control technology is possible.

  For example, in the example of the present embodiment, a read request packet is used as the synchronization packet, but a packet other than the read request may be used as the synchronization packet. For example, a write request packet may be used as the synchronization packet.

  Further, for example, in the example of the present embodiment, notification of synchronization timing is performed using a bus transaction in the PCIe interface, but another interface having a similar bus transaction function may be used.

10 Host 11 CPU
12 memory 13 PCH
130 Bus 131 PCIe Bridge 132 Port 14 Slot 20 Graphics Card 210 Master Synchronization Control Unit 211 Multicast Setting Unit 212 Synchronization Timing Monitoring Unit 213 Synchronization Packet Generation Unit 214 Synchronization Packet Issuing Unit 220 Slave Synchronization Control Unit 221 Multicast Spatial Information Holding Unit 222 Synchronization Packet Monitoring unit 223 Synchronization signal generating unit 30 LCD panel

Claims (5)

A synchronization timing monitoring unit for monitoring the synchronization timing of image output by the own graphic card among a plurality of graphic cards each mounted on a bus of a host computer via a bridge circuit ;
A synchronization packet generator for generating a bus transaction packet for a specific memory space in which multicast is set when synchronization timing is detected;
A synchronization control apparatus comprising: a synchronization packet issuing unit that issues the packet to a bus of the host computer. The synchronization control apparatus according to claim 1, further comprising a multicast setting unit configured to set the specific memory space as a target of a multicast bus transaction. The synchronous control apparatus according to claim 1 or 2, wherein priority control of isochronous transfer is specified for the packet. Any of a plurality of graphics cards that are each mounted via a bridge circuit to the bus of the host computer,
Monitor the synchronization timing of image output by your graphics card
When synchronization timing is detected, it generates a bus transaction packet for a specific memory space for which multicast is set,
Synchronous control method characterized by performing the process of issuing the packet, the bus of the host computer. To one of a plurality of graphics cards that are each mounted via a bridge circuit to the bus of the host computer,
Monitor the synchronization timing of image output by your graphics card
When synchronization timing is detected, it generates a bus transaction packet for a specific memory space for which multicast is set,
Synchronous control program for executing the process of issuing the packet, the bus of the host computer.

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