JP6090474B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including an electrode that is ohmic-connected to a semiconductor layer, and a method for manufacturing the semiconductor device.

  Currently, a semiconductor device using a nitride semiconductor is expected as a semiconductor device used for a high-frequency power amplifier or the like.

  In such a semiconductor device, it is necessary to form electrodes on the surface of the semiconductor layer. For example, when forming a field effect transistor, the gate electrode is formed so as to be Schottky connected to the semiconductor layer. On the other hand, the source electrode and the drain electrode are formed to be in ohmic contact with the semiconductor layer.

  The ohmic connection between the electrode and the semiconductor layer is preferably as low a resistance as possible. In particular, a lower resistance is desired in the above-described high-frequency power amplifier or the like.

  For example, in Patent Document 1, a metal layer, a diffusion prevention layer, and a conductive layer are sequentially formed on the surface of a semiconductor layer made of a nitride semiconductor, and these are subjected to heat treatment, so that the metal constituting the metal layer is contained in the semiconductor layer. A semiconductor device intruded into is disclosed. In the semiconductor device, the resistance of the ohmic connection can be reduced by allowing the metal constituting the metal layer to enter the semiconductor layer.

JP 2009-49391 A

  However, the conventional electrode structure described in Patent Document 1 has the following problems. FIG. 10 is an image obtained by photographing the surface of a conventional ohmic-connected electrode with an optical microscope. In FIG. 10, 30 indicates a semiconductor layer, and 50 indicates a protective layer.

In the conventional electrode structure, Au is used for the diffusion preventing layer and Al is used for the conductive layer. However, in this electrode structure, when heat treatment is performed at a high temperature, as shown in FIG. . This unevenness is caused by an alloy of Au and Al (AuAl ₂ ) formed by high-temperature heat treatment, so-called purple plague. Thereby, for example, the flatness of the electrode surface is deteriorated such that the end portion of the electrode surface protrudes in comparison with the central portion of the electrode surface. In particular, the inventors of the present application have found through experiments that the phenomenon becomes significant when the heat treatment temperature greatly exceeds 800 ° C.

  When the surface state is uneven, the ohmic connection resistance value itself does not change, but the connection resistance when another circuit is connected to the electrode surface increases. Therefore, the substantial resistance of the semiconductor element cannot be reduced.

  An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device in which the resistance value of the ohmic connection is kept low and the flatness of the electrode surface is improved.

  A semiconductor device of the present invention includes a semiconductor layer made of a nitride semiconductor and an electrode layer formed on the surface of the semiconductor layer. The electrode layer is an adhesion layer formed on the surface of the semiconductor layer, a diffusion auxiliary layer formed on the opposite side of the adhesion layer to the semiconductor layer, a dopant layer formed on the opposite side of the adhesion layer of the diffusion auxiliary layer, A conductive layer formed on the side opposite to the diffusion auxiliary layer of the dopant layer is laminated and then alloyed.

  Alternatively, the semiconductor device of the present invention includes a semiconductor layer made of a nitride semiconductor and an electrode layer formed on the surface of the semiconductor layer. The electrode layer includes an adhesion layer formed on the surface of the semiconductor layer, a dopant layer formed on the opposite side of the adhesion layer to the semiconductor layer, a diffusion auxiliary layer formed on the opposite side of the adhesion layer of the dopant layer, and diffusion A conductive layer formed on the side of the auxiliary layer opposite to the diffusion auxiliary layer is laminated and then alloyed.

  In these configurations, by having the diffusion auxiliary layer and the dopant layer, the elements constituting the dopant layer are sufficiently diffused even at a low heat treatment temperature. For example, the impurity doping concentration is low or the impurity is doped before the heat treatment. Even in the case where an electrode layer is formed on a semiconductor layer made of a nitride semiconductor that has not been formed, ohmic connection with the semiconductor layer can be made low resistance. In addition, since the heat treatment temperature is low, adverse effects on the electrode surface caused by high-temperature heat treatment such as purple plague can be suppressed. In addition, since the heat treatment temperature is low, damage to the semiconductor layer can be reduced. Note that an electrode layer having a configuration in which an adhesion layer, a diffusion assisting layer, a dopant layer, and a conductive layer are stacked in this order from the semiconductor layer side can achieve lower resistance.

  In the semiconductor device of the present invention, it is preferable that at least one element selected from Ti, W, Cr, V, Pd, and Ta is selected and used for the adhesion layer. By selecting these elements, the adhesion between the semiconductor layer and the electrode layer can be strengthened.

  In the semiconductor device of the present invention, it is preferable that the nitride semiconductor is a GaN-based semiconductor, and the dopant layer is selected from at least one element of Si, Ge, and Sn. These elements function as n-type dopants in the semiconductor layer made of a GaN-based semiconductor after the heat treatment.

  In the semiconductor device of the present invention, the nitride semiconductor is a GaN-based semiconductor, and the conductive layer is preferably made of a material that contributes to contact resistance by being replaced with Ga by heat treatment.

  In the semiconductor device of the present invention, for example, Al can be selected as the conductive layer, and Au can be selected as the diffusion auxiliary layer, for example.

  The semiconductor device of the present invention preferably includes a protective layer formed on the surface of the electrode layer, and the protective layer is preferably made of a material having a higher melting point than each material constituting the electrode layer.

  In this configuration, the flatness of the surface connecting the electrode layer to another circuit can be further improved by the protective layer.

  In the semiconductor device of the present invention, it is preferable that at least one element selected from Mo, Ta, W, and Nb is selected and used for the protective layer.

  The semiconductor device manufacturing method of the present invention includes a first step of preparing a semiconductor layer made of a nitride semiconductor, a second step of forming an electrode layer on the surface of the semiconductor layer, and heat-treating the electrode layer. A third step. The second step includes a step of forming an adhesion layer on the surface of the semiconductor layer, a step of forming a diffusion auxiliary layer on the surface of the adhesion layer, a step of forming a dopant layer on the surface of the diffusion prevention layer, Forming a conductive layer on the surface of the dopant layer.

  Alternatively, in the method of manufacturing a semiconductor device according to the present invention, a first step of preparing a semiconductor layer made of a nitride semiconductor, a second step of forming an electrode layer on the surface of the semiconductor layer, and heat-treating the electrode layer A third step. The second step includes a step of forming an adhesion layer on the surface of the semiconductor layer, a step of forming a dopant layer on the surface of the adhesion layer, a step of forming a diffusion auxiliary layer on the surface of the dopant layer, and diffusion. Forming a conductive layer on the surface of the auxiliary layer.

  In these manufacturing methods, an adverse effect on the electrode surface due to a high-temperature heat treatment such as purple plague can be suppressed while realizing a low-resistance ohmic connection between the semiconductor layer and the electrode layer.

  In the method for manufacturing a semiconductor device of the present invention, the heat treatment is preferably performed at 800 ° C. or lower.

  In this manufacturing method, the adverse effect on the electrode surface can be further suppressed.

  In addition, the method for manufacturing a semiconductor device according to the present invention preferably further includes a step of forming a protective layer made of a material having a melting point higher than that of each material constituting the electrode layer on the surface of the electrode layer.

  In this manufacturing method, it is possible to manufacture a semiconductor device in which the flatness of the surface connecting the electrode layer to another circuit is further improved.

  According to the present invention, the resistance value of the ohmic connection can be kept low and the flatness of the electrode surface can be improved.

1 is a partial cross-sectional view of a semiconductor device according to a first embodiment of the present invention. It is an EDX image which shows the mode of the spreading | diffusion of the element (Mo, Al, Si) which comprises the electrode layer after heat processing. (A) shows the state of diffusion of Mo. (B) shows the state of Al diffusion. (C) shows the state of Si diffusion. It is the EDX image which shows the mode of diffusion of the element (Au, Ti) which comprises the electrode layer after heat processing, and the TEM image containing the whole electrode layer. (A) shows the state of diffusion of Au. (B) shows the state of Ti diffusion. (C) shows a TEM image. It is a figure which shows the result of having compared the contact resistivity in a conventional structure (comparative structure) and this application structure. (A) shows the figure which plotted the contact resistivity of each sample. (B) shows a table comparing the electrode configuration and annealing treatment conditions of the conventional configuration and the present configuration. It is the image which image | photographed the surface of the electrode using this application structure with the optical microscope. It is the figure which showed the relationship between the ratio of the thickness of a spreading | diffusion auxiliary | assistant layer, and the thickness of a conductive layer, and contact resistivity. It is the image which image | photographed the surface of the electrode at the time of changing only the thickness of a diffusion assistance layer with the optical microscope. It is a partial cross section figure of the semiconductor device concerning the 2nd Embodiment of this invention. It is a figure which shows the comparison of the contact resistivity in the electrode structure of the semiconductor device which concerns on 2nd Embodiment, and the contact resistivity in the electrode structure of the semiconductor device which concerns on 1st Embodiment. It is the image which image | photographed the surface of the electrode connected by ohmic formed with the conventional electrode structure with the optical microscope.

(First embodiment)
A semiconductor device and a semiconductor device manufacturing method according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a partial cross-sectional view of a semiconductor device according to the first embodiment of the present invention. A semiconductor device 10 in FIG. 1 is a field effect transistor (FET).

  The semiconductor device 10 includes a base substrate 20 and a semiconductor layer 30. On the surface of the semiconductor layer 30, a gate electrode (not shown) having a Schottky connection with the semiconductor layer 30 and a drain electrode and a source electrode with ohmic connection with the semiconductor layer 30 are formed. . The drain electrode and the source electrode are formed by the electrode layer 40 and the protective layer 50 in FIG.

The base substrate 20 is made of, for example, single crystal Al ₂ O ₃ (sapphire), Si, SiC, or the like.

  The semiconductor layer 30 includes, for example, a first semiconductor layer 31 and a second semiconductor device 32 that include the same material but have different compositions. The first semiconductor layer 31 and the second semiconductor layer 32 are, for example, non-doped semiconductors.

  The first semiconductor layer 31 is formed on the surface of the base substrate 20. The second semiconductor layer 32 is formed on the surface of the first semiconductor layer 31.

  The first semiconductor layer 31 is made of, for example, GaN, and the second semiconductor layer 32 is made of AlGaN. The semiconductor layer 30 including the first semiconductor layer 31 and the second semiconductor layer 32 has, for example, a single heteroepi structure. That is, the first semiconductor layer 31 and the second semiconductor layer 32 are heterojunction. A two-dimensional electron gas is generated at the interface between the first semiconductor layer 31 and the second semiconductor layer 32.

  The electrode layer 40 is formed on the surface of the semiconductor layer 30, that is, on the surface of the second semiconductor layer 32. The electrode layer 40 includes an adhesion layer 41, a conductive layer 42, a dopant layer 43, and a diffusion auxiliary layer 44, and the dopant layer 43 and the diffusion auxiliary layer 44 are sandwiched between the adhesion layer 41 and the conductive layer 42. These are layers alloyed by heat treatment (annealing).

  Specifically, the electrode layer 40 is laminated in the order of the adhesion layer 41, the diffusion auxiliary layer 44, the dopant layer 43, and the conductive layer 42 from the semiconductor layer 30 side before being alloyed by the heat treatment.

  The adhesion layer 41 is a layer for bringing the electrode layer 40 into close contact with the semiconductor layer 30. As the material of the adhesion layer 41, Ti, W, Cr, V, Pd, Ta or the like is used. When the GaN-based semiconductor layer 30 is used as in the present embodiment, the adhesion layer 41 is preferably made of Ti. By using Ti for the adhesion layer 41, TiN is formed by reaction with the GaN-based semiconductor constituting the semiconductor layer 30 by heat treatment, and can contribute to the ohmic connection between the electrode layer 40 and the semiconductor layer 30.

  The conductive layer 42 is a layer of a material that may replace Ga in the GaN-based semiconductor layer 30. Specifically, the conductive layer 42 may use an element in the same group as Ga. For example, Al is preferable. By using Al, the environmental resistance is high and the contact resistivity can be lowered.

  The dopant layer 43 is made of a material that becomes an n-type dopant with respect to the GaN-based semiconductor layer 30. The dopant layer 43 is preferably Si, Ga, Sn or the like. In particular, Si is preferably used for the dopant layer 43. Since Si has a high activation rate as an n-type dopant for the nitride semiconductor, the semiconductor layer 30 can be effectively doped with n-type.

  The diffusion auxiliary layer 44 is a layer provided to facilitate the diffusion of the elements of the dopant layer 43. For example, Au is preferably used as the material of the diffusion auxiliary layer 44.

  Furthermore, the diffusion auxiliary layer 44 is preferably thinner than the conductive layer 42. Generation of purple plague can be suppressed by reducing the layer thickness.

  The protective layer 50 is formed on the surface of the electrode layer 40, that is, the surface of the conductive layer 42. The protective layer 50 is made of a material having a melting point higher than that of each material constituting the electrode layer 40. For example, Mo, Ta, W, Nb or the like is used for the protective layer 50. In particular, it is preferable to use Mo for the protective layer 50. Mo is easy to form, and hardly forms an alloy with the material of each layer of the electrode layer 40 described above. Therefore, even when heat treatment is performed, high flatness of the surface of the protective layer 50, that is, the surface as the drain electrode and the source electrode can be ensured. The protective layer 50 can be omitted, but is preferably provided.

  The semiconductor device 10 according to the first embodiment is manufactured as follows.

  First, a base substrate 20 is prepared, and a metal organic chemical vapor deposition (MOCVD) method and a molecular beam epitaxial growth method are formed on the surface of the base substrate 20 in the order of a first semiconductor layer 31 and a second semiconductor layer 32. The semiconductor layer 30 is formed by an epitaxial growth method such as the above.

  Next, the adhesion layer 41, the diffusion auxiliary layer 44, the dopant layer 43, and the conductive layer 42 are sequentially formed on the surface of the semiconductor layer 30 by using a vacuum deposition method, a sputtering method, an electron beam (EB) deposition method, or the like. Form.

  Next, the protective layer 50 is formed on the surface of the conductive layer 42 using a vacuum deposition method, a sputtering method, an EB deposition method, or the like.

  Next, heat treatment (annealing treatment) is performed at a preset temperature and time. At this time, the heat treatment temperature is preferably 800 ° C. or lower. If the heat treatment temperature does not greatly exceed 800 ° C., 800 ° C. or higher can be applied depending on the required specifications of the semiconductor device 10.

  By the heat treatment, the electrode layer 40 is alloyed, the elements constituting the electrode layer diffuse, and two-dimensional electrons generated at the interface between the first semiconductor layer 31 and the second semiconductor layer 32 of the electrode layer 40 and the semiconductor layer 30. The gas is ohmically connected.

  2 and 3 are an EDX image and a TEM image showing a state of diffusion of elements constituting each layer after the heat treatment. The higher the element concentration, the more white the image is displayed. 2A shows an EDX image of Mo of the protective layer 50, FIG. 2B shows an EDX image of Al of the conductive layer 42, and FIG. 2C shows an EDX image of Si of the dopant layer 43. Show. 3A shows an EDX image of Au of the diffusion auxiliary layer 44, FIG. 3B shows an EDX image of Ti of the adhesion layer 41, and FIG. 3C shows a TEM image. 2A, 2B, 2C, 3A, 3B, and 3C are the same shooting positions. 2 and 3, IF indicates an interface between the electrode layer and the semiconductor layer.

  As shown in FIGS. 2 and 3, each layer (adhesion layer 41, conductive layer 42, dopant layer 43, diffusion assisting layer 44) constituting the electrode layer 40 is configured by using the configuration and manufacturing method of the present embodiment. Each element (Ti, Al, Si, Au) to be diffused effectively in the electrode layer 40 and in the vicinity of the interface of the second semiconductor layer 32. Thereby, the resistance of the ohmic connection between the electrode layer 40 and the semiconductor layer 30 can be reduced.

  On the other hand, since the element (Mo) constituting the protective layer 50 has a high melting point, it hardly diffuses and is distributed on the surface of the electrode layer 40. In the protective layer 50, each element constituting the electrode layer 40 is not diffused. Therefore, the flatness of the surface of the protective layer 50 can be maintained high.

  FIG. 4 is a diagram showing a result of comparison of contact resistivity between the conventional configuration (comparative configuration) and the present configuration. FIG. 4A is a diagram plotting the resistivity of each sample. FIG. 4B shows a table comparing the electrode configuration and annealing treatment conditions of the conventional configuration and the present configuration.

  Here, the conventional configuration is an electrode structure in which Ti as an adhesion layer, Al as a conductive layer, Pt as a barrier layer, and Au as a protective layer are sequentially stacked from the semiconductor layer side. The thickness of each layer is Ti / Al / Pt / Au = 50 [Å] / 2000 [Å] / 400 [Å] / 1500 [Å]. The annealing temperature is 870 [° C.], and the annealing time is 30 [sec. ].

  On the other hand, the configuration of the present application is an electrode structure in which Ti as an adhesion layer, Au as a diffusion auxiliary layer, Si as a dopant layer, Al as a conductive layer, Mo as a protective layer are sequentially stacked from the semiconductor layer side. is there. The thickness of each layer is Ti / Au / Si / Al / Mo = 250 [Å] / 100 [Å] / 100 [Å] / 1000 [Å] / 2000 [Å]. The annealing temperature is 770 [° C.], and the annealing time is 180 [sec. ].

As shown in FIG. 4, by using the present configuration and the manufacturing method, a contact resistivity of the order of 10 ⁻⁶ [Ω · cm ² ] is realized in the same manner as the conventional configuration and manufacturing method while lowering the annealing temperature. be able to.

  FIG. 5 is an image obtained by photographing the surface of the electrode using the configuration of the present application with an optical microscope. In FIG. 5, 30 is a semiconductor layer and 50 is a protective layer. As shown in FIG. 5, by using the configuration and the manufacturing method of the present application, the occurrence of purple plague can be significantly suppressed, and the electrode surface is hardly uneven. On the other hand, in the conventional configuration, it was confirmed that unevenness occurred on the electrode surface when annealing conditions similar to those of the present invention were used. Therefore, by using the configuration and the manufacturing method of the present invention, the semiconductor device 10 having a low resistance as a device, that is, a low resistance including a connection surface with an external circuit can be formed.

  In addition, when only one of the diffusion auxiliary layer 44 and the dopant layer 43 having the configuration of the present application is used, the resistance value increases. Therefore, it is preferable to use the adhesion layer 41, the conductive layer 42, the dopant layer 43, and the diffusion auxiliary layer 44 described above for the electrode layer 40. That is, it is not a configuration in which only the dopant layer is simply sandwiched between the adhesion layer and the conductive layer or the diffusion auxiliary layer is simply sandwiched between the adhesion layer and the conductive layer. The above-mentioned operation and effect can be obtained more reliably by adopting a configuration sandwiching both the diffusion auxiliary layer and the diffusion auxiliary layer.

  FIG. 6 is a diagram showing a change in contact resistivity when the ratio of the thickness of the diffusion auxiliary layer and the thickness of the conductive layer is changed in the electrode structure of the present application configuration according to the first embodiment. In FIG. 6, the ratio of the thickness of the auxiliary diffusion layer 44 to the thickness of the conductive layer 42 is used on the horizontal axis, and the contact resistivity is used on the vertical axis.

  As shown in FIG. 6, the diffusion auxiliary layer 44 is preferably thinner than the conductive layer 42 if the elements constituting the dopant layer 43 are sufficiently diffused.

  FIG. 7 is an image obtained by photographing the surface of the electrode with an optical microscope when only the thickness of the diffusion assisting layer is changed. In FIG. 7, D1, D2, D3, and D4 indicate the thickness of the diffusion auxiliary layer 44, and D1 <D2 <D3 <D4. In FIG. 7, 30 is a semiconductor layer and 50 is a protective layer.

  As shown in FIG. 7, the thinner the diffusion assisting layer 44, the less the unevenness of the electrode surface. Accordingly, the diffusion assisting layer 44 is preferably thin.

  As described above, by using the configuration and the manufacturing method of the present embodiment, it is possible to realize a semiconductor device in which the resistance value of the ohmic connection is kept low and the flatness of the electrode surface is high.

  Further, as in this embodiment, by using a semiconductor that is non-doped before heat treatment as the semiconductor layer, the doping concentration in the entire semiconductor layer is lowered, and the resistance of the semiconductor device itself when no voltage is applied is ensured to be high. be able to. Therefore, it is more suitable for use in a high-frequency power amplifier or the like that has a low leakage current when turned off.

(Second Embodiment)
Next, a semiconductor device and a method for manufacturing the semiconductor device according to the second embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a partial cross-sectional view of a semiconductor device according to the second embodiment of the present invention.

  The semiconductor device 10A of the present embodiment is different in the stacked structure of the electrode layer 40A before the heat treatment, and other configurations are the same as those of the semiconductor device 10 according to the first embodiment. Therefore, different parts from the semiconductor device 10 according to the first embodiment will be specifically described.

  The electrode layer 40 </ b> A has a configuration in which an adhesion layer 41, a dopant layer 43, a diffusion auxiliary layer 44, and a conductive layer 42 are stacked in this order from the semiconductor layer 30 side.

  FIG. 9 is a diagram showing a comparison of the contact resistivity of the contact portion between the electrode configuration of the second embodiment and the electrode configuration of the first embodiment. In FIG. 9, the horizontal axis represents the annealing time, and the vertical axis represents the contact resistivity. In FIG. 9, the solid line is the configuration of the first embodiment, and the broken line is the configuration of the second embodiment. The thickness of each layer is the same for both the electrode 40 of the first embodiment and the electrode 40A of the second embodiment, and the annealing temperature is also the same condition in the first embodiment and the second embodiment.

As shown in FIG. 9, a contact resistivity of the order of 10 ⁻⁶ [Ω · cm ² ] can be realized with any of the configurations of the first embodiment and the second embodiment. However, the configuration of the first embodiment can make the contact resistivity lower than that of the configuration of the second embodiment.

  Further, as shown in FIG. 9, in any configuration, the value of contact resistivity does not depend on the annealing time.

  In the above-described embodiment, an example of a field effect transistor (FET) is shown as the semiconductor device. However, if the semiconductor device is in an ohmic connection between the electrode layer and the semiconductor layer, the present invention may be implemented. The configuration of the form and the manufacturing method can be applied.

  Moreover, although the example using the semiconductor layer which takes a single hetero structure was shown in the above-described embodiment, a semiconductor layer such as a double hetero structure may be used. The semiconductor layer may be a semiconductor layer that does not have a heterostructure.

10, 10A: Semiconductor device 20: Base substrate 30: Semiconductor layer 31: First semiconductor layer 32: Second semiconductor layer 40, 40A: Electrode layer 41: Adhesion layer 42: Conductive layer 43: Dopant layer 44: Diffusion auxiliary layer 50 : Protective layer

Claims (8)

A semiconductor layer made of a nitride semiconductor;
An electrode layer formed on the surface of the semiconductor layer,
The electrode layer is
An adhesion layer formed on the surface of the semiconductor layer, wherein at least one element of Ti, W, Cr, V, Pd, Ta is selected and used ;
A diffusion auxiliary layer formed on the opposite side of the adhesion layer from the semiconductor layer and using Au ;
A dopant layer which is formed on the opposite side to the adhesion layer of the diffusion assisting layer, and at least one element of Si, Ga, Sn is selectively used ;
A conductive layer formed on the opposite side of the diffusion assisting layer of the dopant layer, wherein at least one element of Ga and Al is selectively used ;
Including
The element used for the adhesion layer, the element used for the diffusion auxiliary layer, the element used for the dopant layer, and the element used for the conductive layer are diffused and alloyed in each other layer ,
Semiconductor device. A semiconductor layer made of a nitride semiconductor;
An electrode layer formed on the surface of the semiconductor layer,
The electrode layer is
An adhesion layer formed on the surface of the semiconductor layer, wherein at least one element of Ti, W, Cr, V, Pd, Ta is selected and used ;
A dopant layer formed on the opposite side of the adhesion layer from the semiconductor layer, wherein at least one element of Si, Ga, Sn is selected and used ;
A diffusion auxiliary layer formed on the opposite side of the adhesion layer from the adhesion layer and using Au ;
A conductive layer formed on a side opposite to the diffusion auxiliary layer of the diffusion auxiliary layer, wherein at least one element of Ga and Al is selectively used ;
Including
The element used for the adhesion layer, the element used for the diffusion auxiliary layer, the element used for the dopant layer, and the element used for the conductive layer are diffused and alloyed in each other layer ,
Semiconductor device. A protective layer formed on the surface of the alloyed electrode layer;
The protective layer is made of a material having a melting point higher than each material constituting the electrode layer and is not alloyed.
The semiconductor device according to claim 1 or 2 . For the protective layer, at least one element of Mo, Ta, W, and Nb is selected and used.
The semiconductor device according to claim 3 . A first step of preparing a semiconductor layer made of a nitride semiconductor;
A second step of forming an electrode layer on the surface of the semiconductor layer;
And a third step of alloying the electrode layer by heat treatment,
The second step includes
Forming an adhesion layer on the surface of the semiconductor layer by selecting and using at least one element of Ti, W, Cr, V, Pd, Ta ;
Forming a diffusion auxiliary layer using Au on the surface of the adhesion layer;
Forming a dopant layer on the surface of the diffusion prevention layer by selecting and using at least one element of Si, Ga, Sn ;
Forming a conductive layer on the surface of the dopant layer by selecting and using at least one element of Ga and Al ;
I have a,
The alloying is an alloying of an element used for the adhesion layer, an element used for the diffusion auxiliary layer, an element used for the dopant layer, and an element used for the conductive layer.
The method of manufacturing a semiconductor device comprising a call. A first step of preparing a semiconductor layer made of a nitride semiconductor;
A second step of forming an electrode layer on the surface of the semiconductor layer;
And a third step of alloying the electrode layer by heat treatment,
The second step includes
Forming an adhesion layer on the surface of the semiconductor layer by selecting and using at least one element of Ti, W, Cr, V, Pd, Ta ;
Forming a dopant layer on the surface of the adhesion layer by selecting and using at least one element of Si, Ga, and Sn ;
Forming a diffusion assisting layer using Au on the surface of the dopant layer;
Forming a conductive layer on the surface of the diffusion auxiliary layer by selecting and using at least one element of Ga and Al ; and
Have,
The alloying is an alloying of an element used for the adhesion layer, an element used for the diffusion auxiliary layer, an element used for the dopant layer, and an element used for the conductive layer.
The method of manufacturing a semiconductor device comprising a call. The heat treatment is performed at 800 ° C. or lower.
A method for manufacturing a semiconductor device according to claim 5 . A step of forming a protective layer which is made of a material having a melting point higher than each material constituting the electrode layer and is not alloyed on the surface of the alloyed electrode layer,
The method for manufacturing a semiconductor device according to claim 5 , further comprising: