JP6090752B2 - Silicon wafer evaluation method - Google Patents

Description

  The present invention relates to a silicon wafer evaluation method using a strain measurement device (SIRD device) using infrared photoelasticity.

  In the semiconductor lithography process, it is necessary to form a fine pattern uniformly on the wafer. A silicon wafer as a substrate is required to have a flat wafer shape during exposure. Even when a silicon wafer is flat at the beginning of manufacture, thermal stress is applied to the wafer in various heat treatment steps such as film formation heat treatment during device formation and damage recovery heat treatment after ion implantation treatment, and the wafer may be deformed.

  In the lithography process, when overlaying layers using an overlay inspection device (overlay measurement device), a measurement mark for the next layer is formed on the measurement mark attached to the underlying layer, and the amount of misalignment between the marks Thus, the amount of wafer deformation between layers can be known. Then, a correction term is calculated from the amount of deviation measured by the overlay inspection apparatus, and after the resist pattern is peeled off, re-exposure is performed in consideration of the correction term, thereby performing correction patterning in consideration of the amount of wafer deformation. Is called.

  However, if the amount of deformation of the wafer is so large that overlay correction is difficult, the wafer is considered defective. Moreover, since overlay inspection takes a very long time, not all wafers are inspected. In particular, for mass-produced varieties, overlay inspection is hardly performed, so if the wafer is deformed, it is difficult to form a pattern without misalignment between layers, and the yield in final product inspection decreases. Will be.

  As a factor of the deformation of the wafer in such a device heat treatment process, generation of slip can be mentioned. It is known that slip occurs due to the influence of the oxygen concentration of a wafer serving as a substrate and the size and density of oxygen precipitates, thereby increasing the amount of deviation in overlay inspection.

  For this, a method is disclosed in which slip generated in a wafer surface is evaluated by revealing only a short-period component from a depolarization value measured by a SIRD apparatus (for example, Non-Patent Document 1). reference).

H.D.Geiler, et al., Material Science in Semiconductor processing, vol.5 (2002), pp.445-455

However, in recent years, with the miniaturization of device design rules, the allowable width of the above-described overlay shift amount in the lithography process has narrowed, and wafer deformation due to distortion that is not detected as slip has become a problem. .
Such distortion that is not detected as slip cannot be evaluated by the method described in Non-Patent Document 1.

  For this reason, when device formation is performed on a wafer manufactured based on a new standard, wafer samples having various oxygen concentrations and oxygen precipitates are prepared. The concentration and the size and density of oxygen precipitates could not be determined. Such a device prototype evaluation takes about 1 to 3 months, which has been a factor in delaying the development of new wafer products.

  Therefore, in order to further improve the yield in the device heat treatment process, and from the viewpoint of shortening the development period of a wafer suitable for device formation, there is a need for a simple evaluation method for distortion inside the wafer that is not detected as slip. Yes.

  The present invention has been made in order to solve the above technical problems, and in order to speed up the development of a wafer suitable for device formation, the distortion inside the wafer that does not lead to the occurrence of slipping can be simplified in a short time. An object of the present invention is to provide a method for evaluating a silicon wafer that can be evaluated in a simple manner.

According to the silicon wafer evaluation method of the present invention, the depolarization value measured by the silicon wafer SIRD apparatus is obtained by removing the short-period component by the smoothing process and using the obtained dispersion value of the long-period component. The internal strain of the wafer due to externally applied stress and thermal stress is evaluated on the wafer, and the shift amount of the pattern position formed on the silicon wafer surface is predicted based on the evaluation.
According to such an evaluation method using the SIRD apparatus, it is possible to easily and easily evaluate the distortion inside the wafer that does not lead to the occurrence of slipping in a short time, and accurately and efficiently predict and evaluate the deviation of the pattern formation position. Can be performed.

In the said evaluation method, it is preferable that the data period used for the said smoothing process shall be 5-20 mm.
By performing such a smoothing process, it is possible to more efficiently predict and evaluate the deviation of the pattern formation position.

According to the silicon wafer evaluation method of the present invention, by using the depolarization value measured by the SIRD apparatus, the distortion inside the wafer that does not lead to the occurrence of slip can be easily evaluated in a short time. Therefore, it is possible to accurately and efficiently predict and evaluate the deviation of the pattern formation position without performing a prototype device.
Therefore, the evaluation method according to the present invention can grasp the deformation of the wafer due to a minute stress, and can contribute to speeding up the development of a wafer suitable for device formation.

It is an example of the depolarization value data measured with the SIRD apparatus about the silicon wafer. It is data which made only the short period component after carrying out the averaging process to the depolarization value shown in FIG. The depolarization value shown in FIG. 1 is data having only a long period component after smoothing processing. It is an in-plane map of the depolarization value measured with the SIRD apparatus in the Example. FIG. 5 is an in-plane map showing only long-period components after smoothing processing of the depolarization values shown in FIG. 4. FIG. It is the in-plane map which showed the deviation | shift amount by the pattern alignment evaluation in an Example. It is the graph which showed the relationship between the dispersion value of the data of the long-period component of the depolarization value in an Example, and the measured pattern alignment shift amount (3 (sigma)). FIG. 5 is an in-plane map showing only a short period component after the averaging process of the depolarization value shown in FIG. 4. FIG.

Hereinafter, the present invention will be described in more detail.
The silicon wafer evaluation method according to the present invention evaluates internal strain of a wafer using a SIRD apparatus. Specifically, with respect to the depolarization value measured by the SIRD apparatus, the short period component is removed by the smoothing process, and using the obtained dispersion value of the long period component, the stress applied from the outside to the silicon wafer and Evaluate internal strain of wafer due to thermal stress.
According to such a method, distortion inside the wafer that does not lead to occurrence of slip can be easily evaluated in a short time.

The inspection by the SIRD apparatus is an inspection that can analyze distortion by irradiating a stressed sample with infrared light and measuring the polarization state change when passing through the birefringence area caused by the photoelastic effect. Is the method.
Usually, the depolarization value measured by the SIRD apparatus is a mixture of the distortion of the long period component and the short period component. FIG. 1 shows an example of depolarization value data measured with a SIRD apparatus for a silicon wafer.

The long-period component is mainly due to the crystal structure, and shows a stress distribution due to the slip surface. In the depolarization image, it appears as a four-fold symmetrical image of the cross, and the track data (measured at the r-θ axis; θ1 round at the radius r position) is detected as a cos wave.
On the other hand, the short period component is local distortion and has a correlation with the occurrence of slip. For this reason, conventionally, floating average processing for revealing only the short-period component from the depolarization value is performed, and the long-period component is smoothed and removed. FIG. 2 shows data of short-period components after averaging the depolarization values shown in FIG.
After that, the wafer surface is divided by the grid width (for example, x = 1 mm, y = 1 mm), and when the short period component exceeds the threshold value (for example, ± 40) in the section, the section is set as a bad cell on the map. A mark was attached, and the ratio of the bad cells was expressed as an area ratio with respect to the entire wafer, and was quantified as a strain area ratio.
On the other hand, the present invention has found a correlation with the amount of deviation of the pattern position formed on the surface of the silicon wafer by evaluating the distortion using a long-period component that is normally removed in slip measurement. It was made based on.

As described above, the depolarization value is a value obtained by combining a long period component (global stress) and a short period component (local strain such as slip).
In the present invention, this depolarization value is smoothed to remove the short period component, and only the long period component. FIG. 3 shows data after the depolarization value smoothing process shown in FIG.

The smoothing data period at this time is preferably 5 to 20 mm. This length corresponds to about 0.5 to 2.5% of the track length (circumference length) of the outermost circumference of the wafer to be measured, and preferably about 1%.
When the smoothing data period is less than 5 mm, the short period component remains in the analysis data (long period component). On the other hand, when the smoothing data period exceeds 20 mm, the data becomes too smooth and evaluation is difficult.

Then, assuming that the amplitude of the long-period component is the magnitude of the distortion, a dispersion value serving as a variation index is obtained from the long-period component data of the depolarization value.
At this time, if the variation index is (maximum value−minimum value), it is not preferable because it is easily affected by noise due to dust or the like when measuring the amount of transmitted light. In order to accurately evaluate internal distortion, a dispersion value is used. It is preferable.

Since this dispersion value correlates with the amount of misalignment at the time of pattern formation in the lithography process, the evaluation of internal distortion due to the long-period component of the depolarization value measured with the SIRD apparatus as described above is used. Thus, it is possible to estimate the amount of deviation of the pattern position formed on the silicon wafer surface.
Therefore, in the new product development stage of silicon wafers, heat treatment simulating the device is performed without actually performing pattern formation and evaluating misalignment of the alignment position, and various oxygen concentrations and oxygen precipitate sizes and densities can be obtained. By applying stress to the wafer in this state, it is possible to easily evaluate the degree of deformation of the wafer due to the stress and the shift amount of the pattern formation position using the SIRD apparatus.
As described above, according to the evaluation method according to the present invention, it is possible to accurately evaluate the deviation of the pattern formation position in a short time, and thus it is possible to shorten the development time of the silicon wafer.

  In addition, the silicon wafer which is an evaluation object in the present invention is not particularly limited. For example, after slicing a silicon single crystal obtained by Czochralski (CZ) method, floating zone (FZ) method or the like, a silicon wafer in which at least a surface on which a semiconductor device is formed is mirror-finished is applied, an epitaxial wafer, Any of SOI wafers and the like may be used.

EXAMPLES Hereinafter, although this invention is demonstrated further more concretely based on an Example, this invention is not restrict | limited by the following Example.
Silicon wafer sliced from a silicon single crystal grown by the Czochralski method and mirror-polished on both sides, having a diameter of 300 mm, an oxygen concentration of 1.25 × 10 ¹⁸ atoms / cm ³ , and a nitrogen concentration of 5 × 10 ¹⁴ atoms / cm ³ Then, heat treatment was performed at 1200 ° C. for 1 hour in an argon atmosphere.
An oxide film and an electrode pattern were formed on each wafer, and thermal stress was applied by rapid thermal annealing (RTA treatment; Rapidthermal annealing). For the thermal stress, the offset value of the outermost peripheral thermometer was changed during the RTA process, and a temperature gradient was applied between the central portion and the outer peripheral portion to change the degree of the stress.

After the RTA treatment, a pattern was formed with a resist, and the deformation amount of the wafer was measured as a deviation amount for pattern alignment evaluation.
Thereafter, the resist was removed, the oxide film and the electrode pattern were removed with a hydrogen fluoride solution, and measurement was performed with a SIRD apparatus.

FIG. 4 shows an in-plane map of the depolarization value measured by the SIRD apparatus, FIG. 5 shows an in-plane map of only the long period component after smoothing the depolarization value, and FIG. The in-plane map about the amount of pattern alignment deviation performed is shown.
FIG. 7 is a graph showing the relationship between the dispersion value of the long-period component data (FIG. 5) after the depolarization value smoothing process and the measured pattern alignment shift amount (FIG. 6). The amount of deviation in FIG. 7 is represented by 3σ with respect to the standard deviation σ of the amount of deviation measured at 38 locations on the wafer surface. Note that the exposure accuracy in patterning is 10 nm, and the data at the two points on the left side of the graph are those when RTA processing is not performed.

  As a comparison, FIG. 8 shows an in-plane map of only the short period component (slip distortion) after averaging the depolarization value by the conventional method.

In the in-plane map of the short period component shown in FIG. 8, slip generated by the RTA process was observed in the left part of the outer periphery, and stains at the time of pattern peeling were observed in the lower part. Thus, it was recognized that the sample after pattern peeling has a lot of noise components due to surface dirt and dust, and these local noises have a great influence in the analysis of short-period components.
Therefore, although there is a high risk of erroneous detection in an evaluation including a short-period component, it can be said that an evaluation with only a long-period component as in the present invention is not easily affected by this, and an accurate evaluation is possible.

Claims (1)

  For the depolarization value measured by the SIRD apparatus of the silicon wafer, the short period component is removed by the smoothing process, and the stress and thermal stress applied to the silicon wafer from the outside using the dispersion value of the obtained long period component. A method for evaluating a silicon wafer, comprising: evaluating an internal strain of the wafer due to the step, and predicting a shift amount of a pattern position formed on the surface of the silicon wafer based on the evaluation.