JP6092482B2 - 半導体デバイスを処理するための方法および構造 - Google Patents
半導体デバイスを処理するための方法および構造 Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/701—Tape-automated bond [TAB] connectors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P54/00—Cutting or separating of wafers, substrates or parts of devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/7448—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the bond interface between the auxiliary support and the wafer comprising two or more, e.g. multilayer adhesive or adhesive and release layer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/7412—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/7422—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/744—Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
- Chemical & Material Sciences (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Life Sciences & Earth Sciences (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Wood Science & Technology (AREA)
- Organic Chemistry (AREA)
- Dicing (AREA)
- Formation Of Insulating Films (AREA)
Description
本出願は、2013年7月30日に出願された米国特許出願整理番号13/954,133“METHODS AND STRUCTURES FOR PROCESSING SEMICONDUCTOR DEVICES”の出願日の利益を享受する権利を主張する。
Claims (21)
- 半導体デバイスの処理方法であって、
シラン材料にキャリア基板を暴露して前記キャリア基板の表面上にコーティングを形成することであって、前記シラン材料は、(XO)3 Si(CH2)nY、(XO)2 Si((CH2)nY)2 および(XO)3 Si(CH2)n Y(CH2)n Si(XO)3のみから成る群から選択される構造を有する化合物を含み、XOは加水分解性アルコキシ基であり、Yは有機官能基であり、nは非負整数である、ことと、
前記コーティングの一部を、前記コーティングの残りを除去することなく、少なくとも前記キャリア基板の周縁部に隣接する所で前記表面から除去することと、
前記表面の上側で前記キャリア基板に別の基板を接着結合することと、
前記キャリア基板から前記別の基板を分離することと、
を含む、ことを特徴とする方法。 - メトキシ基およびエトキシ基のみからなる群からXOを選択することをさらに含む、ことを特徴とする請求項1に記載の方法。
- Yは少なくとも一つの芳香環を含む、ことを特徴とする請求項1に記載の方法。
- 前記キャリア基板に前記別の基板を接着結合する前に、前記コーティングを少なくとも部分的に硬化することをさらに含む、ことを特徴とする請求項1から3のいずれか一項に記載の方法。
- 前記コーティングを少なくとも部分的に硬化することは、前記キャリア基板の前記周縁部に隣接する所で前記コーティングの前記部分を除去する前に、前記コーティングを硬化することを含む、ことを特徴とする請求項4に記載の方法。
- 少なくとも前記キャリア基板の周縁部に隣接する所で前記表面から前記コーティングの一部を除去することは、少なくとも部分的に硬化されたコーティングの一部を除去することを含む、ことを特徴とする請求項1から3のいずれか一項に記載の方法。
- シラン材料にキャリア基板を暴露して前記キャリア基板の表面の上にコーティングを形成することは、前記キャリア基板の表面の上に疎水性コーティングを形成することを含む、ことを特徴とする請求項1から3のいずれか一項に記載の方法。
- 少なくとも前記キャリア基板の周縁部に隣接する所で前記表面から前記コーティングの一部を除去することは、前記キャリア基板を溶剤に暴露することを含む、ことを特徴とする請求項1から3のいずれか一項に記載の方法。
- 前記キャリア基板に別の基板を接着結合することは、前記コーティングの上と、前記キャリア基板のコーティングされていない部分の上に、接着剤を塗布することを含む、ことを特徴とする請求項1から3のいずれか一項に記載の方法。
- 前記キャリア基板に別の基板を接着結合することは、前記キャリア基板に前記別の基板を結合する前に、前記別の基板の上に接着剤を塗布することを含む、ことを特徴とする請求項1から3のいずれか一項に記載の方法。
- 前記シラン材料は、1,2−ビス[トリエトキシシリル]エタン、1,2−ビス[トリメトキシシリル]オクタンおよび1,2−ビス[トリメトキシシリル]デカンのみから成る群から選択される材料を含む、ことを特徴とする請求項1から3のいずれか一項に記載の方法。
- シラン材料にキャリア基板を暴露して前記キャリア基板の表面上にコーティングを形成することは、前記シラン材料を含む溶液に前記キャリア基板を暴露することを含む、ことを特徴とする請求項1から3のいずれか一項に記載の方法。
- 前記シラン材料を含む溶液に前記キャリア基板を暴露することは、前記シラン材料と水とを含む溶液に前記キャリア基板を暴露することを含む、ことを特徴とする請求項12に記載の方法。
- 前記シラン材料を含む溶液に前記キャリア基板を暴露することは、前記シラン材料と有機溶媒とを含む溶液に前記キャリア基板を暴露することを含む、ことを特徴とする請求項12に記載の方法。
- 前記シラン材料に前記キャリア基板を暴露することは、体積百分率で約5パーセントのシラン材料と、体積百分率で約5パーセントの脱イオン水と、体積百分率で約90パーセントのメタノールまたはエタノールとを含む溶液に、前記キャリア基板を暴露することを含む、ことを特徴とする請求項14に記載の方法。
- 半導体デバイスの処理方法であって、
基板の表面の上に、Si−O−Siを含むポリマー材料を形成することと、
前記ポリマー材料の残留物を取除くことなく、前記基板の表面の周辺に少なくとも隣接した前記ポリマー材料の一部を除去することと、
前記表面上で前記基板へ他の基板を接着することと、
前記基板から前記他の基板を分離することと、
を含み、
前記基板の上に、Si−O−Siを含むポリマー材料を形成することは、シラン材料に前記基板を暴露することであって、前記シラン材料は、(XO)3Si(CH2)n Y、(XO)2 Si((CH2)n Y)2 および(XO)3 Si(CH2)n Y(CH2)n Si(XO)3 のみから成る群から選択される化合物を含み、XOは加水分解性アルコキシ基であり、Yは有機官能基であり、nは非負整数である、こと、を含む、ことを特徴とする方法。 - 基板の上に、Si−O−Siを含むポリマー材料を形成することは、前記シラン材料を硬化させることを更に含む、ことを特徴とする請求項16に記載の方法。
- シラン材料に前記基板を暴露することは、1,2−ビス[トリエトキシシリル]エタン、1,2−ビス[トリメトキシシリル]オクタンおよび1,2−ビス[トリメトキシシリル]デカンのみから成る群から選択される材料に前記基板を暴露することを含む、ことを特徴とする請求項16に記載の方法。
- 基板の上に、Si−O−Siを含むポリマー材料を形成することは、多孔質シランフィルムを形成することを含む、ことを特徴とする請求項16に記載の方法。
- Si−O−SiおよびM−O−Siを含む界面層を形成することをさらに含み、Mは金属である、ことを特徴とする請求項16に記載の方法。
- 前記基板へ他の基板を接着することは、実質的に前記ポリマー材料がない前記基板の一部に、前記他の基板を接着することを含む、ことを特徴とする請求項20に記載の方法。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/954,133 | 2013-07-30 | ||
| US13/954,133 US8962449B1 (en) | 2013-07-30 | 2013-07-30 | Methods for processing semiconductor devices |
| PCT/US2014/047426 WO2015017154A1 (en) | 2013-07-30 | 2014-07-21 | Methods and structures for processing semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2016535450A JP2016535450A (ja) | 2016-11-10 |
| JP6092482B2 true JP6092482B2 (ja) | 2017-03-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2016530849A Active JP6092482B2 (ja) | 2013-07-30 | 2014-07-21 | 半導体デバイスを処理するための方法および構造 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US8962449B1 (ja) |
| EP (1) | EP3028299B1 (ja) |
| JP (1) | JP6092482B2 (ja) |
| KR (1) | KR101720474B1 (ja) |
| CN (1) | CN105474375B (ja) |
| TW (1) | TWI542545B (ja) |
| WO (1) | WO2015017154A1 (ja) |
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2013
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- 2014-07-21 CN CN201480043545.9A patent/CN105474375B/zh active Active
- 2014-07-21 WO PCT/US2014/047426 patent/WO2015017154A1/en not_active Ceased
- 2014-07-21 JP JP2016530849A patent/JP6092482B2/ja active Active
- 2014-07-21 EP EP14832406.4A patent/EP3028299B1/en active Active
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11101167B2 (en) | 2019-03-18 | 2021-08-24 | Toshiba Memory Corporation | Semiconductor device manufacturing method and semiconductor device |
| US11862510B2 (en) | 2019-03-18 | 2024-01-02 | Kioxia Corporation | Semiconductor device manufacturing method and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105474375B (zh) | 2019-04-02 |
| KR101720474B1 (ko) | 2017-03-27 |
| JP2016535450A (ja) | 2016-11-10 |
| CN105474375A (zh) | 2016-04-06 |
| EP3028299A1 (en) | 2016-06-08 |
| EP3028299B1 (en) | 2021-11-03 |
| US9449940B2 (en) | 2016-09-20 |
| TWI542545B (zh) | 2016-07-21 |
| US20150035126A1 (en) | 2015-02-05 |
| US20150097301A1 (en) | 2015-04-09 |
| TW201514097A (zh) | 2015-04-16 |
| KR20160023916A (ko) | 2016-03-03 |
| WO2015017154A1 (en) | 2015-02-05 |
| US8962449B1 (en) | 2015-02-24 |
| EP3028299A4 (en) | 2017-03-22 |
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