JP6120368B2 - Multi-wiring board - Google Patents

Description

  The present invention relates to a multi-cavity wiring board in which a plurality of regions serving as wiring boards for housing electronic components such as semiconductor elements and crystal resonators are arranged.

FIG. 9 shows a small wiring board 50 used in an electronic component storage package for storing electronic components such as semiconductor elements and crystal resonators. Insulating layers 51a to 51d made of ceramics such as aluminum oxide are shown. A substantially rectangular insulating base 51 having a cavity 53 for accommodating the electronic component 52 on the upper surface, a plurality of wiring conductors 55 provided on the step 54 in the cavity 53, and an insulating layer 51a. Through 51c, one end of which is connected to the wiring conductor 55 on the step 54, and the other end of the wiring conductor 55 is connected to the wiring conductor 55 on the step through the via 56. doing.
In addition, with the request | requirement of the wiring density improvement of an approximate electronic apparatus, providing the some level | step difference 54 in the cavity 53 and providing the some wiring conductor 55 on each level | step difference 54 is performed. By providing a plurality of steps 54 for forming a wiring conductor in the cavity 53, more wiring conductors 55 can be formed in the insulating base 51.
In order to prevent the wiring conductor 55 from being oxidized and corroded on the exposed surface of the wiring conductor 55 on the step 54, and to improve the electrical connection between the wiring conductor 55 and the electronic component 52, For example, a plating layer 58 made of nickel plating having a thickness of about 1 to 10 μm and gold plating having a thickness of about 0.1 to 3 μm is applied by an electrolytic plating method. The wiring conductor 55 and the plating layer 58 on the step 54 constitute an internal electrode 59.
Similarly, the thickness of the wiring conductor 55 on the lower surface 57 is reduced, for example, in order to prevent the wiring conductor 55 from being oxidatively corroded and to have good electrical connection with the mounting pads 66 of the external electric circuit board 65. A plating layer 58 made of nickel plating having a thickness of about 1 to 10 μm and gold plating having a thickness of about 0.1 to 3 μm is applied by an electrolytic plating method. The wiring conductor 55 and the plating layer 58 on the lower surface 57 constitute an external electrode 60.

  According to this wiring board 50, the electronic component 52 is accommodated in the cavity 53 of the insulating base 51, and the electrode 61 of the electronic component 52 is electrically connected to the internal electrode 59 in the cavity 53 via the bonding wire 62. Thereafter, a lid 64 is joined to the cavity outer periphery 63 on the upper surface of the insulating base 51 to contain the electronic component 52 in an airtight manner, whereby an electronic device as a product is formed. It is mounted on the external electric circuit board 66 by being connected to the 65 mounting pads 66 via solder, and the electrode 61 of the electronic component 52 is electrically connected to the external electric circuit.

  Such a wiring board 50 has become smaller in size in response to the recent demand for downsizing of electronic devices. In order to facilitate handling of a large number of wiring boards, a single wide board is required. It is manufactured in the form of a so-called multi-cavity wiring board in which a large number of wiring boards are arranged vertically and horizontally on a ceramic multilayer substrate having an area.

10 and 11 show an example of a multi-piece wiring board, FIG. 10 is a plan view, and FIG. 11 is a cross-sectional view taken along the line AA of FIG. The multi-piece wiring board 70 is constituted by a ceramic multilayer board 71 formed by laminating a plurality of insulating layers 71a to 71d. A plurality of wiring board regions 72 that become wiring boards after division are arranged vertically and horizontally in the central portion of the ceramic multilayer substrate 71, and a disposal margin area 85 that is separated from the wiring board region 72 at the time of division is formed on the outer periphery.
Each wiring board region 72 has a cavity 73 for accommodating an electronic component on its upper surface, a plurality of steps 74 are provided in the cavity 73, and a plurality of wiring conductors 75 are provided on each step 74. Yes. The wiring conductor 75 is connected to the wiring conductor 75 on the lower surface 77 of the wiring board region 72 through a via 76 that penetrates the insulating layers 71a to 71c. 10 and 11, two stepped portions 74 are provided in the cavity 73, and a wiring conductor 75 is provided on each stepped portion 74.
A notch 86 is formed on the side surface of the discard margin region 85, and a plating electrode 87 made of a conductor layer is formed along the inner wall of the notch 86. By connecting the plating electrode 87 to a plating power source, a charge for electrolytic plating is applied to all the wiring conductors 75 on which the plating layer is to be deposited.

In order to deposit a nickel plating layer or a gold plating layer on the exposed surface of each wiring conductor 75 by electrolytic plating, it is necessary to connect all the wiring conductors 75 on which the plating layer is to be deposited to the plating electrode 87.
As an example of connecting all the wiring conductors 75 to the plating electrode 87, in FIG. 2 and FIG. 3 of Patent Document 1, a technique such as a smooth wiring 16 (staggered wiring) is used, and the input / output terminals 14 of each electrode portion are used. A technique is described in which the continuous wiring 16 is subjected to plating at the same time, and then the continuous wiring 16 is divided by breaking or cutting into the single product 20.

FIG. 12 is a plan view for explaining a method of connecting each wiring conductor 75 of the multi-piece wiring board 70 to the plating electrode 87 using the smooth wiring of Patent Document 1, and FIG. 12 (a) is on the insulating layer 71b. FIG. 12B is a partial plan view for explaining a method of connecting the wiring conductor 75 on the lower surface 77 connected to the wiring conductor 75 on the insulating layer 71b and the wiring conductor 75 on the insulating layer 71b to the plating electrode 87. FIG. FIG. 10 is a partial plan view for explaining a method of connecting the wiring conductor 75 of the lower surface 77 connected to the wiring conductor 75 and the wiring conductor 75 on the insulating layer 71 c to the plating electrode 87.
In FIG. 12A, a rectangular frame-shaped common conductor frame 90 for plating is formed in the disposal margin region 85 on the outer periphery of the insulating layer 71b. The plating common conductor frame 90 is connected to the plating electrode 87. Between the adjacent wiring board region 72 and the wiring board region 72, a connecting conductor 91 is formed which meanders while alternately drawing a folded pattern on the left and right sides of the boundary line 84 and both ends are connected to the plating common conductor frame 90. ing.
An opening 92 for forming the cavity 73 is formed at the center of each wiring board region 72, and a wiring conductor 75 extending from the periphery of the opening 92 to the boundary line 84 of the wiring board region 72 is formed. Among the wiring conductors 75, the one extending to the boundary line 84 with the disposal margin region 85 is connected to the plating common conductor frame 90 via the lead line 93. Among the wiring conductors 75, the one extending to the boundary line 84 between the adjacent wiring board region 72 and the wiring board region 72 is connected to the connecting conductor 91.
In this way, the wiring conductor 75 on the insulating layer 72b is connected to the plating electrode 87 via the lead wire 93, the connecting conductor 91, and the plating common conductor frame 90. Similarly, the wiring conductor 75 on the insulating layer 71c shown in FIG. 12B is also connected to the plating electrode 87 through the lead wire 93, the plating connecting conductor 91, and the plating common conductor frame 90.
Further, the wiring conductor 75 on the lower surface 77 is connected to the plating electrode 87 by being connected to either the wiring conductor 75 on the insulating layer 72 b or the wiring conductor 75 on the insulating layer 72 c through the via 76. It will be. By connecting the plating electrode 87 to a plating power source, a plated metal layer by electrolytic plating is deposited on the exposed surface of the wiring conductor 75.

  The wiring conductors 75 adjacent to each other in the wiring board regions 72 electrically connected via the connecting conductors 91 divide the ceramic multilayer substrate 71 into the wiring board regions 72, and then the connecting conductors 91 are folded back. By being divided into units, each becomes electrically independent from each other.

JP-A-11-214832

The wiring conductor 75 on the insulating layer 71b and the wiring conductor 75 on the insulating layer 71c differ in the number, width, length, etc. of the normal wiring conductors. Therefore, the electrical resistance of the plating circuit of the insulating layer 71b composed of the connecting conductor 91 on the insulating layer 71b and the wiring conductor 75 connected thereto, and the connecting conductor 91 on the insulating layer 71c and the wiring conductor connected thereto. This is different from the electrical resistance of the plating circuit of the insulating layer 71c composed of 75. Even if this difference in electric resistance is small in one wiring board area unit, in the multi-cavity wiring board in which many wiring board areas are formed for the purpose of improving production efficiency in recent years, the plating of the insulating layer 71b is performed. The difference between the electric resistance of the circuit for use and the electric resistance of the plating circuit for the insulating layer 71c becomes large.
Then, by immersing the multi-piece wiring board 70 in an electrolytic plating bath and connecting the plating electrode 87 to a power source for plating, when a plating metal layer is deposited on all the wiring conductors 75, the insulating layer 71b is covered. There is a difference between the thickness of the plating metal layer deposited on the wiring conductor 75 connected to the connecting conductor 91 and the thickness of the plating metal layer deposited on the wiring conductor 75 connected to the connecting conductor 91 on the insulating layer 71c. Therefore, it is difficult to deposit a plated metal layer having a predetermined thickness on all the wiring conductors 75.

  The present invention has been devised in view of such conventional problems, and its purpose is to reduce the variation in the thickness of the plated metal layer applied to each wiring conductor and to provide a predetermined thickness for all wiring conductors. An object of the present invention is to provide a multi-piece wiring board capable of depositing the plated metal layer by electrolytic plating.

The multi-cavity wiring board according to claim 1 of the present invention for solving the above problems is
A multilayer substrate in which a plurality of insulating layers are laminated;
A product area in which the wiring board area located at the center of the multilayer board and arranged by the boundary line is arranged vertically and horizontally;
Located on the outer periphery of the product area, abandon area having a plating electrode,
The meandering region is formed on the first insulating layer of the insulating layers, and has a meandering pattern having a folded pattern alternately and continuously arranged on the left and right of the boundary line, and at least one end is connected to the plating electrode. A first connecting conductor;
The meandering region is formed on the second insulating layer of the insulating layers, and has a meandering pattern having a folded pattern alternately and continuously arranged on the left and right of the boundary line, and at least one end is connected to the plating electrode. A second connecting conductor;
A wiring conductor formed on the first insulating layer and having one end connected to one of the folded patterns of the first connecting conductor;
A multi-cavity wiring board having a wiring conductor formed on the second insulating layer and having one end connected to one of the folded patterns of the second connecting conductor,
At least one of the first connection conductor and the second connection conductor has a folded pattern that is not connected to the wiring conductor;
The folded pattern that is not connected to the wiring conductor is connected to a folded pattern formed on a different insulating layer in the same wiring board region with a via.

Moreover, the multi-cavity wiring board according to claim 2 of the present invention for solving the above problems is
The first connecting conductor is formed by the meandering region and a loop surrounding an intersection of a vertical boundary line and a horizontal boundary line on the first insulating layer,
The second connecting conductor is formed by the meandering region and a loop surrounding an intersection of a vertical boundary line and a horizontal boundary line on the second insulating layer;
The multi-piece wiring board according to claim 1, wherein the loop of the first connecting conductor and the loop of the second connecting conductor are connected by vias.

According to the multi-cavity wiring board according to claim 1 of the present invention, at least one of the first connecting conductor and the second connecting conductor has a folded pattern that is not connected to the wiring conductor, and is not connected to the wiring conductor. The folded pattern is connected to the folded pattern formed on different insulating layers in the same wiring board region by vias.
For this reason, the electrical resistance of the circuit for plating comprised by the 1st connection conductor and the wiring conductor connected to it, and the electrical resistance of the circuit for plating comprised by the 2nd connection conductor and the wiring conductor connected to it, The difference can be very small. Therefore, the difference between the plating thickness deposited on the wiring conductor on the first insulating layer and the plating thickness deposited on the wiring conductor on the second insulating layer can be made extremely small.
Further, when the wiring conductor is connected to both the folded pattern on the first insulating layer and the folded pattern on the second insulating layer connected by vias, even after dividing the multilayer board into each wiring board region, Through the vias, the wiring conductors on different insulating layers in the same wiring board region are not divided and remain short-circuited. For this reason, the wiring conductor is not connected to at least one of the folded patterns connected to each other by vias, so that after the multilayer substrate is divided into the respective wiring substrate regions, different insulations in the same wiring substrate region are provided via the vias. The wiring conductors on the layer are not short-circuited.

According to the multiple wiring substrate according to claim 2 of the present invention, a loop is formed in each of the first connecting conductor and the second connecting conductor according to claim 1, and the loop of the first connecting conductor and the second connecting conductor are formed. Two connecting conductor loops are connected by vias.
For this reason, the electric resistance of the circuit for plating comprised by the 1st connection conductor and the 1st wiring conductor connected to it, and the circuit for plating comprised by the 2nd connection conductor and the 2nd wiring conductor connected to it The difference from the electrical resistance can be further reduced. Therefore, the difference between the plating thickness applied to the wiring conductor on the first insulating layer and the plating thickness applied to the wiring conductor on the second insulating edge layer can be further reduced.

The top view of the multi-cavity wiring board which concerns on Embodiment 1 of this invention Sectional drawing along the AA line of FIG. 3A is a partial plan view of the insulating layer 1b of the multi-cavity wiring board 10 of FIG. 1, and FIG. 3B is a partial plan view of the insulating layer 1c of the multi-cavity wiring board 10 of FIG. FIG. 4A is a partially enlarged view for explaining the configuration of the first connecting conductor 21-1 in FIG. 3A, and FIG. 4B shows the second connecting conductor 21-2 in FIG. Partial enlarged view for explaining the configuration 5A is a partial plan view of the insulating layer 1b of the multi-piece wiring board 10 according to the second embodiment of the present invention, and FIG. 5B is a partial plan view of the insulating layer 1c. 6A is a partially enlarged view for explaining the configuration of the first connection conductor 21-1 in FIG. 5A, and FIG. 6B is a view of the second connection conductor 21-2 in FIG. 5B. Partial enlarged view for explaining the configuration Partial enlarged view of multi-cavity wiring board according to Embodiment 3 of the present invention The elements on larger scale which show the modification of Embodiment 1 of this invention Cross-sectional view of a small wiring board used for electronic component storage packages Plan view of a conventional multi-cavity wiring board Sectional drawing along the AA line of FIG. 12A is a partial plan view of the insulating layer 71b of the multi-piece wiring board 70 of FIG. 10, and FIG. 12B is a partial plan view of the insulating layer 71c of the multi-piece wiring board 70 of FIG.

[Embodiment 1]
Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a multi-piece wiring board according to the present invention, FIG. 2 is a cross-sectional view taken along the line AA in FIG. 1, and a plurality of insulating layers 1a to 1d made of a ceramic sintered body such as alumina are provided. The laminated ceramic multilayer substrate 1 is used. A plurality of wiring board regions 2 that become wiring boards after division are arranged vertically and horizontally in the central portion of the ceramic multilayer substrate 1, and a disposal margin area 15 that is separated from the wiring board region 2 at the time of division is formed on the outer periphery. Each of the wiring board regions 2 has a cavity 3 for accommodating electronic components on the upper surface thereof, and a plurality of steps 4 are provided in the cavity 3. A plurality of wiring conductors 5 formed by printing / baking a conductive paste such as tungsten or molybdenum is provided on each step 4. The wiring conductor 5 is connected to the wiring conductor 5 on the lower surface 7 of the wiring board region 2 through a via 6 penetrating the insulating layers 1a to 1c.
Then, a plating layer 8 composed of, for example, a nickel plating layer having a thickness of about 1 to 10 μm and a gold plating layer having a thickness of about 0.1 to 3 μm is deposited on the exposed surface of each wiring conductor 5 by an electrolytic plating method. Yes.
1 and FIG. 2, two steps 4-1 and 4-2 are provided in the cavity 3, and the first wiring conductor 5-1 and the second wiring are provided on each step. A conductor 5-2 is provided.
A cutout 16 is formed on the side surface of the discard margin region 15, and a plating electrode 17 made of a conductor layer is formed along the inner wall of the cutout 16. By connecting the plating electrode 17 to a plating power source, a charge for electrolytic plating is applied to the exposed surfaces of all the wiring conductors.

Next, FIG. 3 and FIG. 4 are used to explain the procedure of this embodiment in which all the wiring conductors 5 are connected to the plating electrodes 17 in order to deposit the nickel plating layer or the gold plating layer on each wiring conductor 5 by electrolytic plating. It explains using. 3A is a partial plan view of the insulating layer 1b of the multi-piece wiring board 10 according to the present embodiment, FIG. 3B is a partial plan view of the insulating layer 1c, and FIG. 4A is a first connecting conductor. FIG. 4B is a partially enlarged view for explaining the configuration of the second connecting conductor 21-2.
In FIG. 3A, a rectangular frame-shaped common conductor frame 20 for plating is formed in the discard margin region 15 on the outer periphery of the insulating layer 1b. The plating common conductor frame 20 is connected to the plating electrode 17. Between the adjacent wiring board area | regions 2 and the wiring board area | region 2, the 1st connection conductor 21 which has the meandering area | region which consists of the substantially U-shaped folding pattern 24 arrange | positioned alternately on either side of the boundary line 14 continuously. -1 is formed, and both ends of the first connecting conductor 21-1 are connected to the common conductor frame 20 for plating via lead wires 23. Incidentally, the number of the lead lines 23 may be one as shown in FIG. 3, or may be branched into two as shown in FIG.
An opening 22 for forming the cavity 3 is formed at the center of each wiring board region 2, and a first wiring conductor 5-1 extending from the periphery of the opening 22 to the boundary line 14 of the wiring board region 2 is formed. . The first wiring conductor 5-1 is connected to the wiring conductor 5 on the lower surface 7 of the wiring board region 2 through the via 6.
Among the first wiring conductors 5-1, the one extending to the boundary line 14 with the disposal margin region 15 is connected to the plating common conductor frame 20 through the lead wire 23. Among the first wiring conductors 5-1, the one extending to the boundary line 14 between the adjacent wiring board region 2 and the wiring board region 2 is included in the folded pattern 24 a (see FIG. 4) of the first connection conductor 21-1. Connected to one.
In this way, the first wiring conductor 5-1 and the wiring conductor 5 on the lower surface 7 connected to the first wiring conductor 5-1 via the via 6 are connected to the lead wire 23 and the first connecting conductor 21-1. The plating electrode 17 is connected via the plating common conductor frame 20.
Similarly, the second wiring conductor 5-2 shown in FIG. 3B and the wiring conductor 5 on the lower surface 7 connected to the second wiring conductor 5-2 through the via 6 are the lead wire 23, the second wiring conductor 5 and the second wiring conductor 5-2. It is connected to the plating electrode 17 through the connecting conductor 21-2 and the common conductor frame 20 for plating.
By connecting the plating electrode 17 to a plating power source, the plating layer 8 by electrolytic plating is deposited on the exposed surface of the wiring conductor 5. Then, the adjacent wiring conductors 5 of each wiring board region 2 electrically connected via the connecting conductors 21-1 and 21-2, after dividing the ceramic multilayer substrate 1 into each wiring board region 2, The connection conductors 21-1 and 21-2 are divided into folded pattern units, so that they are electrically independent from each other.

As shown in FIG. 4A, the multi-piece wiring board 10 includes a folded pattern 24a in which the first connection conductor 21-1 is connected to the first wiring conductor 5-1, and the first wiring conductor 5-1. The folded pattern 24b is not connected to the. Similarly, as shown in FIG. 4B, the second connecting conductor 21-2 has a folded pattern 24c connected to the second wiring conductor 5-2 and a folded pattern not connected to the second wiring conductor 5-2. 24d. The folded pattern 24b that is not connected to the first wiring conductor 5-1 and the folded pattern 24d that is not connected to the second wiring conductor 5-2 are formed at substantially the same position in plan view and are connected by the via 25. .
For this reason, the circuit for plating comprised by the 1st connection conductor 21-1 and the 1st wiring conductor 5-1 connected to it, the 2nd connection conductor 21-2, and the 2nd wiring conductor 5- connected to it 2 is short-circuited by the via 25, the difference in electrical resistance between the two plating circuits can be made extremely small. Therefore, the difference between the plating thickness deposited on the first wiring conductor 5-1 and the plating thickness deposited on the second wiring conductor 5-2 can be made extremely small.
Further, when the wiring conductor 5 (5-1, 5-2) is connected to the folded pattern 24b and the folded pattern 24d connected by the via 25, the ceramic multilayer substrate 1 is divided into the respective wiring substrate regions 2. In addition, the wiring conductors 5-1 and 5-2 on different insulating layers in the same wiring board region are not divided and are short-circuited via the via 25. For this reason, by not connecting the wiring conductors 5-1 and 5-2 to the folded patterns 24 b and 24 d connected to each other by the via 25, the via 25 is formed after the multilayer substrate 1 is divided into the wiring substrate regions 2. Thus, the wiring conductors 5-1 and 5-2 on different insulating layers in the same wiring board region are not short-circuited.

[Embodiment 2]
In the first embodiment, the folded patterns 24b and 24d that are not connected to the wiring conductor 5 are formed on both the first connecting conductor 21-1 and the second connecting conductor 21-2, and the folded patterns 24b and 24d are connected to each other through the via 25. Was. On the other hand, in the second embodiment, as shown in FIGS. 5 to 6, the first connecting conductor 21-1 has the folded pattern 24 a connected to the first wiring conductor 5-1 and the first wiring conductor 5-1. The second connection conductor 21-2 has only the folding pattern 24c connected to the second wiring conductor 5-2, whereas the folding pattern 24b is not connected to the second wiring conductor 5-2. The folded pattern 24b not connected to the first wiring conductor 5-1 is connected by a via 25 to the folded pattern 24c connected to the second wiring conductor 5-2.
Also in the present embodiment, a plating circuit composed of the first connecting conductor 21-1 and the first wiring conductor 5-1 connected thereto, and the second connecting conductor 21-2 and the second wiring connected thereto. The difference in electrical resistance of the plating circuit composed of the conductor 5-2 can be made extremely small, and the plating thickness deposited on the first wiring conductor 5-1 and the second wiring conductor 5-2 The difference in the plating thickness to be deposited can be made extremely small.
Further, as in the present embodiment, the multilayer substrate 1 is also divided into the respective wiring substrate regions 2 by not connecting the wiring conductor 5-1 to only one of the folded patterns 24b connected to each other by the via 25. It is possible to prevent the wiring conductors 5-1 and 5-2 on different insulating layers in the same wiring board region from being short-circuited via the via 25 later.

[Embodiment 3]
In the first embodiment and the second embodiment, the first connection conductor 21-1 and the second connection conductor 21-2 are all formed in a meandering region. On the other hand, in this embodiment, the first connecting conductor 21-1 and the second connecting conductor 21-2 are connected to the first meandering region 26-1 and the second meandering region 26-2 as shown in FIG. The loops 28-1 and 28-2 surround the intersection 27 of the boundary line 14y and the horizontal boundary line 14x, and the first loop 28-1 and the second connection conductor 21-2 of the first connection conductor 21-1 are formed. The second loop 28-2 is connected by a via 29.
For this reason, the electrical resistance of the circuit for plating comprised by the 1st connection conductor 21-1 and the 1st wiring conductor 5-1 connected to it, the 2nd connection conductor 21-2, and the 2nd wiring connected to it The difference with the electric resistance of the circuit for plating comprised with the conductor 5-2 can be made still smaller. Therefore, the difference between the plating thickness applied to the first wiring conductor 5-1 and the plating thickness applied to the second wiring conductor 5-2 can be further reduced.

(Example)
First, a multi-piece wiring board 10 before plating shown in FIGS. 1 to 4 was prepared. Next, the resistance value from the first internal electrode 11-1 to the plating electrode 17 and the resistance value from the second internal electrode 11-2 to the plating electrode 17 for an arbitrary wiring board region 2 of the prepared multi-piece wiring board 10. The value was measured. Next, after connecting a plating power source to the plating electrode 17 and performing nickel plating by an electrolytic plating method, the thickness of the nickel plating formed on the internal electrodes 11-1 and 11-2 where the resistance values were measured is measured. did. The results are shown in Table 1.
As a comparative example, a multi-cavity wiring board 70 before plating shown in FIGS. 10 to 12 was prepared, and the wiring board area 72 at the same position as the wiring board area 2 where the resistance value was measured was measured on the insulating layer 71b. A resistance value from the electrode 81 (corresponding to the first internal electrode 11-1) to the plating electrode 87, and a resistance value from the internal electrode 81 (corresponding to the second internal electrode 11-2) on the insulating layer 71c to the plating electrode 87 Was measured. Next, a plating power source was connected to the plating electrode 87 and nickel plating was performed by an electrolytic plating method, and then the thickness of the nickel plating formed on the internal electrode 81 where the resistance value was measured was measured. The results are shown in Table 1.

  As shown in Table 1, in the multi-cavity wiring board of the example, the difference in resistance value between the first internal electrode and the second internal electrode is reduced as compared with the comparative example, and nickel deposited on the first internal electrode It was confirmed that the difference between the thickness of the plating and the thickness of the nickel plating formed on the second electrode was reduced.

  In this embodiment, the thickness variation when nickel plating is described, but it goes without saying that the thickness variation of gold plating when gold plating is performed on nickel plating can also be reduced.

DESCRIPTION OF SYMBOLS 1 ... Ceramic multilayer substrate 1a, 1b, 1c, 1d ... Insulating layer 2 ... Wiring board area | region 3 ... Cavity 4, 4-1, 4-2 ... Level | step difference 5 ... Wiring conductor 5-1 ... 1st wiring conductor 5-2 ... 2nd wiring conductor 6 ... Via 7 ... Bottom surface 8 ... Plating layer 10 ... Multi-cavity wiring substrate 11-1 ... First internal electrode 11-2 ... Second internal electrode 12 ... External electrode 14 ... Boundary line 15 ... Disposal allowance area DESCRIPTION OF SYMBOLS 16 ... Notch 17 ... Plating electrode 20 ... Common conductor frame for plating 21-1 ... 1st connection conductor 21-2 ... 2nd connection conductor 22 ... Opening 23 ... Lead wire 24, 24a, 24b, 24c, 24d ... Folding pattern 25 ... via 26-1 ... first meandering region 26-2 ... second meandering region 27 ... intersection 28-1 ... first loop 28-2 ... second loop 29 ... via

Claims (2)

A multilayer substrate in which a plurality of insulating layers are laminated;
A product area in which the wiring board area located at the center of the multilayer board and arranged by the boundary line is arranged vertically and horizontally;
Located on the outer periphery of the product area, abandon area having a plating electrode,
The meandering region is formed on the first insulating layer of the insulating layers, and has a meandering pattern having a folded pattern alternately and continuously arranged on the left and right of the boundary line, and at least one end is connected to the plating electrode. A first connecting conductor;
The meandering region is formed on the second insulating layer of the insulating layers, and has a meandering pattern having a folded pattern alternately and continuously arranged on the left and right of the boundary line, and at least one end is connected to the plating electrode. A second connecting conductor;
A wiring conductor formed on the first insulating layer and having one end connected to one of the folded patterns of the first connecting conductor;
A multi-cavity wiring board having a wiring conductor formed on the second insulating layer and having one end connected to one of the folded patterns of the second connecting conductor,
At least one of the first connection conductor and the second connection conductor has a folded pattern that is not connected to the wiring conductor;
A multi-piece wiring board, wherein the folded pattern not connected to the wiring conductor is connected to a folded pattern formed on a different insulating layer in the same wiring board region by a via. The first connecting conductor is formed by the meandering region and a loop surrounding an intersection of a vertical boundary line and a horizontal boundary line on the first insulating layer,
The second connecting conductor is formed by the meandering region and a loop surrounding an intersection of a vertical boundary line and a horizontal boundary line on the second insulating layer;
The multi-piece wiring board according to claim 1, wherein the loop of the first connection conductor and the loop of the second connection conductor are connected by a via.

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